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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231023-display-support-v1-14-5c860ed5c33b@baylibre.com> References: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> In-Reply-To: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , Xinlei Lee , CK Hu , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Catalin Marinas , Will Deacon Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pwm@vger.kernel.org, Alexandre Mergnat , Fabien Parent X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5504; i=amergnat@baylibre.com; h=from:subject:message-id; bh=gNNMmG/tic5FCAz01Mxk94pBODEehb9j1DvbosxWwjM=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBlNoXPtvxxoh6jBrTsWy5g9sqziSKeYRBQSeK2X9qj pLF6+oGJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZTaFzwAKCRArRkmdfjHURTkGD/ 9aHtaIPalJ9hCBJVp5Cm+eMJS63WzvlzUNGpmZTUXItS7gLNhiSr5M9Ygkx2cEbtyjitdJsef3ebnI CbVf/pWb3thpVnIj2emA0T4Ft/AvZDt5A69fkPmF0PrrVI1d7IPf336AX5AIsJKIlB+cchIXGi4oOh VcSTryoyVCGkKCmID4fVfNyVHV1Fxw1dTipJbS12OvX9fwfCclZHjoikr/B8G6xSopAC66omgAJTbD GJ/nV8ATBffGjCldK8zWsdXhnhMdOVG4nJgjN18FH8IgkPRd8e4/U6SX0Qj/NdTphyWitHWxmt8a3J 2LyqB+lcQ49WBFaLOs7qxG1u1ZCZyElHol4PLbjye0nJdWyNlnMW7yTbODQgwaMpJ4s0/SHlV2+c6o 4Z0L64Ie/RWZdHX3gXB2q+MZJKcx7lpbST/D3q4GumpmPewlHH95Z8ewyluHzWINNM4FSfWCszIE/a I9xFyVeZB1Qo1hzvaVrEj+u9Wtko52r9LNrmvJi+Yds9DdVxwMkDwuPGCF3SdSeEv/sHVvPbrGkXTw Ni1R85QW/UwDwmlAqvlu6ntr0MwqOwZ6Qy6BTGrKnXRTfxP9iAlV3E1beT/pOqKF0gY69zplnECvOy j9CUjsKAn7VaC/s6pr6m0Yx1QK6UQhrO3tl4u84dpMgDExKgpTM/DcDiEkCQ== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Fabien Parent MT8365 requires an additional clock for DPI. Add support for that additional clock. Signed-off-by: Fabien Parent Signed-off-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_dpi.c | 50 ++++++++++++++++++++++++++++++++++= +++- 1 file changed, 49 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 2f931e4e2b60..ddd7c54febe6 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -70,6 +70,7 @@ struct mtk_dpi { struct device *mmsys_dev; struct clk *engine_clk; struct clk *pixel_clk; + struct clk *dpi_clk; struct clk *tvd_clk; int irq; struct drm_display_mode mode; @@ -137,6 +138,7 @@ struct mtk_dpi_yc_limit { * @csc_enable_bit: Enable bit of CSC. * @pixels_per_iter: Quantity of transferred pixels per iteration. * @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to= be set in MMSYS. + * @is_dpi_clk_req: Support the additionnal DPI clock. */ struct mtk_dpi_conf { unsigned int (*cal_factor)(int clock); @@ -156,6 +158,7 @@ struct mtk_dpi_conf { u32 csc_enable_bit; u32 pixels_per_iter; bool edge_cfg_in_mmsys; + bool is_dpi_clk_req; }; =20 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mas= k) @@ -472,6 +475,7 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi) mtk_dpi_disable(dpi); clk_disable_unprepare(dpi->pixel_clk); clk_disable_unprepare(dpi->engine_clk); + clk_disable_unprepare(dpi->dpi_clk); } =20 static int mtk_dpi_power_on(struct mtk_dpi *dpi) @@ -481,10 +485,16 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) if (++dpi->refcount !=3D 1) return 0; =20 + ret =3D clk_prepare_enable(dpi->dpi_clk); + if (ret) { + dev_err(dpi->dev, "failed to enable dpi clock: %d\n", ret); + goto err_refcount; + } + ret =3D clk_prepare_enable(dpi->engine_clk); if (ret) { dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret); - goto err_refcount; + goto err_engine; } =20 ret =3D clk_prepare_enable(dpi->pixel_clk); @@ -497,6 +507,8 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) =20 err_pixel: clk_disable_unprepare(dpi->engine_clk); +err_engine: + clk_disable_unprepare(dpi->dpi_clk); err_refcount: dpi->refcount--; return ret; @@ -902,6 +914,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .channel_swap_shift =3D CH_SWAP, .yuv422_en_bit =3D YUV422_EN, .csc_enable_bit =3D CSC_ENABLE, + .is_dpi_clk_req =3D false, }; =20 static const struct mtk_dpi_conf mt2701_conf =3D { @@ -920,6 +933,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .channel_swap_shift =3D CH_SWAP, .yuv422_en_bit =3D YUV422_EN, .csc_enable_bit =3D CSC_ENABLE, + .is_dpi_clk_req =3D false, }; =20 static const struct mtk_dpi_conf mt8183_conf =3D { @@ -937,6 +951,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .channel_swap_shift =3D CH_SWAP, .yuv422_en_bit =3D YUV422_EN, .csc_enable_bit =3D CSC_ENABLE, + .is_dpi_clk_req =3D false, }; =20 static const struct mtk_dpi_conf mt8186_conf =3D { @@ -969,6 +984,7 @@ static const struct mtk_dpi_conf mt8188_dpintf_conf =3D= { .channel_swap_shift =3D DPINTF_CH_SWAP, .yuv422_en_bit =3D DPINTF_YUV422_EN, .csc_enable_bit =3D DPINTF_CSC_ENABLE, + .is_dpi_clk_req =3D false, }; =20 static const struct mtk_dpi_conf mt8192_conf =3D { @@ -986,6 +1002,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .channel_swap_shift =3D CH_SWAP, .yuv422_en_bit =3D YUV422_EN, .csc_enable_bit =3D CSC_ENABLE, + .is_dpi_clk_req =3D false, }; =20 static const struct mtk_dpi_conf mt8195_dpintf_conf =3D { @@ -1000,6 +1017,25 @@ static const struct mtk_dpi_conf mt8195_dpintf_conf = =3D { .channel_swap_shift =3D DPINTF_CH_SWAP, .yuv422_en_bit =3D DPINTF_YUV422_EN, .csc_enable_bit =3D DPINTF_CSC_ENABLE, + .is_dpi_clk_req =3D false, +}; + +static const struct mtk_dpi_conf mt8365_conf =3D { + .cal_factor =3D mt8183_calculate_factor, + .channel_swap_shift =3D CH_SWAP, + .csc_enable_bit =3D CSC_ENABLE, + .dimension_mask =3D HPW_MASK, + .hvsize_mask =3D HSIZE_MASK, + .is_ck_de_pol =3D true, + .is_dpi_clk_req =3D true, + .max_clock_khz =3D 150000, + .num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts), + .output_fmts =3D mt8183_output_fmts, + .pixels_per_iter =3D 1, + .reg_h_fre_con =3D 0xe0, + .support_direct_pin =3D true, + .swap_input_support =3D true, + .yuv422_en_bit =3D YUV422_EN, }; =20 static int mtk_dpi_probe(struct platform_device *pdev) @@ -1056,6 +1092,17 @@ static int mtk_dpi_probe(struct platform_device *pde= v) return dev_err_probe(dev, PTR_ERR(dpi->tvd_clk), "Failed to get tvdpll clock\n"); =20 + if (dpi->conf->is_dpi_clk_req) { + dpi->dpi_clk =3D devm_clk_get(dev, "dpi"); + if (IS_ERR(dpi->dpi_clk)) { + ret =3D PTR_ERR(dpi->dpi_clk); + if (ret !=3D -EPROBE_DEFER) + dev_err(dev, "Failed to get dpi clock: %d\n", ret); + + return ret; + } + } + dpi->irq =3D platform_get_irq(pdev, 0); if (dpi->irq < 0) return dpi->irq; @@ -1097,6 +1144,7 @@ static const struct of_device_id mtk_dpi_of_ids[] =3D= { { .compatible =3D "mediatek,mt8188-dp-intf", .data =3D &mt8188_dpintf_con= f }, { .compatible =3D "mediatek,mt8192-dpi", .data =3D &mt8192_conf }, { .compatible =3D "mediatek,mt8195-dp-intf", .data =3D &mt8195_dpintf_con= f }, + { .compatible =3D "mediatek,mt8365-dpi", .data =3D &mt8365_conf }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids); --=20 2.25.1