From nobody Wed Dec 17 10:06:00 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6233FC001DF for ; Fri, 20 Oct 2023 15:00:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377633AbjJTPAh (ORCPT ); Fri, 20 Oct 2023 11:00:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37690 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377554AbjJTPAa (ORCPT ); Fri, 20 Oct 2023 11:00:30 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EA31FD5D; Fri, 20 Oct 2023 08:00:27 -0700 (PDT) Received: from jupiter.universe (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sre) by madras.collabora.co.uk (Postfix) with ESMTPSA id 64C32660737B; Fri, 20 Oct 2023 16:00:26 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1697814026; bh=K+0lTyZ8qgIAV5y3w5nBjySn4RnIUfEpHKakMzY0RXw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=f4aNpQIay1c/DlzV39XL7teswYsy+XOUcc6z2UhE9Z5b9Mmh9Jcaahk5ZEY1Snm4R TF2F0t8cjWTU+QdC0g/fGt+UOp4yDhKsLds9ntXcqJjCvSD31qyiuokFEtIT0CIoxj CnHuFvYferPRoOLD8r6kuIEpl+QWX6jpgHAin9kALEvQkEYcS7xfQZ/J/iN49v301f sjabKyb+/fzyqAaMpKyzfM50Ihv51fes7Dgrd1ZrLqYLTXK+yJPB5J8upWLkaPYRwK QQTNh5UMVo53kvxJUzCq9x5GLudUr5uTX8vBfWwNe5Ea6CLkVuy5qqby9+D2Q4g+fX D7yJwz8RtA4CA== Received: by jupiter.universe (Postfix, from userid 1000) id 087F2480104; Fri, 20 Oct 2023 17:00:24 +0200 (CEST) From: Sebastian Reichel To: Heiko Stuebner , Greg Kroah-Hartman Cc: Thinh Nguyen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-rockchip@lists.infradead.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v4 2/3] usb: dwc3: add optional PHY interface clocks Date: Fri, 20 Oct 2023 16:11:41 +0200 Message-ID: <20231020150022.48725-3-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231020150022.48725-1-sebastian.reichel@collabora.com> References: <20231020150022.48725-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" On Rockchip RK3588 one of the DWC3 cores is integrated weirdly and requires two extra clocks to be enabled. Without these extra clocks hot-plugging USB devices is broken. Signed-off-by: Sebastian Reichel Acked-by: Thinh Nguyen --- drivers/usb/dwc3/core.c | 28 ++++++++++++++++++++++++++++ drivers/usb/dwc3/core.h | 4 ++++ 2 files changed, 32 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 343d2570189f..639b768c3386 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -854,8 +854,20 @@ static int dwc3_clk_enable(struct dwc3 *dwc) if (ret) goto disable_ref_clk; =20 + ret =3D clk_prepare_enable(dwc->utmi_clk); + if (ret) + goto disable_susp_clk; + + ret =3D clk_prepare_enable(dwc->pipe_clk); + if (ret) + goto disable_utmi_clk; + return 0; =20 +disable_utmi_clk: + clk_disable_unprepare(dwc->utmi_clk); +disable_susp_clk: + clk_disable_unprepare(dwc->susp_clk); disable_ref_clk: clk_disable_unprepare(dwc->ref_clk); disable_bus_clk: @@ -865,6 +877,8 @@ static int dwc3_clk_enable(struct dwc3 *dwc) =20 static void dwc3_clk_disable(struct dwc3 *dwc) { + clk_disable_unprepare(dwc->pipe_clk); + clk_disable_unprepare(dwc->utmi_clk); clk_disable_unprepare(dwc->susp_clk); clk_disable_unprepare(dwc->ref_clk); clk_disable_unprepare(dwc->bus_clk); @@ -1785,6 +1799,20 @@ static int dwc3_get_clocks(struct dwc3 *dwc) } } =20 + /* specific to Rockchip RK3588 */ + dwc->utmi_clk =3D devm_clk_get_optional(dev, "utmi"); + if (IS_ERR(dwc->utmi_clk)) { + return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk), + "could not get utmi clock\n"); + } + + /* specific to Rockchip RK3588 */ + dwc->pipe_clk =3D devm_clk_get_optional(dev, "pipe"); + if (IS_ERR(dwc->pipe_clk)) { + return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk), + "could not get pipe clock\n"); + } + return 0; } =20 diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index a69ac67d89fe..f5e6ae6e394e 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -991,6 +991,8 @@ struct dwc3_scratchpad_array { * @bus_clk: clock for accessing the registers * @ref_clk: reference clock * @susp_clk: clock used when the SS phy is in low power (S3) state + * @utmi_clk: clock used for USB2 PHY communication + * @pipe_clk: clock used for USB3 PHY communication * @reset: reset control * @regs: base address for our registers * @regs_size: address space size @@ -1156,6 +1158,8 @@ struct dwc3 { struct clk *bus_clk; struct clk *ref_clk; struct clk *susp_clk; + struct clk *utmi_clk; + struct clk *pipe_clk; =20 struct reset_control *reset; =20 --=20 2.42.0