From nobody Wed Dec 17 09:44:32 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1640C001DF for ; Fri, 20 Oct 2023 10:37:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376939AbjJTKhu convert rfc822-to-8bit (ORCPT ); Fri, 20 Oct 2023 06:37:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34718 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376775AbjJTKht (ORCPT ); Fri, 20 Oct 2023 06:37:49 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 479EED5A; Fri, 20 Oct 2023 03:37:46 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 92D2224E13F; Fri, 20 Oct 2023 18:37:44 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 20 Oct 2023 18:37:44 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 20 Oct 2023 18:37:43 +0800 From: William Qiu To: , , , CC: Emil Renner Berthing , Rob Herring , Thierry Reding , Philipp Zabel , Krzysztof Kozlowski , Conor Dooley , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , "Hal Feng" , Paul Walmsley , Palmer Dabbelt , Albert Ou , William Qiu Subject: [PATCH v6 1/4] dt-bindings: pwm: Add OpenCores PWM module Date: Fri, 20 Oct 2023 18:37:38 +0800 Message-ID: <20231020103741.557735-2-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020103741.557735-1-william.qiu@starfivetech.com> References: <20231020103741.557735-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add documentation to describe OpenCores Pulse Width Modulation controller driver. Signed-off-by: William Qiu Reviewed-by: Krzysztof Kozlowski Reviewed-by: Hal Feng --- .../bindings/pwm/opencores,pwm-ocores.yaml | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/opencores,pwm-oco= res.yaml diff --git a/Documentation/devicetree/bindings/pwm/opencores,pwm-ocores.yam= l b/Documentation/devicetree/bindings/pwm/opencores,pwm-ocores.yaml new file mode 100644 index 000000000000..0f6a3434f155 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/opencores,pwm-ocores.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/opencores,pwm-ocores.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OpenCores PWM controller + +maintainers: + - William Qiu + +description: + OpenCores PTC ip core contains a PWM controller. When operating in PWM m= ode, the PTC core + generates binary signal with user-programmable low and high periods. All= PTC counters and + registers are 32-bit. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + enum: + - opencores,pwm-ocores + - starfive,jh71x0-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + "#pwm-cells": + const: 3 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + pwm@12490000 { + compatible =3D "opencores,pwm-ocores"; + reg =3D <0x12490000 0x10000>; + clocks =3D <&clkgen 181>; + resets =3D <&rstgen 109>; + #pwm-cells =3D <3>; + }; --=20 2.34.1 From nobody Wed Dec 17 09:44:32 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31105CDB474 for ; Fri, 20 Oct 2023 10:38:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376986AbjJTKh7 convert rfc822-to-8bit (ORCPT ); Fri, 20 Oct 2023 06:37:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34770 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376932AbjJTKhu (ORCPT ); Fri, 20 Oct 2023 06:37:50 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 286EBD46; Fri, 20 Oct 2023 03:37:47 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 6BC9D24E346; Fri, 20 Oct 2023 18:37:45 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 20 Oct 2023 18:37:45 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 20 Oct 2023 18:37:44 +0800 From: William Qiu To: , , , CC: Emil Renner Berthing , Rob Herring , Thierry Reding , Philipp Zabel , Krzysztof Kozlowski , Conor Dooley , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , "Hal Feng" , Paul Walmsley , Palmer Dabbelt , Albert Ou , William Qiu Subject: [PATCH v6 2/4] pwm: opencores: Add PWM driver support Date: Fri, 20 Oct 2023 18:37:39 +0800 Message-ID: <20231020103741.557735-3-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020103741.557735-1-william.qiu@starfivetech.com> References: <20231020103741.557735-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add Pulse Width Modulation driver support for OpenCores. Co-developed-by: Hal Feng Signed-off-by: Hal Feng Signed-off-by: William Qiu --- MAINTAINERS | 7 ++ drivers/pwm/Kconfig | 11 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-ocores.c | 211 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 230 insertions(+) create mode 100644 drivers/pwm/pwm-ocores.c diff --git a/MAINTAINERS b/MAINTAINERS index 6c4cce45a09d..321af8fa7aad 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16003,6 +16003,13 @@ F: Documentation/i2c/busses/i2c-ocores.rst F: drivers/i2c/busses/i2c-ocores.c F: include/linux/platform_data/i2c-ocores.h +OPENCORES PWM DRIVER +M: William Qiu +M: Hal Feng +S: Supported +F: Documentation/devicetree/bindings/pwm/opencores,pwm-ocores.yaml +F: drivers/pwm/pwm-ocores.c + OPENRISC ARCHITECTURE M: Jonas Bonn M: Stefan Kristiansson diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 8ebcddf91f7b..cbfbf227d957 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -434,6 +434,17 @@ config PWM_NTXEC controller found in certain e-book readers designed by the original design manufacturer Netronix. +config PWM_OCORES + tristate "Opencores PWM support" + depends on HAS_IOMEM && OF + depends on COMMON_CLK && RESET_CONTROLLER + help + If you say yes to this option, support will be included for the + OpenCores PWM. For details see https://opencores.org/projects/ptc. + + To compile this driver as a module, choose M here: the module + will be called pwm-ocores. + config PWM_OMAP_DMTIMER tristate "OMAP Dual-Mode Timer PWM support" depends on OF diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index c822389c2a24..542b98202153 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_PWM_MICROCHIP_CORE) +=3D pwm-microchip-core.o obj-$(CONFIG_PWM_MTK_DISP) +=3D pwm-mtk-disp.o obj-$(CONFIG_PWM_MXS) +=3D pwm-mxs.o obj-$(CONFIG_PWM_NTXEC) +=3D pwm-ntxec.o +obj-$(CONFIG_PWM_OCORES) +=3D pwm-ocores.o obj-$(CONFIG_PWM_OMAP_DMTIMER) +=3D pwm-omap-dmtimer.o obj-$(CONFIG_PWM_PCA9685) +=3D pwm-pca9685.o obj-$(CONFIG_PWM_PXA) +=3D pwm-pxa.o diff --git a/drivers/pwm/pwm-ocores.c b/drivers/pwm/pwm-ocores.c new file mode 100644 index 000000000000..7a510de4e063 --- /dev/null +++ b/drivers/pwm/pwm-ocores.c @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * OpenCores PWM Driver + * + * https://opencores.org/projects/ptc + * + * Copyright (C) 2018-2023 StarFive Technology Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define REG_OCPWM_CNTR(base) ((base)) +#define REG_OCPWM_HRC(base) ((base) + 0x4) +#define REG_OCPWM_LRC(base) ((base) + 0x8) +#define REG_OCPWM_CTRL(base) ((base) + 0xC) + +/* OCPWM_CTRL register bits*/ +#define OCPWM_EN BIT(0) +#define OCPWM_ECLK BIT(1) +#define OCPWM_NEC BIT(2) +#define OCPWM_OE BIT(3) +#define OCPWM_SIGNLE BIT(4) +#define OCPWM_INTE BIT(5) +#define OCPWM_INT BIT(6) +#define OCPWM_CNTRRST BIT(7) +#define OCPWM_CAPTE BIT(8) + +struct ocores_pwm_device { + struct pwm_chip chip; + struct clk *clk; + struct reset_control *rst; + const struct ocores_pwm_data *data; + void __iomem *regs; + u32 clk_rate; /* PWM APB clock frequency */ +}; + +struct ocores_pwm_data { + void __iomem *(*get_ch_base)(void __iomem *base, unsigned int channel); +}; + +static inline struct ocores_pwm_device * +chip_to_ocores(struct pwm_chip *chip) + +{ + return container_of(chip, struct ocores_pwm_device, chip); +} + +void __iomem *starfive_jh71x0_get_ch_base(void __iomem *base, + unsigned int channel) +{ + return base + (channel > 3 ? channel % 4 * 0x10 + (1 << 15) : channel * 0= x10); +} + +static int ocores_pwm_get_state(struct pwm_chip *chip, + struct pwm_device *dev, + struct pwm_state *state) +{ + struct ocores_pwm_device *pwm =3D chip_to_ocores(chip); + void __iomem *base =3D pwm->data->get_ch_base ? + pwm->data->get_ch_base(pwm->regs, dev->hwpwm) : pwm->regs; + u32 period_data, duty_data, ctrl_data; + + period_data =3D readl(REG_OCPWM_LRC(base)); + duty_data =3D readl(REG_OCPWM_HRC(base)); + ctrl_data =3D readl(REG_OCPWM_CTRL(base)); + + state->period =3D DIV_ROUND_CLOSEST_ULL((u64)period_data * NSEC_PER_SEC, = pwm->clk_rate); + state->duty_cycle =3D DIV_ROUND_CLOSEST_ULL((u64)duty_data * NSEC_PER_SEC= , pwm->clk_rate); + state->polarity =3D PWM_POLARITY_INVERSED; + state->enabled =3D (ctrl_data & OCPWM_EN) ? true : false; + + return 0; +} + +static int ocores_pwm_apply(struct pwm_chip *chip, + struct pwm_device *dev, + const struct pwm_state *state) +{ + struct ocores_pwm_device *pwm =3D chip_to_ocores(chip); + void __iomem *base =3D pwm->data->get_ch_base ? + pwm->data->get_ch_base(pwm->regs, dev->hwpwm) : pwm->regs; + u32 period_data, duty_data, ctrl_data =3D 0; + + if (state->polarity !=3D PWM_POLARITY_INVERSED) + return -EINVAL; + + period_data =3D DIV_ROUND_CLOSEST_ULL(state->period * pwm->clk_rate, + NSEC_PER_SEC); + duty_data =3D DIV_ROUND_CLOSEST_ULL(state->duty_cycle * pwm->clk_rate, + NSEC_PER_SEC); + + writel(period_data, REG_OCPWM_LRC(base)); + writel(duty_data, REG_OCPWM_HRC(base)); + writel(0, REG_OCPWM_CNTR(base)); + + ctrl_data =3D readl(REG_OCPWM_CTRL(base)); + if (state->enabled) + writel(ctrl_data | OCPWM_EN | OCPWM_OE, REG_OCPWM_CTRL(base)); + else + writel(ctrl_data & ~(OCPWM_EN | OCPWM_OE), REG_OCPWM_CTRL(base)); + + return 0; +} + +static const struct pwm_ops ocores_pwm_ops =3D { + .get_state =3D ocores_pwm_get_state, + .apply =3D ocores_pwm_apply, + .owner =3D THIS_MODULE, +}; + +static const struct ocores_pwm_data jh71x0_pwm_data =3D { + .get_ch_base =3D starfive_jh71x0_get_ch_base, +}; + +static const struct of_device_id ocores_pwm_of_match[] =3D { + { .compatible =3D "opencores,pwm-ocores" }, + { .compatible =3D "starfive,jh71x0-pwm", .data =3D &jh71x0_pwm_data}, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ocores_pwm_of_match); + +static int ocores_pwm_probe(struct platform_device *pdev) +{ + const struct of_device_id *id; + struct device *dev =3D &pdev->dev; + struct ocores_pwm_device *pwm; + struct pwm_chip *chip; + int ret; + + id =3D of_match_device(ocores_pwm_of_match, dev); + if (!id) + return -EINVAL; + + pwm =3D devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL); + if (!pwm) + return -ENOMEM; + + pwm->data =3D id->data; + chip =3D &pwm->chip; + chip->dev =3D dev; + chip->ops =3D &ocores_pwm_ops; + chip->npwm =3D 8; + chip->of_pwm_n_cells =3D 3; + + pwm->regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pwm->regs)) + return dev_err_probe(dev, PTR_ERR(pwm->regs), + "Unable to map IO resources\n"); + + pwm->clk =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(pwm->clk)) + return dev_err_probe(dev, PTR_ERR(pwm->clk), + "Unable to get pwm's clock\n"); + + pwm->rst =3D devm_reset_control_get_optional_exclusive(dev, NULL); + reset_control_deassert(pwm->rst); + + pwm->clk_rate =3D clk_get_rate(pwm->clk); + if (pwm->clk_rate <=3D 0) { + dev_warn(dev, "Failed to get APB clock rate\n"); + return -EINVAL; + } + + ret =3D devm_pwmchip_add(dev, chip); + if (ret < 0) { + dev_err(dev, "Cannot register PTC: %d\n", ret); + clk_disable_unprepare(pwm->clk); + reset_control_assert(pwm->rst); + return ret; + } + + platform_set_drvdata(pdev, pwm); + + return 0; +} + +static int ocores_pwm_remove(struct platform_device *dev) +{ + struct ocores_pwm_device *pwm =3D platform_get_drvdata(dev); + + reset_control_assert(pwm->rst); + clk_disable_unprepare(pwm->clk); + + return 0; +} + +static struct platform_driver ocores_pwm_driver =3D { + .probe =3D ocores_pwm_probe, + .remove =3D ocores_pwm_remove, + .driver =3D { + .name =3D "ocores-pwm", + .of_match_table =3D ocores_pwm_of_match, + }, +}; +module_platform_driver(ocores_pwm_driver); + +MODULE_AUTHOR("Jieqin Chen"); +MODULE_AUTHOR("Hal Feng "); +MODULE_DESCRIPTION("OpenCores PWM PTC driver"); +MODULE_LICENSE("GPL"); -- 2.34.1 From nobody Wed Dec 17 09:44:32 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 102B0C25B41 for ; Fri, 20 Oct 2023 10:37:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376958AbjJTKhw convert rfc822-to-8bit (ORCPT ); Fri, 20 Oct 2023 06:37:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34752 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376842AbjJTKht (ORCPT ); Fri, 20 Oct 2023 06:37:49 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C481D55; Fri, 20 Oct 2023 03:37:47 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 560D124E35A; Fri, 20 Oct 2023 18:37:46 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 20 Oct 2023 18:37:46 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 20 Oct 2023 18:37:45 +0800 From: William Qiu To: , , , CC: Emil Renner Berthing , Rob Herring , Thierry Reding , Philipp Zabel , Krzysztof Kozlowski , Conor Dooley , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , "Hal Feng" , Paul Walmsley , Palmer Dabbelt , Albert Ou , William Qiu Subject: [PATCH v6 3/4] riscv: dts: starfive: jh7110: Add PWM node and pins configuration Date: Fri, 20 Oct 2023 18:37:40 +0800 Message-ID: <20231020103741.557735-4-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020103741.557735-1-william.qiu@starfivetech.com> References: <20231020103741.557735-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add OpenCores PWM controller node and add PWM pins configuration on VisionFive 2 board. Signed-off-by: William Qiu Reviewed-by: Hal Feng --- .../jh7110-starfive-visionfive-2.dtsi | 22 +++++++++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 ++++++++ 2 files changed, 31 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi= b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index 12ebe9792356..63d16a6a4e12 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -268,6 +268,12 @@ reserved-data@600000 { }; }; =20 +&pwm { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm_pins>; + status =3D "okay"; +}; + &spi0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&spi0_pins>; @@ -402,6 +408,22 @@ GPOEN_SYS_SDIO1_DATA3, }; }; =20 + pwm_pins: pwm-0 { + pwm-pins { + pinmux =3D , + ; + bias-disable; + drive-strength =3D <12>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + }; + spi0_pins: spi0-0 { mosi-pins { pinmux =3D ; + clocks =3D <&syscrg JH7110_SYSCLK_PWM_APB>; + resets =3D <&syscrg JH7110_SYSRST_PWM_APB>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + sfctemp: temperature-sensor@120e0000 { compatible =3D "starfive,jh7110-temp"; reg =3D <0x0 0x120e0000 0x0 0x10000>; --=20 2.34.1 From nobody Wed Dec 17 09:44:32 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5FC9C001DF for ; Fri, 20 Oct 2023 10:37:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376979AbjJTKh4 convert rfc822-to-8bit (ORCPT ); Fri, 20 Oct 2023 06:37:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376795AbjJTKhu (ORCPT ); Fri, 20 Oct 2023 06:37:50 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73A78D5F; Fri, 20 Oct 2023 03:37:48 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 39C4A24E14F; Fri, 20 Oct 2023 18:37:47 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 20 Oct 2023 18:37:47 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 20 Oct 2023 18:37:46 +0800 From: William Qiu To: , , , CC: Emil Renner Berthing , Rob Herring , Thierry Reding , Philipp Zabel , Krzysztof Kozlowski , Conor Dooley , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , "Hal Feng" , Paul Walmsley , Palmer Dabbelt , Albert Ou , William Qiu Subject: [PATCH v6 4/4] riscv: dts: starfive: jh7100: Add PWM node and pins configuration Date: Fri, 20 Oct 2023 18:37:41 +0800 Message-ID: <20231020103741.557735-5-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020103741.557735-1-william.qiu@starfivetech.com> References: <20231020103741.557735-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add OpenCores PWM controller node and add PWM pins configuration on VisionFive 1 board. Signed-off-by: William Qiu Reviewed-by: Hal Feng --- .../boot/dts/starfive/jh7100-common.dtsi | 24 +++++++++++++++++++ arch/riscv/boot/dts/starfive/jh7100.dtsi | 9 +++++++ 2 files changed, 33 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/b= oot/dts/starfive/jh7100-common.dtsi index b93ce351a90f..11876906cc05 100644 --- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi @@ -84,6 +84,24 @@ GPO_I2C2_PAD_SDA_OEN, }; }; =20 + pwm_pins: pwm-0 { + pwm-pins { + pinmux =3D , + ; + bias-disable; + drive-strength =3D <35>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + }; + uart3_pins: uart3-0 { rx-pins { pinmux =3D ; }; =20 +&pwm { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm_pins>; + status =3D "okay"; +}; + &uart3 { pinctrl-names =3D "default"; pinctrl-0 =3D <&uart3_pins>; diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts= /starfive/jh7100.dtsi index 35ab54fb235f..0bb9e2e5ae68 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -274,6 +274,15 @@ watchdog@12480000 { <&rstgen JH7100_RSTN_WDT>; }; =20 + pwm: pwm@12490000 { + compatible =3D "starfive,jh71x0-pwm"; + reg =3D <0x0 0x12490000 0x0 0x10000>; + clocks =3D <&clkgen JH7100_CLK_PWM_APB>; + resets =3D <&rstgen JH7100_RSTN_PWM_APB>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + sfctemp: temperature-sensor@124a0000 { compatible =3D "starfive,jh7100-temp"; reg =3D <0x0 0x124a0000 0x0 0x10000>; --=20 2.34.1