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Thu, 19 Oct 2023 01:07:27 -0500 From: Praveen Teja Kundanala To: , , , , , , , CC: Subject: [PATCH V2 4/5] nvmem: zynqmp_nvmem: Add support to access efuse Date: Thu, 19 Oct 2023 11:36:50 +0530 Message-ID: <20231019060651.23341-5-praveen.teja.kundanala@amd.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20231019060651.23341-1-praveen.teja.kundanala@amd.com> References: <20231019060651.23341-1-praveen.teja.kundanala@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD0:EE_|LV3PR12MB9234:EE_ X-MS-Office365-Filtering-Correlation-Id: 6f76ae6e-c629-4ea1-1625-08dbd069adf5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: soelFM+XG3D1fIe++r3eWVTlakSORIiqhB2n/hezVIZ1muxoGkkbHW5iPgfDlBhuV4ERNMobBjcP7w1rbdEQmXzH4O1RXrcmlfUrmaM2bC3G/mtv1SyD5hL8yoJ0DXviUS2mGy835oSovQBkhI8VNmjxFGrYFnjU9vveXhUqpQ0eXlALy0lsx2AOEth2f4QvPvQXGJoOQ6Hgr/Gxd/leVc51s8vd0rLymtFvjE6eU6yWdPsEWd2YCVDjbVEtPT28Y7kTeeHO5Icl0JzzXlG623Lj9crEbpaHwfsWormfIUQaPivh7L1r/9RgOSdAWJmtmSjQbEVy1iUPf3M52emQiABIHOxPD+TWGW1FLZif9zpOdgu+DVvsHEpcVBTHC+5LjC7hwxTf5QjnTFcxsGOHpw8BYOrj2A4/LCLB1eA63ZaeU07AZsSnFO49eIGTXhpS2fldPE040DAVyaa4MWpH0AzMO49YYb3bShagQAUNCxbObVN56OU8IzqaHCWevp93dpy+cFl8QXFVN7d8hrWeV+9GT93Ws5SUunoPwrGxhViT74DWyUmOgDHA6w/VjvIAwnF76hYV06dKMgU5VYM6XKc1vgxi8QN1+GhJ3P4Z4GiRFBi8K1eOcHieaeYWzzBIi97f6KW4BjMn+OYbkVsXGrGI4e3fmRoxCIPc7YwQmOq+nbZQrheS1kCQwmYTdVqTYgDBrovKgHNK9V6Faa4CCOEd7UaK/98ZRcK/zdRNROWw9nYrEs+EbzqHgA9h+d9PKCmaBasy2mZdHMkdGNWwOg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(376002)(136003)(346002)(39860400002)(396003)(230922051799003)(186009)(1800799009)(64100799003)(451199024)(82310400011)(46966006)(36840700001)(40470700004)(83380400001)(2906002)(6666004)(86362001)(103116003)(36756003)(336012)(426003)(41300700001)(47076005)(5660300002)(81166007)(478600001)(2616005)(26005)(40460700003)(316002)(70206006)(36860700001)(8936002)(356005)(4326008)(40480700001)(8676002)(82740400003)(110136005)(1076003)(70586007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Oct 2023 06:07:31.0627 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6f76ae6e-c629-4ea1-1625-08dbd069adf5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD0.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9234 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support to read/write efuse memory map of ZynqMP Below are the offsets of ZynqMP efuse memory map 0 - SOC version(read only) 0xC - 0xFC -ZynqMP specific purpose efuses 0x100 - 0x17F - Physical Unclonable Function(PUF) efuses repurposed as user efuses Signed-off-by: Praveen Teja Kundanala --- drivers/nvmem/zynqmp_nvmem.c | 218 ++++++++++++++++++++++++++++++----- 1 file changed, 186 insertions(+), 32 deletions(-) diff --git a/drivers/nvmem/zynqmp_nvmem.c b/drivers/nvmem/zynqmp_nvmem.c index 7f15aa89a9d0..a3bb8c3a831b 100644 --- a/drivers/nvmem/zynqmp_nvmem.c +++ b/drivers/nvmem/zynqmp_nvmem.c @@ -1,8 +1,10 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2019 Xilinx, Inc. + * Copyright (C), 2022 - 2023 Advanced Micro Devices, Inc. */ =20 +#include #include #include #include @@ -10,36 +12,190 @@ #include =20 #define SILICON_REVISION_MASK 0xF +#define P_USER_0_64_UPPER_MASK GENMASK(31, 16) +#define P_USER_127_LOWER_4_BIT_MASK GENMASK(3, 0) +#define WORD_INBYTES 4 +#define SOC_VER_SIZE 0x4 +#define EFUSE_MEMORY_SIZE 0x177 +#define UNUSED_SPACE 0x8 +#define ZYNQMP_NVMEM_SIZE (SOC_VER_SIZE + UNUSED_SPACE + \ + EFUSE_MEMORY_SIZE) +#define SOC_VERSION_OFFSET 0x0 +#define EFUSE_START_OFFSET 0xC +#define EFUSE_END_OFFSET 0xFC +#define EFUSE_PUF_START_OFFSET 0x100 +#define EFUSE_PUF_MID_OFFSET 0x140 +#define EFUSE_PUF_END_OFFSET 0x17F +#define EFUSE_NOT_ENABLED 29 =20 -struct zynqmp_nvmem_data { - struct device *dev; - struct nvmem_device *nvmem; +/* + * efuse access type + */ +enum efuse_access { + EFUSE_READ =3D 0, + EFUSE_WRITE +}; + +/** + * struct xilinx_efuse - the basic structure + * @src: address of the buffer to store the data to be write/read + * @size: read/write word count + * @offset: read/write offset + * @flag: 0 - represents efuse read and 1- represents efuse write + * @pufuserfuse:0 - represents non-puf efuses, offset is used for read/wri= te + * 1 - represents puf user fuse row number. + * + * this structure stores all the required details to + * read/write efuse memory. + */ +struct xilinx_efuse { + u64 src; + u32 size; + u32 offset; + enum efuse_access flag; + u32 pufuserfuse; }; =20 -static int zynqmp_nvmem_read(void *context, unsigned int offset, - void *val, size_t bytes) +static int zynqmp_efuse_access(void *context, unsigned int offset, + void *val, size_t bytes, enum efuse_access flag, + unsigned int pufflag) { + struct device *dev =3D context; + struct xilinx_efuse *efuse; + dma_addr_t dma_addr; + dma_addr_t dma_buf; + size_t words =3D bytes / WORD_INBYTES; int ret; - int idcode, version; - struct zynqmp_nvmem_data *priv =3D context; - - ret =3D zynqmp_pm_get_chipid(&idcode, &version); - if (ret < 0) - return ret; + int value; + char *data; + + if (bytes % WORD_INBYTES !=3D 0) { + dev_err(dev, "Bytes requested should be word aligned\n"); + return -EOPNOTSUPP; + } + + if (pufflag =3D=3D 0 && offset % WORD_INBYTES) { + dev_err(dev, "Offset requested should be word aligned\n"); + return -EOPNOTSUPP; + } + + if (pufflag =3D=3D 1 && flag =3D=3D EFUSE_WRITE) { + memcpy(&value, val, bytes); + if ((offset =3D=3D EFUSE_PUF_START_OFFSET || + offset =3D=3D EFUSE_PUF_MID_OFFSET) && + value & P_USER_0_64_UPPER_MASK) { + dev_err(dev, "Only lower 4 bytes are allowed to be programmed in P_USER= _0 & P_USER_64\n"); + return -EOPNOTSUPP; + } + + if (offset =3D=3D EFUSE_PUF_END_OFFSET && + (value & P_USER_127_LOWER_4_BIT_MASK)) { + dev_err(dev, "Only MSB 28 bits are allowed to be programmed for P_USER_= 127\n"); + return -EOPNOTSUPP; + } + } + + efuse =3D dma_alloc_coherent(dev, sizeof(struct xilinx_efuse), + &dma_addr, GFP_KERNEL); + if (!efuse) + return -ENOMEM; =20 - dev_dbg(priv->dev, "Read chipid val %x %x\n", idcode, version); - *(int *)val =3D version & SILICON_REVISION_MASK; + data =3D dma_alloc_coherent(dev, sizeof(bytes), + &dma_buf, GFP_KERNEL); + if (!data) { + ret =3D -ENOMEM; + goto efuse_data_fail; + } + + if (flag =3D=3D EFUSE_WRITE) { + memcpy(data, val, bytes); + efuse->flag =3D EFUSE_WRITE; + } else { + efuse->flag =3D EFUSE_READ; + } + + efuse->src =3D dma_buf; + efuse->size =3D words; + efuse->offset =3D offset; + efuse->pufuserfuse =3D pufflag; + + zynqmp_pm_efuse_access(dma_addr, (u32 *)&ret); + if (ret !=3D 0) { + if (ret =3D=3D EFUSE_NOT_ENABLED) { + dev_err(dev, "efuse access is not enabled\n"); + ret =3D -EOPNOTSUPP; + } else { + dev_err(dev, "Error in efuse read %x\n", ret); + ret =3D -EPERM; + } + goto efuse_access_err; + } + + if (flag =3D=3D EFUSE_READ) + memcpy(val, data, bytes); +efuse_access_err: + dma_free_coherent(dev, sizeof(bytes), + data, dma_buf); +efuse_data_fail: + dma_free_coherent(dev, sizeof(struct xilinx_efuse), + efuse, dma_addr); + + return ret; +} =20 - return 0; +static int zynqmp_nvmem_read(void *context, unsigned int offset, void *val= , size_t bytes) +{ + struct device *dev =3D context; + int ret; + int pufflag =3D 0; + int idcode; + int version; + + if (offset >=3D EFUSE_PUF_START_OFFSET && offset <=3D EFUSE_PUF_END_OFFSE= T) + pufflag =3D 1; + + switch (offset) { + /* Soc version offset is zero */ + case SOC_VERSION_OFFSET: + if (bytes !=3D SOC_VER_SIZE) + return -EOPNOTSUPP; + + ret =3D zynqmp_pm_get_chipid((u32 *)&idcode, (u32 *)&version); + if (ret < 0) + return ret; + + dev_dbg(dev, "Read chipid val %x %x\n", idcode, version); + *(int *)val =3D version & SILICON_REVISION_MASK; + break; + /* Efuse offset starts from 0xc */ + case EFUSE_START_OFFSET ... EFUSE_END_OFFSET: + case EFUSE_PUF_START_OFFSET ... EFUSE_PUF_END_OFFSET: + ret =3D zynqmp_efuse_access(context, offset, val, + bytes, EFUSE_READ, pufflag); + break; + default: + *(u32 *)val =3D 0xDEADBEEF; + ret =3D 0; + break; + } + + return ret; } =20 -static struct nvmem_config econfig =3D { - .name =3D "zynqmp-nvmem", - .owner =3D THIS_MODULE, - .word_size =3D 1, - .size =3D 1, - .read_only =3D true, -}; +static int zynqmp_nvmem_write(void *context, + unsigned int offset, void *val, size_t bytes) +{ + int pufflag =3D 0; + + if (offset < EFUSE_START_OFFSET || offset > EFUSE_PUF_END_OFFSET) + return -EOPNOTSUPP; + + if (offset >=3D EFUSE_PUF_START_OFFSET && offset <=3D EFUSE_PUF_END_OFFSE= T) + pufflag =3D 1; + + return zynqmp_efuse_access(context, offset, + val, bytes, EFUSE_WRITE, pufflag); +} =20 static const struct of_device_id zynqmp_nvmem_match[] =3D { { .compatible =3D "xlnx,zynqmp-nvmem-fw", }, @@ -50,21 +206,19 @@ MODULE_DEVICE_TABLE(of, zynqmp_nvmem_match); static int zynqmp_nvmem_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; - struct zynqmp_nvmem_data *priv; - - priv =3D devm_kzalloc(dev, sizeof(struct zynqmp_nvmem_data), GFP_KERNEL); - if (!priv) - return -ENOMEM; + struct nvmem_config econfig =3D {}; =20 - priv->dev =3D dev; + econfig.name =3D "zynqmp-nvmem"; + econfig.owner =3D THIS_MODULE; + econfig.word_size =3D 1; + econfig.size =3D ZYNQMP_NVMEM_SIZE; econfig.dev =3D dev; econfig.add_legacy_fixed_of_cells =3D true; + econfig.priv =3D dev; econfig.reg_read =3D zynqmp_nvmem_read; - econfig.priv =3D priv; - - priv->nvmem =3D devm_nvmem_register(dev, &econfig); + econfig.reg_write =3D zynqmp_nvmem_write; =20 - return PTR_ERR_OR_ZERO(priv->nvmem); + return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &econfig)); } =20 static struct platform_driver zynqmp_nvmem_driver =3D { @@ -77,6 +231,6 @@ static struct platform_driver zynqmp_nvmem_driver =3D { =20 module_platform_driver(zynqmp_nvmem_driver); =20 -MODULE_AUTHOR("Michal Simek , Nava kishore Manne "); +MODULE_AUTHOR("Kalyani Akula , Praveen Teja Kundana= la "); MODULE_DESCRIPTION("ZynqMP NVMEM driver"); MODULE_LICENSE("GPL"); --=20 2.36.1