From nobody Thu Nov 14 05:18:57 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10300CDB482 for ; Thu, 19 Oct 2023 05:56:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232820AbjJSF4o (ORCPT ); Thu, 19 Oct 2023 01:56:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53010 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231705AbjJSF4e (ORCPT ); Thu, 19 Oct 2023 01:56:34 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C5FC4112; Wed, 18 Oct 2023 22:56:28 -0700 (PDT) X-UUID: 3c3a52266e4411eea33bb35ae8d461a2-20231019 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=hCddrdlDqKBenFHKsmGj9TdLiwG7aCIS6uamT9ldeW0=; b=dBY78zsjgnqvcVrisbsOmlD4Ll5niGxTj5Twt6E/dI/V+goRii5xV0wm2+ozGG+DVuSuRiwolpVxzOXQt20Hoaj0Ayrnh/1sQ+R4eHljba4TWt2ymZ01u7ZaV8NiE7+NSCqzLypDqHGJfm30LKMuA9RJnExW0+CBhQkHbJ4gEP4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:14511d16-4d23-4285-a55d-b704ebda40c0,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5f78ec9,CLOUDID:d9671cc0-14cc-44ca-b657-2d2783296e72,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: 3c3a52266e4411eea33bb35ae8d461a2-20231019 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1650186100; Thu, 19 Oct 2023 13:56:24 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 19 Oct 2023 13:56:23 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 19 Oct 2023 13:56:22 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , CK Hu , Krzysztof Kozlowski , Matthias Brugger , Rob Herring CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Fei Shao , Sean Paul , Johnson Wang , "Nancy . Lin" , Moudy Ho , Hsiao Chien Sung , "Jason-JH . Lin" , Nathan Lu , , , , , Subject: [PATCH v10 15/24] drm/mediatek: Remove ineffectual power management codes Date: Thu, 19 Oct 2023 13:56:10 +0800 Message-ID: <20231019055619.19358-16-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231019055619.19358-1-shawn.sung@mediatek.com> References: <20231019055619.19358-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Display modules will be powered on when .atomic_enable(), there is no need to do it again in mtk_crtc_ddp_hw_init(). Besides, the DRM devices are created manually when mtk-mmsys is probed and there is no power domain linked to it. Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.= ") Signed-off-by: Hsiao Chien Sung Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/medi= atek/mtk_drm_crtc.c index bc4cc75cca18..c7edd80be428 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include @@ -362,22 +361,16 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *= mtk_crtc, struct drm_atomic drm_connector_list_iter_end(&conn_iter); } =20 - ret =3D pm_runtime_resume_and_get(crtc->dev->dev); - if (ret < 0) { - DRM_ERROR("Failed to enable power domain: %d\n", ret); - return ret; - } - ret =3D mtk_mutex_prepare(mtk_crtc->mutex); if (ret < 0) { DRM_ERROR("Failed to enable mutex clock: %d\n", ret); - goto err_pm_runtime_put; + goto error; } =20 ret =3D mtk_crtc_ddp_clk_enable(mtk_crtc); if (ret < 0) { DRM_ERROR("Failed to enable component clocks: %d\n", ret); - goto err_mutex_unprepare; + goto error; } =20 for (i =3D 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { @@ -426,16 +419,13 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *= mtk_crtc, struct drm_atomic =20 return 0; =20 -err_mutex_unprepare: +error: mtk_mutex_unprepare(mtk_crtc->mutex); -err_pm_runtime_put: - pm_runtime_put(crtc->dev->dev); return ret; } =20 static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) { - struct drm_device *drm =3D mtk_crtc->base.dev; struct drm_crtc *crtc =3D &mtk_crtc->base; int i; =20 @@ -465,8 +455,6 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *m= tk_crtc) mtk_crtc_ddp_clk_disable(mtk_crtc); mtk_mutex_unprepare(mtk_crtc->mutex); =20 - pm_runtime_put(drm->dev); - if (crtc->state->event && !crtc->state->active) { spin_lock_irq(&crtc->dev->event_lock); drm_crtc_send_vblank_event(crtc, crtc->state->event); --=20 2.18.0