From nobody Tue Dec 16 21:17:25 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54E2ECDB465 for ; Thu, 19 Oct 2023 05:40:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232686AbjJSFku (ORCPT ); Thu, 19 Oct 2023 01:40:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53674 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232620AbjJSFkm (ORCPT ); Thu, 19 Oct 2023 01:40:42 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B303A121; Wed, 18 Oct 2023 22:40:39 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 39J5eR8F047182; Thu, 19 Oct 2023 00:40:27 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1697694027; bh=PRDvk/yhvGLHfgWqLs4QyICY9FBtECjobg+fOFKg+38=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=tUYskH4j7NCUe80kl4qX9xrLmfqLCUkSuE5V34r4zNAZPiIgKk2LJ5Facvs2VumuO 3tjnhXoB9VtLAF3VvInXrWoZ0uCRA72GrRrcGOzBGzhiZiqZdNJzasnqCUB6D3WK8t 6AkQY4B3f1L1TZdq6VVlFvLrxTUm4i5wUSczP1YA= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 39J5eRhO118305 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 19 Oct 2023 00:40:27 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 19 Oct 2023 00:40:26 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 19 Oct 2023 00:40:26 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 39J5eP8U090119; Thu, 19 Oct 2023 00:40:26 -0500 From: Jayesh Choudhary To: , , , CC: , , , , , , , , , , , Subject: [PATCH v12 1/5] arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane mux Date: Thu, 19 Oct 2023 11:10:18 +0530 Message-ID: <20231019054022.175163-2-j-choudhary@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231019054022.175163-1-j-choudhary@ti.com> References: <20231019054022.175163-1-j-choudhary@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Siddharth Vadapalli The system controller node manages the CTRL_MMR0 region. Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux. Signed-off-by: Siddharth Vadapalli [j-choudhary@ti.com: Fix serdes_ln_ctrl node] Signed-off-by: Jayesh Choudhary Reviewed-by: Roger Quadros --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index 6ca80d16ee78..d65788d16e22 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -5,6 +5,10 @@ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ */ =20 +#include + +#include "k3-serdes.h" + &cbass_main { msmc_ram: sram@70000000 { compatible =3D "mmio-sram"; @@ -26,6 +30,42 @@ l3cache-sram@200000 { }; }; =20 + scm_conf: bus@100000 { + compatible =3D "simple-bus"; + reg =3D <0x00 0x00100000 0x00 0x1c000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x00 0x00 0x00100000 0x1c000>; + + serdes_ln_ctrl: mux-controller@4080 { + compatible =3D "reg-mux"; + reg =3D <0x00004080 0x30>; + #mux-control-cells =3D <1>; + mux-reg-masks =3D <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select= */ + <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */ + <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ + <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */ + <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ + <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */ + idle-states =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + gic500: interrupt-controller@1800000 { compatible =3D "arm,gic-v3"; #address-cells =3D <2>; --=20 2.25.1