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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SN1PEPF0002529E.mail.protection.outlook.com (10.167.242.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6907.20 via Frontend Transport; Wed, 18 Oct 2023 17:19:02 +0000 Received: from rric.localdomain (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Wed, 18 Oct 2023 12:18:56 -0500 From: Robert Richter To: Davidlohr Bueso , Jonathan Cameron , Dave Jiang , "Alison Schofield" , Vishal Verma , Ira Weiny , Ben Widawsky , Dan Williams CC: , , Bjorn Helgaas , Terry Bowman , Robert Richter Subject: [PATCH v12 07/20] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Date: Wed, 18 Oct 2023 19:17:00 +0200 Message-ID: <20231018171713.1883517-8-rrichter@amd.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20231018171713.1883517-1-rrichter@amd.com> References: <20231018171713.1883517-1-rrichter@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002529E:EE_|DM6PR12MB4895:EE_ X-MS-Office365-Filtering-Correlation-Id: 538c3933-729e-4dde-68cd-08dbcffe52db X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Oct 2023 17:19:02.1185 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 538c3933-729e-4dde-68cd-08dbcffe52db X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002529E.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4895 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Now, that the Component Register mappings are stored, use them to enable and map the HDM decoder capabilities. The Component Registers do not need to be probed again for this, remove probing code. The HDM capability applies to Endpoints, USPs and VH Host Bridges. The Endpoint's component register mappings are located in the cxlds and else in the port's structure. Duplicate the cxlds->reg_map in port->reg_map for endpoint ports. Signed-off-by: Terry Bowman Signed-off-by: Robert Richter Reviewed-by: Dave Jiang [rework to drop cxl_port_get_comp_map()] Signed-off-by: Dan Williams --- drivers/cxl/core/hdm.c | 49 +++++++++++++++++------------------------ drivers/cxl/core/port.c | 29 ++++++++++++++++++------ drivers/cxl/mem.c | 5 ++--- 3 files changed, 44 insertions(+), 39 deletions(-) diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c index 11d9971f3e8c..c5f951658130 100644 --- a/drivers/cxl/core/hdm.c +++ b/drivers/cxl/core/hdm.c @@ -81,26 +81,6 @@ static void parse_hdm_decoder_caps(struct cxl_hdm *cxlhd= m) cxlhdm->interleave_mask |=3D GENMASK(14, 12); } =20 -static int map_hdm_decoder_regs(struct cxl_port *port, void __iomem *crb, - struct cxl_component_regs *regs) -{ - struct cxl_register_map map =3D { - .host =3D &port->dev, - .resource =3D port->component_reg_phys, - .base =3D crb, - .max_size =3D CXL_COMPONENT_REG_BLOCK_SIZE, - }; - - cxl_probe_component_regs(&port->dev, crb, &map.component_map); - if (!map.component_map.hdm_decoder.valid) { - dev_dbg(&port->dev, "HDM decoder registers not implemented\n"); - /* unique error code to indicate no HDM decoder capability */ - return -ENODEV; - } - - return cxl_map_component_regs(&map, regs, BIT(CXL_CM_CAP_CAP_ID_HDM)); -} - static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info) { struct cxl_hdm *cxlhdm; @@ -153,9 +133,9 @@ static bool should_emulate_decoders(struct cxl_endpoint= _dvsec_info *info) struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port, struct cxl_endpoint_dvsec_info *info) { + struct cxl_register_map *reg_map =3D &port->reg_map; struct device *dev =3D &port->dev; struct cxl_hdm *cxlhdm; - void __iomem *crb; int rc; =20 cxlhdm =3D devm_kzalloc(dev, sizeof(*cxlhdm), GFP_KERNEL); @@ -164,19 +144,30 @@ struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *p= ort, cxlhdm->port =3D port; dev_set_drvdata(dev, cxlhdm); =20 - crb =3D ioremap(port->component_reg_phys, CXL_COMPONENT_REG_BLOCK_SIZE); - if (!crb && info && info->mem_enabled) { + /* Memory devices can configure device HDM using DVSEC range regs. */ + if (reg_map->resource =3D=3D CXL_RESOURCE_NONE) { + if (!info && !info->mem_enabled) { + WARN_ON(1); + dev_err(dev, "No component registers mapped\n"); + return ERR_PTR(-ENXIO); + } + cxlhdm->decoder_count =3D info->ranges; return cxlhdm; - } else if (!crb) { - dev_err(dev, "No component registers mapped\n"); - return ERR_PTR(-ENXIO); } =20 - rc =3D map_hdm_decoder_regs(port, crb, &cxlhdm->regs); - iounmap(crb); - if (rc) + if (!reg_map->component_map.hdm_decoder.valid) { + dev_dbg(&port->dev, "HDM decoder registers not implemented\n"); + /* unique error code to indicate no HDM decoder capability */ + return ERR_PTR(-ENODEV); + } + + rc =3D cxl_map_component_regs(reg_map, &cxlhdm->regs, + BIT(CXL_CM_CAP_CAP_ID_HDM)); + if (rc) { + dev_err(dev, "Failed to map HDM capability.\n"); return ERR_PTR(rc); + } =20 parse_hdm_decoder_caps(cxlhdm); if (cxlhdm->decoder_count =3D=3D 0) { diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 28ba8922d0a4..f69484d3c93c 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -751,16 +751,31 @@ static struct cxl_port *__devm_cxl_add_port(struct de= vice *host, return port; =20 dev =3D &port->dev; - if (is_cxl_memdev(uport_dev)) + if (is_cxl_memdev(uport_dev)) { + struct cxl_memdev *cxlmd =3D to_cxl_memdev(uport_dev); + struct cxl_dev_state *cxlds =3D cxlmd->cxlds; + rc =3D dev_set_name(dev, "endpoint%d", port->id); - else if (parent_dport) + if (rc) + goto err; + + /* + * The endpoint driver already enumerated the component and RAS + * registers. Reuse that enumeration while prepping them to be + * mapped by the cxl_port driver. + */ + port->reg_map =3D cxlds->reg_map; + port->reg_map.host =3D &port->dev; + } else if (parent_dport) { rc =3D dev_set_name(dev, "port%d", port->id); - else - rc =3D dev_set_name(dev, "root%d", port->id); - if (rc) - goto err; + if (rc) + goto err; =20 - rc =3D cxl_port_setup_regs(port, component_reg_phys); + rc =3D cxl_port_setup_regs(port, component_reg_phys); + if (rc) + goto err; + } else + rc =3D dev_set_name(dev, "root%d", port->id); if (rc) goto err; =20 diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index 317c7548e4e9..04107058739b 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -49,7 +49,6 @@ static int devm_cxl_add_endpoint(struct device *host, str= uct cxl_memdev *cxlmd, struct cxl_dport *parent_dport) { struct cxl_port *parent_port =3D parent_dport->port; - struct cxl_dev_state *cxlds =3D cxlmd->cxlds; struct cxl_port *endpoint, *iter, *down; int rc; =20 @@ -65,8 +64,8 @@ static int devm_cxl_add_endpoint(struct device *host, str= uct cxl_memdev *cxlmd, ep->next =3D down; } =20 - endpoint =3D devm_cxl_add_port(host, &cxlmd->dev, - cxlds->component_reg_phys, + /* Note: endpoint port component registers are derived from @cxlds */ + endpoint =3D devm_cxl_add_port(host, &cxlmd->dev, CXL_RESOURCE_NONE, parent_dport); if (IS_ERR(endpoint)) return PTR_ERR(endpoint); --=20 2.30.2