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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SN1PEPF000252A2.mail.protection.outlook.com (10.167.242.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6907.20 via Frontend Transport; Wed, 18 Oct 2023 17:18:11 +0000 Received: from rric.localdomain (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Wed, 18 Oct 2023 12:18:08 -0500 From: Robert Richter To: Davidlohr Bueso , Jonathan Cameron , Dave Jiang , "Alison Schofield" , Vishal Verma , Ira Weiny , Ben Widawsky , Dan Williams , "Robert Richter" , Terry Bowman CC: , , Bjorn Helgaas , Jonathan Cameron Subject: [PATCH v12 02/20] cxl/core/regs: Rename @dev to @host in struct cxl_register_map Date: Wed, 18 Oct 2023 19:16:55 +0200 Message-ID: <20231018171713.1883517-3-rrichter@amd.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20231018171713.1883517-1-rrichter@amd.com> References: <20231018171713.1883517-1-rrichter@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A2:EE_|LV3PR12MB9331:EE_ X-MS-Office365-Filtering-Correlation-Id: 5562c569-9f3d-44b4-a843-08dbcffe34b8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Oct 2023 17:18:11.5591 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5562c569-9f3d-44b4-a843-08dbcffe34b8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9331 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The primary role of @dev is to host the mappings for devm operations. @dev is too ambiguous as a name. I.e. when does @dev refer to the 'struct device *' instance that the registers belong, and when does @dev refer to the 'struct device *' instance hosting the mapping for devm operations? Clarify the role of @dev in cxl_register_map by renaming it to @host. Also, rename local variables to 'host' where map->host is used. Add Fixes: tag as the fix in the next patch depends on this change. Fixes: 5d2ffbe4b81a ("cxl/port: Store the downstream port's Component Regis= ter mappings in struct cxl_dport") Signed-off-by: Terry Bowman Signed-off-by: Robert Richter Reviewed-by: Jonathan Cameron --- drivers/cxl/core/hdm.c | 2 +- drivers/cxl/core/port.c | 4 ++-- drivers/cxl/core/regs.c | 28 ++++++++++++++-------------- drivers/cxl/cxl.h | 4 ++-- drivers/cxl/pci.c | 2 +- 5 files changed, 20 insertions(+), 20 deletions(-) diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c index 4449b34a80cc..11d9971f3e8c 100644 --- a/drivers/cxl/core/hdm.c +++ b/drivers/cxl/core/hdm.c @@ -85,7 +85,7 @@ static int map_hdm_decoder_regs(struct cxl_port *port, vo= id __iomem *crb, struct cxl_component_regs *regs) { struct cxl_register_map map =3D { - .dev =3D &port->dev, + .host =3D &port->dev, .resource =3D port->component_reg_phys, .base =3D crb, .max_size =3D CXL_COMPONENT_REG_BLOCK_SIZE, diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index d4572a02989a..033651a5da30 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -691,14 +691,14 @@ static struct cxl_port *cxl_port_alloc(struct device = *uport_dev, return ERR_PTR(rc); } =20 -static int cxl_setup_comp_regs(struct device *dev, struct cxl_register_map= *map, +static int cxl_setup_comp_regs(struct device *host, struct cxl_register_ma= p *map, resource_size_t component_reg_phys) { if (component_reg_phys =3D=3D CXL_RESOURCE_NONE) return 0; =20 *map =3D (struct cxl_register_map) { - .dev =3D dev, + .host =3D host, .reg_type =3D CXL_REGLOC_RBI_COMPONENT, .resource =3D component_reg_phys, .max_size =3D CXL_COMPONENT_REG_BLOCK_SIZE, diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c index 6281127b3e9d..e0fbe964f6f0 100644 --- a/drivers/cxl/core/regs.c +++ b/drivers/cxl/core/regs.c @@ -204,7 +204,7 @@ int cxl_map_component_regs(const struct cxl_register_ma= p *map, struct cxl_component_regs *regs, unsigned long map_mask) { - struct device *dev =3D map->dev; + struct device *host =3D map->host; struct mapinfo { const struct cxl_reg_map *rmap; void __iomem **addr; @@ -225,7 +225,7 @@ int cxl_map_component_regs(const struct cxl_register_ma= p *map, continue; phys_addr =3D map->resource + mi->rmap->offset; length =3D mi->rmap->size; - *(mi->addr) =3D devm_cxl_iomap_block(dev, phys_addr, length); + *(mi->addr) =3D devm_cxl_iomap_block(host, phys_addr, length); if (!*(mi->addr)) return -ENOMEM; } @@ -237,7 +237,7 @@ EXPORT_SYMBOL_NS_GPL(cxl_map_component_regs, CXL); int cxl_map_device_regs(const struct cxl_register_map *map, struct cxl_device_regs *regs) { - struct device *dev =3D map->dev; + struct device *host =3D map->host; resource_size_t phys_addr =3D map->resource; struct mapinfo { const struct cxl_reg_map *rmap; @@ -259,7 +259,7 @@ int cxl_map_device_regs(const struct cxl_register_map *= map, =20 addr =3D phys_addr + mi->rmap->offset; length =3D mi->rmap->size; - *(mi->addr) =3D devm_cxl_iomap_block(dev, addr, length); + *(mi->addr) =3D devm_cxl_iomap_block(host, addr, length); if (!*(mi->addr)) return -ENOMEM; } @@ -309,7 +309,7 @@ int cxl_find_regblock_instance(struct pci_dev *pdev, en= um cxl_regloc_type type, int regloc, i; =20 *map =3D (struct cxl_register_map) { - .dev =3D &pdev->dev, + .host =3D &pdev->dev, .resource =3D CXL_RESOURCE_NONE, }; =20 @@ -403,15 +403,15 @@ EXPORT_SYMBOL_NS_GPL(cxl_map_pmu_regs, CXL); =20 static int cxl_map_regblock(struct cxl_register_map *map) { - struct device *dev =3D map->dev; + struct device *host =3D map->host; =20 map->base =3D ioremap(map->resource, map->max_size); if (!map->base) { - dev_err(dev, "failed to map registers\n"); + dev_err(host, "failed to map registers\n"); return -ENOMEM; } =20 - dev_dbg(dev, "Mapped CXL Memory Device resource %pa\n", &map->resource); + dev_dbg(host, "Mapped CXL Memory Device resource %pa\n", &map->resource); return 0; } =20 @@ -425,28 +425,28 @@ static int cxl_probe_regs(struct cxl_register_map *ma= p) { struct cxl_component_reg_map *comp_map; struct cxl_device_reg_map *dev_map; - struct device *dev =3D map->dev; + struct device *host =3D map->host; void __iomem *base =3D map->base; =20 switch (map->reg_type) { case CXL_REGLOC_RBI_COMPONENT: comp_map =3D &map->component_map; - cxl_probe_component_regs(dev, base, comp_map); - dev_dbg(dev, "Set up component registers\n"); + cxl_probe_component_regs(host, base, comp_map); + dev_dbg(host, "Set up component registers\n"); break; case CXL_REGLOC_RBI_MEMDEV: dev_map =3D &map->device_map; - cxl_probe_device_regs(dev, base, dev_map); + cxl_probe_device_regs(host, base, dev_map); if (!dev_map->status.valid || !dev_map->mbox.valid || !dev_map->memdev.valid) { - dev_err(dev, "registers not found: %s%s%s\n", + dev_err(host, "registers not found: %s%s%s\n", !dev_map->status.valid ? "status " : "", !dev_map->mbox.valid ? "mbox " : "", !dev_map->memdev.valid ? "memdev " : ""); return -ENXIO; } =20 - dev_dbg(dev, "Probing device registers...\n"); + dev_dbg(host, "Probing device registers...\n"); break; default: break; diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 76d92561af29..b5b015b661ea 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -247,7 +247,7 @@ struct cxl_pmu_reg_map { =20 /** * struct cxl_register_map - DVSEC harvested register block mapping parame= ters - * @dev: device for devm operations and logging + * @host: device for devm operations and logging * @base: virtual base of the register-block-BAR + @block_offset * @resource: physical resource base of the register block * @max_size: maximum mapping size to perform register search @@ -257,7 +257,7 @@ struct cxl_pmu_reg_map { * @pmu_map: cxl_reg_maps for CXL Performance Monitoring Units */ struct cxl_register_map { - struct device *dev; + struct device *host; void __iomem *base; resource_size_t resource; resource_size_t max_size; diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 44a21ab7add5..f9d852957809 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -484,7 +484,7 @@ static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev, resource_size_t component_reg_phys; =20 *map =3D (struct cxl_register_map) { - .dev =3D &pdev->dev, + .host =3D &pdev->dev, .resource =3D CXL_RESOURCE_NONE, }; =20 --=20 2.30.2