From nobody Fri Dec 19 18:44:25 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5157C41513 for ; Wed, 18 Oct 2023 06:17:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229675AbjJRGR4 (ORCPT ); Wed, 18 Oct 2023 02:17:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229718AbjJRGRp (ORCPT ); Wed, 18 Oct 2023 02:17:45 -0400 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [IPv6:2a0a:edc0:2:b01:1d::104]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A2246F9 for ; Tue, 17 Oct 2023 23:17:42 -0700 (PDT) Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1qszrw-0001a0-Sd; Wed, 18 Oct 2023 08:17:24 +0200 Received: from [2a0a:edc0:0:1101:1d::28] (helo=dude02.red.stw.pengutronix.de) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1qszrr-002UYT-7m; Wed, 18 Oct 2023 08:17:19 +0200 Received: from sha by dude02.red.stw.pengutronix.de with local (Exim 4.96) (envelope-from ) id 1qszrq-00Evj7-3D; Wed, 18 Oct 2023 08:17:18 +0200 From: Sascha Hauer To: linux-rockchip@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Heiko Stuebner , Chanwoo Choi , Kyungmin Park , MyungJoo Ham , Will Deacon , Mark Rutland , kernel@pengutronix.de, Michael Riesch , Robin Murphy , Vincent Legoll , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, Sebastian Reichel , Sascha Hauer , Jonathan Cameron Subject: [PATCH v8 17/26] PM / devfreq: rockchip-dfi: make register stride SoC specific Date: Wed, 18 Oct 2023 08:17:05 +0200 Message-Id: <20231018061714.3553817-18-s.hauer@pengutronix.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231018061714.3553817-1-s.hauer@pengutronix.de> References: <20231018061714.3553817-1-s.hauer@pengutronix.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: sha@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The currently supported RK3399 has a stride of 20 between the channel specific registers. Upcoming RK3588 has a different stride, so put the stride into driver data to make it configurable. While at it convert decimal 20 to hex 0x14 for consistency with RK3588 which has a register stride 0x4000 and we want to write that in hex as well. Reviewed-by: Jonathan Cameron Reviewed-by: Sebastian Reichel Signed-off-by: Sascha Hauer Acked-by: Chanwoo Choi --- Notes: Changes since v7: - Initialize ddrmon_stride for RK3568 and explain why it's not needed drivers/devfreq/event/rockchip-dfi.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/r= ockchip-dfi.c index 63977f9fc2693..a3d823ac68ace 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -113,6 +113,7 @@ struct rockchip_dfi { int active_events; int burst_len; int buswidth[DMC_MAX_CHANNELS]; + int ddrmon_stride; }; =20 static int rockchip_dfi_enable(struct rockchip_dfi *dfi) @@ -190,13 +191,13 @@ static void rockchip_dfi_read_counters(struct rockchi= p_dfi *dfi, struct dmc_coun if (!(dfi->channel_mask & BIT(i))) continue; res->c[i].read_access =3D readl_relaxed(dfi_regs + - DDRMON_CH0_RD_NUM + i * 20); + DDRMON_CH0_RD_NUM + i * dfi->ddrmon_stride); res->c[i].write_access =3D readl_relaxed(dfi_regs + - DDRMON_CH0_WR_NUM + i * 20); + DDRMON_CH0_WR_NUM + i * dfi->ddrmon_stride); res->c[i].access =3D readl_relaxed(dfi_regs + - DDRMON_CH0_DFI_ACCESS_NUM + i * 20); + DDRMON_CH0_DFI_ACCESS_NUM + i * dfi->ddrmon_stride); res->c[i].clock_cycles =3D readl_relaxed(dfi_regs + - DDRMON_CH0_COUNT_NUM + i * 20); + DDRMON_CH0_COUNT_NUM + i * dfi->ddrmon_stride); } } =20 @@ -664,6 +665,8 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi) dfi->buswidth[0] =3D FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH0, val) =3D=3D = 0 ? 4 : 2; dfi->buswidth[1] =3D FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH1, val) =3D=3D = 0 ? 4 : 2; =20 + dfi->ddrmon_stride =3D 0x14; + return 0; }; =20 @@ -690,6 +693,8 @@ static int rk3568_dfi_init(struct rockchip_dfi *dfi) =20 dfi->buswidth[0] =3D FIELD_GET(RK3568_PMUGRF_OS_REG2_BW_CH0, reg2) =3D=3D= 0 ? 4 : 2; =20 + dfi->ddrmon_stride =3D 0x0; /* not relevant, we only have a single channe= l on this SoC */ + return 0; }; =20 --=20 2.39.2