From nobody Fri Sep 20 12:43:16 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68E45CDB47E for ; Wed, 18 Oct 2023 04:38:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235078AbjJREiA (ORCPT ); Wed, 18 Oct 2023 00:38:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43450 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234947AbjJREhM (ORCPT ); Wed, 18 Oct 2023 00:37:12 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 136F7120; Tue, 17 Oct 2023 21:37:02 -0700 (PDT) X-UUID: f7f36a8c6d6f11eea33bb35ae8d461a2-20231018 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=WTOeBIDjwXjGhqKsLqsXHoxBxxG+10elJsW9pXcqeO0=; b=AWBEEaWCI4Q8BZrlLhEmV9wGYgCBFs5GsK1wH68rCAhQqeHSW8ReyEUULYMOp58Rs8VrVlW6VJyp8uTWTLKsk494YMEkRVKJlfmTPRa2l2onJ0J7ed9S2cixMsyRf66V5l7PmpVFfiDz32Dxe1SkHYQ5vbU7JmslJN4IEteencM=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:30884643-6bee-4da2-9a8a-14c71876d0ee,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:5f78ec9,CLOUDID:1e2341c4-1e57-4345-9d31-31ad9818b39f,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: f7f36a8c6d6f11eea33bb35ae8d461a2-20231018 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1834920141; Wed, 18 Oct 2023 12:36:56 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 18 Oct 2023 12:36:55 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 18 Oct 2023 12:36:55 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , CK Hu , Krzysztof Kozlowski , Matthias Brugger , Rob Herring CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Fei Shao , Sean Paul , Johnson Wang , "Nancy . Lin" , Moudy Ho , Hsiao Chien Sung , "Jason-JH . Lin" , Nathan Lu , , , , , Subject: [PATCH v9 20/23] drm/mediatek: Remove the redundant driver data for DPI Date: Wed, 18 Oct 2023 12:36:47 +0800 Message-ID: <20231018043650.22532-21-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231018043650.22532-1-shawn.sung@mediatek.com> References: <20231018043650.22532-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" DPI input is in 1T2P mode on both MT8195 and MT8188. Remove the redundant driver data to align the settings, or the screen will glitch. Fixes: 2847cd7e6403 ("drm/mediatek: Add mt8188 dpi compatibles and platform= data") Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_dpi.c | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 1bf6041dd88b..d633f1ca3e71 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -967,20 +967,6 @@ static const struct mtk_dpi_conf mt8186_conf =3D { .csc_enable_bit =3D CSC_ENABLE, }; =20 -static const struct mtk_dpi_conf mt8188_dpintf_conf =3D { - .cal_factor =3D mt8195_dpintf_calculate_factor, - .max_clock_khz =3D 600000, - .output_fmts =3D mt8195_output_fmts, - .num_output_fmts =3D ARRAY_SIZE(mt8195_output_fmts), - .pixels_per_iter =3D 4, - .input_2pixel =3D false, - .dimension_mask =3D DPINTF_HPW_MASK, - .hvsize_mask =3D DPINTF_HSIZE_MASK, - .channel_swap_shift =3D DPINTF_CH_SWAP, - .yuv422_en_bit =3D DPINTF_YUV422_EN, - .csc_enable_bit =3D DPINTF_CSC_ENABLE, -}; - static const struct mtk_dpi_conf mt8192_conf =3D { .cal_factor =3D mt8183_calculate_factor, .reg_h_fre_con =3D 0xe0, @@ -1104,7 +1090,7 @@ static const struct of_device_id mtk_dpi_of_ids[] =3D= { { .compatible =3D "mediatek,mt8173-dpi", .data =3D &mt8173_conf }, { .compatible =3D "mediatek,mt8183-dpi", .data =3D &mt8183_conf }, { .compatible =3D "mediatek,mt8186-dpi", .data =3D &mt8186_conf }, - { .compatible =3D "mediatek,mt8188-dp-intf", .data =3D &mt8188_dpintf_con= f }, + { .compatible =3D "mediatek,mt8188-dp-intf", .data =3D &mt8195_dpintf_con= f }, { .compatible =3D "mediatek,mt8192-dpi", .data =3D &mt8192_conf }, { .compatible =3D "mediatek,mt8195-dp-intf", .data =3D &mt8195_dpintf_con= f }, { /* sentinel */ }, --=20 2.18.0