From nobody Fri Sep 20 10:01:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B68C6CDB484 for ; Wed, 18 Oct 2023 04:37:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229627AbjJREhI (ORCPT ); Wed, 18 Oct 2023 00:37:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229608AbjJREhA (ORCPT ); Wed, 18 Oct 2023 00:37:00 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DC9F5A2; Tue, 17 Oct 2023 21:36:57 -0700 (PDT) X-UUID: f5b430086d6f11eea33bb35ae8d461a2-20231018 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=3bwWmp38+I/LoyedglLaGgKkEJRhkTImvrhTZ0gSEPs=; b=tL0ZPVzJawu8tCOfoP+kX/x46d+/M/EK/L6jWLUfAzMBrlRIiHJyu0wGTshKMMoTFmuuTptAteE1qIflQLDyuCfHFx/QIx9IeOZa+3hjBRshEwA0umj8/EvIPY1zFKeim27CArZ95++WzEfXWErQ0D/uz6usJfJqSj2/m7LQNAI=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:da05dd7e-35c1-4732-8463-72ab63c3fd07,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5f78ec9,CLOUDID:e7382a15-4929-4845-9571-38c601e9c3c9,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: f5b430086d6f11eea33bb35ae8d461a2-20231018 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1617126690; Wed, 18 Oct 2023 12:36:52 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 18 Oct 2023 12:36:51 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 18 Oct 2023 12:36:51 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , CK Hu , Krzysztof Kozlowski , Matthias Brugger , Rob Herring CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Fei Shao , Sean Paul , Johnson Wang , "Nancy . Lin" , Moudy Ho , Hsiao Chien Sung , "Jason-JH . Lin" , Nathan Lu , , , , , Subject: [PATCH v9 01/23] dt-bindings: display: mediatek: ethdr: Add compatible for MT8188 Date: Wed, 18 Oct 2023 12:36:28 +0800 Message-ID: <20231018043650.22532-2-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231018043650.22532-1-shawn.sung@mediatek.com> References: <20231018043650.22532-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatible name for MediaTek MT8188 ETHDR. Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Reviewed-by: CK Hu Signed-off-by: Hsiao Chien Sung --- .../bindings/display/mediatek/mediatek,ethdr.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,et= hdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethd= r.yaml index 801fa66ae615..677882348ede 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml @@ -23,7 +23,11 @@ description: =20 properties: compatible: - const: mediatek,mt8195-disp-ethdr + oneOf: + - const: mediatek,mt8195-disp-ethdr + - items: + - const: mediatek,mt8188-disp-ethdr + - const: mediatek,mt8195-disp-ethdr =20 reg: maxItems: 7 --=20 2.18.0 From nobody Fri Sep 20 10:01:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9888CCDB482 for ; Wed, 18 Oct 2023 04:38:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229608AbjJREiS (ORCPT ); Wed, 18 Oct 2023 00:38:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43478 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229575AbjJREhM (ORCPT ); Wed, 18 Oct 2023 00:37:12 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED50713A; Tue, 17 Oct 2023 21:37:06 -0700 (PDT) X-UUID: f5c614586d6f11ee8051498923ad61e6-20231018 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=zT0/dVzTq/5/KwjP2Gaq1AJNyFqB1WS0NxFr2ZWObRU=; b=GccDWtrFiir3FqadsI49EgjKbQ3oP2yqUiPiK9ljbMrduwb/lXi4ZMrwy30DthzmkDZV0eIUWAO8EKdrR3280v5ziZkxCoUO55YS8iPQJYrTvyBUyMTwlyNDyCJRw6DFvyztZ7e1g6bD9OCs5svJ5RCyugiZoKHuFCHie+rmp0o=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:146bd98d-5d31-48cb-a8e2-8a81aa977021,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5f78ec9,CLOUDID:7ce90fc0-14cc-44ca-b657-2d2783296e72,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: f5c614586d6f11ee8051498923ad61e6-20231018 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 561039201; Wed, 18 Oct 2023 12:36:52 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 18 Oct 2023 12:36:51 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 18 Oct 2023 12:36:51 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , CK Hu , Krzysztof Kozlowski , Matthias Brugger , Rob Herring CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Fei Shao , Sean Paul , Johnson Wang , "Nancy . Lin" , Moudy Ho , Hsiao Chien Sung , "Jason-JH . Lin" , Nathan Lu , , , , , Subject: [PATCH v9 02/23] dt-bindings: display: mediatek: mdp-rdma: Add compatible for MT8188 Date: Wed, 18 Oct 2023 12:36:29 +0800 Message-ID: <20231018043650.22532-3-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231018043650.22532-1-shawn.sung@mediatek.com> References: <20231018043650.22532-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatible name for MediaTek MT8188 MDP-RDMA. Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Reviewed-by: CK Hu Signed-off-by: Hsiao Chien Sung --- .../bindings/display/mediatek/mediatek,mdp-rdma.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,md= p-rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,m= dp-rdma.yaml index dd12e2ff685c..7570a0684967 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.= yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.= yaml @@ -21,7 +21,11 @@ description: =20 properties: compatible: - const: mediatek,mt8195-vdo1-rdma + oneOf: + - const: mediatek,mt8195-vdo1-rdma + - items: + - const: mediatek,mt8188-vdo1-rdma + - const: mediatek,mt8195-vdo1-rdma =20 reg: maxItems: 1 --=20 2.18.0 From nobody Fri Sep 20 10:01:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A389BCDB485 for ; Wed, 18 Oct 2023 04:37:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235046AbjJREhl (ORCPT ); Wed, 18 Oct 2023 00:37:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42390 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229572AbjJREhF (ORCPT ); Wed, 18 Oct 2023 00:37:05 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1AA27116; Tue, 17 Oct 2023 21:37:00 -0700 (PDT) X-UUID: f5f2f8ba6d6f11eea33bb35ae8d461a2-20231018 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=VP/1tDlzIPrQAvOfYhnWvYsMQpUhOw6iHjDPTiQLtRA=; b=AqOJ3jTSjZ5g7jBb3iyRPvxifCgHLb4WPmOg72G6LsbvVvlZkCFCV9u33wfwHLM5JaQbK6o/xgoiEv88Ww0OCW+MhsHtnN/BY1euQzTnXej9xPvZwDjED+SwP3va9DcKV8D1o9yAqnvaZPpULrI6XPxnJblRuno3Tx6giK+8I7c=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:629d45e7-60df-420c-bf35-e723b5d1b7e3,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5f78ec9,CLOUDID:a554ecf0-9a6e-4c39-b73e-f2bc08ca3dc5,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: f5f2f8ba6d6f11eea33bb35ae8d461a2-20231018 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1944502935; Wed, 18 Oct 2023 12:36:53 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 18 Oct 2023 12:36:51 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 18 Oct 2023 12:36:51 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , CK Hu , Krzysztof Kozlowski , Matthias Brugger , Rob Herring CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Fei Shao , Sean Paul , Johnson Wang , "Nancy . Lin" , Moudy Ho , Hsiao Chien Sung , "Jason-JH . Lin" , Nathan Lu , , , , , Subject: [PATCH v9 03/23] dt-bindings: display: mediatek: merge: Add compatible for MT8188 Date: Wed, 18 Oct 2023 12:36:30 +0800 Message-ID: <20231018043650.22532-4-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231018043650.22532-1-shawn.sung@mediatek.com> References: <20231018043650.22532-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatible name for MediaTek MT8188 MERGE. Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Reviewed-by: CK Hu Signed-off-by: Hsiao Chien Sung --- .../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,me= rge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merg= e.yaml index eead5cb8636e..5c678695162e 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml @@ -27,6 +27,9 @@ properties: - items: - const: mediatek,mt6795-disp-merge - const: mediatek,mt8173-disp-merge + - items: + - const: mediatek,mt8188-disp-merge + - const: mediatek,mt8195-disp-merge =20 reg: maxItems: 1 --=20 2.18.0 From nobody Fri Sep 20 10:01:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C07D1CDB483 for ; Wed, 18 Oct 2023 04:38:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235200AbjJREiD (ORCPT ); Wed, 18 Oct 2023 00:38:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43496 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235013AbjJREhP (ORCPT ); Wed, 18 Oct 2023 00:37:15 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0034513D; Tue, 17 Oct 2023 21:37:06 -0700 (PDT) X-UUID: f77c71ca6d6f11ee8051498923ad61e6-20231018 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=W5RMBeAtAJ3QWTJFC7HXa4Omx7QtPIe8uwySAvSyeRk=; b=lbpnYpD0H5mPwctA+n9f+nivUhzz+imO/vPfAS5lMQxE8sHWxhkAqXZUij2MraIsFoPxAx2Odvshk065I9HOvi8TTdYy4/5Z1tpXCNVF2hTBi44FLqFWGt0/emhVKL9uh/KqPIcxXqQpuKcljEQJCmO4YDFEA/CXySdRLJYbzHI=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:56b7f214-36a3-470a-bb89-63a68f311ff4,IP:0,U RL:25,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:25 X-CID-META: VersionHash:5f78ec9,CLOUDID:102341c4-1e57-4345-9d31-31ad9818b39f,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_ULN,TF_CID_SPAM_SNR X-UUID: f77c71ca6d6f11ee8051498923ad61e6-20231018 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1294101140; Wed, 18 Oct 2023 12:36:55 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 18 Oct 2023 12:36:51 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 18 Oct 2023 12:36:51 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , "CK Hu" , Krzysztof Kozlowski , Matthias Brugger , Rob Herring CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Fei Shao , Sean Paul , Johnson Wang , "Nancy . Lin" , Moudy Ho , Hsiao Chien Sung , "Jason-JH . Lin" , Nathan Lu , , , , , Subject: [PATCH v9 04/23] dt-bindings: display: mediatek: padding: Add MT8188 Date: Wed, 18 Oct 2023 12:36:31 +0800 Message-ID: <20231018043650.22532-5-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231018043650.22532-1-shawn.sung@mediatek.com> References: <20231018043650.22532-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--7.513800-8.000000 X-TMASE-MatchedRID: 9rm+L2YNiKzyZ92BnYqk5lz+axQLnAVB6SXuwUgGH0hbKBBN5zqG8FaP 6AhhdqyDBRj5e39v/eGsMR/ATxTHjWVnjx+sD6Kytw+xHnsmQjOMp+s3ceVcmb/Yg8aa0YTZdd3 vE6bWkcHv3WZroeUzUI1xSG08E+c3VHcNS6pil71CnGIuUMP0VUEKKv3+tzX7UiwXYafXfD6kB0 1zVAshlyIvUI0oiRYyZMzrwqima4jmyenDbONxLaEtILqFekmXLoYOuiLW+uXW4BShNeq/ewpCM S7M3CBmkHg+Xqfv+GzQvEuTNHaCJh0QUKM89Lf/o65WJt1k1O+H7D1bP/FcOglbhF7ZTanLYeGP 4tValiDG3TRnfVX2PIAy6p60ZV62v2ThXg3lx4DdB/CxWTRRu4as+d5/8j56Yxdi4F8nEfi5OCV GY5JudjeHtrlqvPTaQnQ6/WjRw2GXmU/FzSSM1Q== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--7.513800-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: BEA73C3609E4C71771ADCFBC57CC5502AE115990252F4F242B6702D18DAFF7992000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Padding is a new hardware module on MediaTek MT8188, add dt-bindings for it. Reviewed-by: Krzysztof Kozlowski Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- .../display/mediatek/mediatek,padding.yaml | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/medi= atek,padding.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,pa= dding.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,pa= dding.yaml new file mode 100644 index 000000000000..db24801ebc48 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.y= aml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,padding.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Display Padding + +maintainers: + - Chun-Kuang Hu + - Philipp Zabel + +description: + Padding provides ability to add pixels to width and height of a layer wi= th + specified colors. Due to hardware design, Mixer in VDOSYS1 requires + width of a layer to be 2-pixel-align, or 4-pixel-align when ETHDR is ena= bled, + we need Padding to deal with odd width. + Please notice that even if the Padding is in bypass mode, settings in + register must be cleared to 0, or undefined behaviors could happen. + +properties: + compatible: + const: mediatek,mt8188-padding + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + items: + - description: RDMA Clock + + mediatek,gce-client-reg: + description: + GCE (Global Command Engine) is a multi-core micro processor that hel= ps + its clients to execute commands without interrupting CPU. This prope= rty + describes GCE client's information that is composed by 4 fields. + 1. Phandle of the GCE (there may be several GCE processors) + 2. Sub-system ID defined in the dt-binding like a user ID + (Please refer to include/dt-bindings/gce/-gce.h) + 3. Offset from base address of the subsys you are at + 4. Size of the register the client needs + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: Phandle of the GCE + - description: Subsys ID defined in the dt-binding + - description: Offset from base address of the subsys + - description: Size of register + maxItems: 1 + +required: + - compatible + - reg + - power-domains + - clocks + - mediatek,gce-client-reg + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + padding0: padding@1c11d000 { + compatible =3D "mediatek,mt8188-padding"; + reg =3D <0 0x1c11d000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_PADDING0>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c11XXXX 0xd000 0x10= 00>; + }; + }; --=20 2.18.0 From nobody Fri Sep 20 10:01:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06C12CDB47E for ; Wed, 18 Oct 2023 04:37:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235090AbjJREhV (ORCPT ); Wed, 18 Oct 2023 00:37:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42490 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229564AbjJREhD (ORCPT ); Wed, 18 Oct 2023 00:37:03 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50E29102; Tue, 17 Oct 2023 21:37:00 -0700 (PDT) X-UUID: f670720e6d6f11eea33bb35ae8d461a2-20231018 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=zzF3boDBRWlfDL4Pvp/k1dn44ua+Sn799t2Hqg8wI/g=; b=I5Y6lNwZ4lwQHIp2nThU0C3HRrXDDc2QduvwkcPvhurIHVKqP5FxBoHtY/s7Og6AenZkEoV5ZMDZkLFs7IhZr6vNVwcGzaYWLo0v8B/2rTiGviqQa4vl+49mFP7MRblIdh1Pb1IShny8u8M3aT3ttU7nvyYa1/6I9Cz7qjxSaLQ=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:89ee2a30-d784-4ad3-8ee9-bd960aa90543,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5f78ec9,CLOUDID:fe382a15-4929-4845-9571-38c601e9c3c9,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: f670720e6d6f11eea33bb35ae8d461a2-20231018 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1520138686; Wed, 18 Oct 2023 12:36:53 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 18 Oct 2023 12:36:52 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 18 Oct 2023 12:36:52 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , "CK Hu" , Krzysztof Kozlowski , Matthias Brugger , Rob Herring CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Fei Shao , Sean Paul , Johnson Wang , "Nancy . Lin" , Moudy Ho , Hsiao Chien Sung , "Jason-JH . Lin" , Nathan Lu , , , , , Subject: [PATCH v9 05/23] dt-bindings: arm: mediatek: Add compatible for MT8188 Date: Wed, 18 Oct 2023 12:36:32 +0800 Message-ID: <20231018043650.22532-6-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231018043650.22532-1-shawn.sung@mediatek.com> References: <20231018043650.22532-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--1.601500-8.000000 X-TMASE-MatchedRID: jhJi18RLqAIDh1tb/sWFHED6z8N1m1ALqm/9CTn1HV3fUZT83lbkEA0F DzFL1GEo4vM1YF6AJbbCCfuIMF6xLSdET58jp62S5HN/FSoy8AiM7DEEPaeBzaURFpIT6knaSIs V/u7tNK1eBZ+cZnanZdkp29rlArbfywQl8cu/FAKIOAPcIWMwYv/rxeniXYwBgITnGkK0NFNRsk XKHhdfKpij9M86UwHhsKHfMTjCprwNQJGvyiKf6Q== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--1.601500-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: A0790376C20C48CE6D35D8DC57A30125C250155E7C446CA3A8211518081003092000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatible name for MediaTek MT8188 VDOSYS1. Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Signed-off-by: Hsiao Chien Sung --- .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.= yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml index d1410345ef18..8180199d6573 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml @@ -32,6 +32,7 @@ properties: - mediatek,mt8183-mmsys - mediatek,mt8186-mmsys - mediatek,mt8188-vdosys0 + - mediatek,mt8188-vdosys1 - mediatek,mt8192-mmsys - mediatek,mt8195-vdosys1 - mediatek,mt8195-vppsys0 --=20 2.18.0 From nobody Fri Sep 20 10:01:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EC3CC41513 for ; Wed, 18 Oct 2023 04:37:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229693AbjJREhg (ORCPT ); Wed, 18 Oct 2023 00:37:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229571AbjJREhE (ORCPT ); Wed, 18 Oct 2023 00:37:04 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6238B110; Tue, 17 Oct 2023 21:37:00 -0700 (PDT) X-UUID: f5f4618c6d6f11eea33bb35ae8d461a2-20231018 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=e3ahd3M0XcppL08N+KpDhIH1BYr1qRQbibyyNReplTw=; b=oHKAFsZjhbQ79G5hA4Y4qU/ucVOkDiv6urzjd8wdDUXs3lo9tzzM60K93k9/iz6sXavbFIJF+oBGv40M3bk89n0Jq7/hLtGBUQTZJ5LY/RdOXv9xPQV44/v5ITCfqXC8AA1tEBRLNCW7HkGoNdJiJdxGaiJuIlX0/q6ICPxL00k=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:dc9837fb-dfbe-4371-aed7-4063e26bac3a,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5f78ec9,CLOUDID:022341c4-1e57-4345-9d31-31ad9818b39f,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: f5f4618c6d6f11eea33bb35ae8d461a2-20231018 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 557243001; Wed, 18 Oct 2023 12:36:53 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 18 Oct 2023 12:36:52 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 18 Oct 2023 12:36:52 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , CK Hu , Krzysztof Kozlowski , Matthias Brugger , Rob Herring CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Fei Shao , Sean Paul , Johnson Wang , "Nancy . Lin" , Moudy Ho , Hsiao Chien Sung , "Jason-JH . Lin" , Nathan Lu , , , , , Subject: [PATCH v9 06/23] dt-bindings: reset: mt8188: Add VDOSYS reset control bits Date: Wed, 18 Oct 2023 12:36:33 +0800 Message-ID: <20231018043650.22532-7-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231018043650.22532-1-shawn.sung@mediatek.com> References: <20231018043650.22532-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add MT8188 VDOSYS0 and VDOSYS1 reset control bits. Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Signed-off-by: Hsiao Chien Sung --- include/dt-bindings/reset/mt8188-resets.h | 75 +++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-binding= s/reset/mt8188-resets.h index ba9a5e9b8899..5a58c54e7d20 100644 --- a/include/dt-bindings/reset/mt8188-resets.h +++ b/include/dt-bindings/reset/mt8188-resets.h @@ -38,4 +38,79 @@ #define MT8188_INFRA_RST1_THERMAL_CTRL_RST 1 #define MT8188_INFRA_RST3_PTP_CTRL_RST 2 =20 +#define MT8188_VDO0_RST_DISP_OVL0 0 +#define MT8188_VDO0_RST_FAKE_ENG0 1 +#define MT8188_VDO0_RST_DISP_CCORR0 2 +#define MT8188_VDO0_RST_DISP_MUTEX0 3 +#define MT8188_VDO0_RST_DISP_GAMMA0 4 +#define MT8188_VDO0_RST_DISP_DITHER0 5 +#define MT8188_VDO0_RST_DISP_WDMA0 6 +#define MT8188_VDO0_RST_DISP_RDMA0 7 +#define MT8188_VDO0_RST_DSI0 8 +#define MT8188_VDO0_RST_DSI1 9 +#define MT8188_VDO0_RST_DSC_WRAP0 10 +#define MT8188_VDO0_RST_VPP_MERGE0 11 +#define MT8188_VDO0_RST_DP_INTF0 12 +#define MT8188_VDO0_RST_DISP_AAL0 13 +#define MT8188_VDO0_RST_INLINEROT0 14 +#define MT8188_VDO0_RST_APB_BUS 15 +#define MT8188_VDO0_RST_DISP_COLOR0 16 +#define MT8188_VDO0_RST_MDP_WROT0 17 +#define MT8188_VDO0_RST_DISP_RSZ0 18 + +#define MT8188_VDO1_RST_SMI_LARB2 0 +#define MT8188_VDO1_RST_SMI_LARB3 1 +#define MT8188_VDO1_RST_GALS 2 +#define MT8188_VDO1_RST_FAKE_ENG0 3 +#define MT8188_VDO1_RST_FAKE_ENG1 4 +#define MT8188_VDO1_RST_MDP_RDMA0 5 +#define MT8188_VDO1_RST_MDP_RDMA1 6 +#define MT8188_VDO1_RST_MDP_RDMA2 7 +#define MT8188_VDO1_RST_MDP_RDMA3 8 +#define MT8188_VDO1_RST_VPP_MERGE0 9 +#define MT8188_VDO1_RST_VPP_MERGE1 10 +#define MT8188_VDO1_RST_VPP_MERGE2 11 +#define MT8188_VDO1_RST_VPP_MERGE3 12 +#define MT8188_VDO1_RST_VPP_MERGE4 13 +#define MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC 14 +#define MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC 15 +#define MT8188_VDO1_RST_DISP_MUTEX 16 +#define MT8188_VDO1_RST_MDP_RDMA4 17 +#define MT8188_VDO1_RST_MDP_RDMA5 18 +#define MT8188_VDO1_RST_MDP_RDMA6 19 +#define MT8188_VDO1_RST_MDP_RDMA7 20 +#define MT8188_VDO1_RST_DP_INTF1_MMCK 21 +#define MT8188_VDO1_RST_DPI0_MM_CK 22 +#define MT8188_VDO1_RST_DPI1_MM_CK 23 +#define MT8188_VDO1_RST_MERGE0_DL_ASYNC 24 +#define MT8188_VDO1_RST_MERGE1_DL_ASYNC 25 +#define MT8188_VDO1_RST_MERGE2_DL_ASYNC 26 +#define MT8188_VDO1_RST_MERGE3_DL_ASYNC 27 +#define MT8188_VDO1_RST_MERGE4_DL_ASYNC 28 +#define MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_ASYNC 29 +#define MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ASYNC 30 +#define MT8188_VDO1_RST_PADDING0 31 +#define MT8188_VDO1_RST_PADDING1 32 +#define MT8188_VDO1_RST_PADDING2 33 +#define MT8188_VDO1_RST_PADDING3 34 +#define MT8188_VDO1_RST_PADDING4 35 +#define MT8188_VDO1_RST_PADDING5 36 +#define MT8188_VDO1_RST_PADDING6 37 +#define MT8188_VDO1_RST_PADDING7 38 +#define MT8188_VDO1_RST_DISP_RSZ0 39 +#define MT8188_VDO1_RST_DISP_RSZ1 40 +#define MT8188_VDO1_RST_DISP_RSZ2 41 +#define MT8188_VDO1_RST_DISP_RSZ3 42 +#define MT8188_VDO1_RST_HDR_VDO_FE0 43 +#define MT8188_VDO1_RST_HDR_GFX_FE0 44 +#define MT8188_VDO1_RST_HDR_VDO_BE 45 +#define MT8188_VDO1_RST_HDR_VDO_FE1 46 +#define MT8188_VDO1_RST_HDR_GFX_FE1 47 +#define MT8188_VDO1_RST_DISP_MIXER 48 +#define MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC 49 +#define MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC 50 +#define MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC 51 +#define MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC 52 +#define MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC 53 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */ --=20 2.18.0 From nobody Fri Sep 20 10:01:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0CA77CDB482 for ; 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Wed, 18 Oct 2023 12:36:53 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 18 Oct 2023 12:36:52 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 18 Oct 2023 12:36:52 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , CK Hu , Krzysztof Kozlowski , Matthias Brugger , Rob Herring CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Fei Shao , Sean Paul , Johnson Wang , "Nancy . Lin" , Moudy Ho , Hsiao Chien Sung , "Jason-JH . Lin" , Nathan Lu , , , , , Subject: [PATCH v9 07/23] soc: mediatek: Support MT8188 VDOSYS1 in mtk-mmsys Date: Wed, 18 Oct 2023 12:36:34 +0800 Message-ID: <20231018043650.22532-8-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231018043650.22532-1-shawn.sung@mediatek.com> References: <20231018043650.22532-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" - Add register definitions for MT8188 - Add VDOSYS1 routing table - Update MUTEX definitions accordingly - Set VSYNC length from 0x40 (default) to 1 since ETHDR is bypassed Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/soc/mediatek/mt8188-mmsys.h | 126 ++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 13 +++ drivers/soc/mediatek/mtk-mmsys.h | 29 +++++++ drivers/soc/mediatek/mtk-mutex.c | 35 ++++++++ 4 files changed, 203 insertions(+) diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8= 188-mmsys.h index 448cc3761b43..a9490c3c4256 100644 --- a/drivers/soc/mediatek/mt8188-mmsys.h +++ b/drivers/soc/mediatek/mt8188-mmsys.h @@ -67,6 +67,56 @@ #define MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE BIT(18) #define MT8188_SOUT_DSC_WRAP0_OUT_TO_DISP_WDMA0 BIT(19) =20 +#define MT8188_VDO1_HDR_TOP_CFG 0xd00 +#define MT8188_VDO1_MIXER_IN1_ALPHA 0xd30 +#define MT8188_VDO1_MIXER_IN1_PAD 0xd40 +#define MT8188_VDO1_MIXER_VSYNC_LEN 0xd5c +#define MT8188_VDO1_MERGE0_ASYNC_CFG_WD 0xe30 +#define MT8188_VDO1_HDRBE_ASYNC_CFG_WD 0xe70 +#define MT8188_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04 +#define MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 1 +#define MT8188_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08 +#define MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 1 +#define MT8188_VDO1_DISP_DPI1_SEL_IN 0xf10 +#define MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT 0 +#define MT8188_VDO1_DISP_DP_INTF0_SEL_IN 0xf14 +#define MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT 0 +#define MT8188_VDO1_MERGE4_SOUT_SEL 0xf18 +#define MT8188_MERGE4_SOUT_TO_DPI1_SEL BIT(2) +#define MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL BIT(3) +#define MT8188_VDO1_MIXER_IN1_SEL_IN 0xf24 +#define MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT 1 +#define MT8188_VDO1_MIXER_IN2_SEL_IN 0xf28 +#define MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT 1 +#define MT8188_VDO1_MIXER_IN3_SEL_IN 0xf2c +#define MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT 1 +#define MT8188_VDO1_MIXER_IN4_SEL_IN 0xf30 +#define MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT 1 +#define MT8188_VDO1_MIXER_OUT_SOUT_SEL 0xf34 +#define MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL 1 +#define MT8188_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c +#define MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 1 +#define MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40 +#define MT8188_SOUT_TO_MIXER_IN1_SEL 1 +#define MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44 +#define MT8188_SOUT_TO_MIXER_IN2_SEL 1 +#define MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48 +#define MT8188_SOUT_TO_MIXER_IN3_SEL 1 +#define MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c +#define MT8188_SOUT_TO_MIXER_IN4_SEL 1 +#define MT8188_VDO1_MERGE4_ASYNC_SEL_IN 0xf50 +#define MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT 1 +#define MT8188_VDO1_MIXER_IN1_SOUT_SEL 0xf58 +#define MT8188_MIXER_IN1_SOUT_TO_DISP_MIXER 0 +#define MT8188_VDO1_MIXER_IN2_SOUT_SEL 0xf5c +#define MT8188_MIXER_IN2_SOUT_TO_DISP_MIXER 0 +#define MT8188_VDO1_MIXER_IN3_SOUT_SEL 0xf60 +#define MT8188_MIXER_IN3_SOUT_TO_DISP_MIXER 0 +#define MT8188_VDO1_MIXER_IN4_SOUT_SEL 0xf64 +#define MT8188_MIXER_IN4_SOUT_TO_DISP_MIXER 0 +#define MT8188_VDO1_MIXER_SOUT_SEL_IN 0xf68 +#define MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0 + static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] =3D { { DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, @@ -146,4 +196,80 @@ static const struct mtk_mmsys_routes mmsys_mt8188_rout= ing_table[] =3D { }, }; =20 +static const struct mtk_mmsys_routes mmsys_mt8188_vdo1_routing_table[] =3D= { + { + DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1, + MT8188_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0), + MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 + }, { + DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1, + MT8188_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0), + MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 + }, { + DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2, + MT8188_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0), + MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 + }, { + DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8188_SOUT_TO_MIXER_IN1_SEL + }, { + DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8188_SOUT_TO_MIXER_IN2_SEL + }, { + DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8188_SOUT_TO_MIXER_IN3_SEL + }, { + DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8188_SOUT_TO_MIXER_IN4_SEL + }, { + DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, + MT8188_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0), + MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL + }, { + DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0), + MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT + }, { + DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0), + MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT + }, { + DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0), + MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT + }, { + DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0), + MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT + }, { + DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, + MT8188_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0), + MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER + }, { + DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, + MT8188_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0), + MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, + MT8188_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0), + MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, + MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0), + MT8188_MERGE4_SOUT_TO_DPI1_SEL + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, + MT8188_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0), + MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, + MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0), + MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL + } +}; + #endif /* __SOC_MEDIATEK_MT8188_MMSYS_H */ diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mm= sys.c index 9619faa796e8..b1db09e19905 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -89,6 +89,14 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys0= _driver_data =3D { .num_routes =3D ARRAY_SIZE(mmsys_mt8188_routing_table), }; =20 +static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data =3D { + .clk_driver =3D "clk-mt8188-vdo1", + .routes =3D mmsys_mt8188_vdo1_routing_table, + .num_routes =3D ARRAY_SIZE(mmsys_mt8188_vdo1_routing_table), + .num_resets =3D 96, + .vsync_len =3D 1, +}; + static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data =3D { .clk_driver =3D "clk-mt8192-mm", .routes =3D mmsys_mt8192_routing_table, @@ -169,6 +177,10 @@ void mtk_mmsys_ddp_connect(struct device *dev, if (cur =3D=3D routes[i].from_comp && next =3D=3D routes[i].to_comp) mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask, routes[i].val, NULL); + + if (mmsys->data->vsync_len) + mtk_mmsys_update_bits(mmsys, MT8188_VDO1_MIXER_VSYNC_LEN, GENMASK(31, 0), + mmsys->data->vsync_len, NULL); } EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); =20 @@ -431,6 +443,7 @@ static const struct of_device_id of_match_mtk_mmsys[] = =3D { { .compatible =3D "mediatek,mt8183-mmsys", .data =3D &mt8183_mmsys_driver= _data }, { .compatible =3D "mediatek,mt8186-mmsys", .data =3D &mt8186_mmsys_driver= _data }, { .compatible =3D "mediatek,mt8188-vdosys0", .data =3D &mt8188_vdosys0_dr= iver_data }, + { .compatible =3D "mediatek,mt8188-vdosys1", .data =3D &mt8188_vdosys1_dr= iver_data }, { .compatible =3D "mediatek,mt8192-mmsys", .data =3D &mt8192_mmsys_driver= _data }, /* "mediatek,mt8195-mmsys" compatible is deprecated */ { .compatible =3D "mediatek,mt8195-mmsys", .data =3D &mt8195_vdosys0_driv= er_data }, diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mm= sys.h index 6725403d2e3a..9d8507f98b7a 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -86,6 +86,34 @@ struct mtk_mmsys_routes { u32 val; }; =20 +/** + * struct mtk_mmsys_driver_data - Settings of the mmsys + * @clk_driver: Clock driver name that the mmsys is using + * (defined in drivers/clk/mediatek/clk-*.c). + * @routes: Routing table of the mmsys. + * It provides mux settings from one module to another. + * @num_routes: Array size of the routes. + * @sw0_rst_offset: Register offset for the reset control. + * @num_resets: Number of reset bits that are defined + * @is_vppsys: Whether the mmsys is VPPSYS (Video Processing Pipe) + * or VDOSYS (Video). Only VDOSYS needs to be added to drm dri= ver. + * @vsync_len: VSYNC length of the MIXER. + * VSYNC is usually triggered by the connector, so its length = is a + * fixed value when the frame rate is decided, but ETHDR and + * MIXER generate their own VSYNC due to hardware design, ther= efore + * MIXER has to sync with ETHDR by adjusting VSYNC length. + * On MT8195, there is no such setting so we use the gap betwe= en + * falling edge and rising edge of SOF (Start of Frame) signal= to + * do the job, but since MT8188, VSYNC_LEN setting is introduc= ed to + * solve the problem and is given 0x40 (ticks) as the default = value. + * Please notice that this value has to be set to 1 (minimum) = if + * ETHDR is bypassed, otherwise MIXER could wait too long and = causing + * underflow. + * + * Each MMSYS (multi-media system) may have different settings, they may u= se + * different clock sources, mux settings, reset control ...etc., and these + * differences are all stored here. + */ struct mtk_mmsys_driver_data { const char *clk_driver; const struct mtk_mmsys_routes *routes; @@ -93,6 +121,7 @@ struct mtk_mmsys_driver_data { const u16 sw0_rst_offset; const u32 num_resets; const bool is_vppsys; + const u8 vsync_len; }; =20 /* diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mu= tex.c index b92cffec7be7..988a678819d9 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -134,6 +134,22 @@ #define MT8188_MUTEX_MOD_DISP_POSTMASK0 24 #define MT8188_MUTEX_MOD2_DISP_PWM0 33 =20 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA0 0 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA1 1 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA2 2 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA3 3 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA4 4 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA5 5 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA6 6 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA7 7 +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE0 20 +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE1 21 +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE2 22 +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE3 23 +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE4 24 +#define MT8188_MUTEX_MOD_DISP1_DISP_MIXER 30 +#define MT8188_MUTEX_MOD_DISP1_DP_INTF1 39 + #define MT8195_MUTEX_MOD_DISP_OVL0 0 #define MT8195_MUTEX_MOD_DISP_WDMA0 1 #define MT8195_MUTEX_MOD_DISP_RDMA0 2 @@ -265,6 +281,7 @@ #define MT8183_MUTEX_SOF_DPI0 2 #define MT8188_MUTEX_SOF_DSI0 1 #define MT8188_MUTEX_SOF_DP_INTF0 3 +#define MT8188_MUTEX_SOF_DP_INTF1 4 #define MT8195_MUTEX_SOF_DSI0 1 #define MT8195_MUTEX_SOF_DSI1 2 #define MT8195_MUTEX_SOF_DP_INTF0 3 @@ -276,6 +293,7 @@ #define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) #define MT8188_MUTEX_EOF_DSI0 (MT8188_MUTEX_SOF_DSI0 << 7) #define MT8188_MUTEX_EOF_DP_INTF0 (MT8188_MUTEX_SOF_DP_INTF0 << 7) +#define MT8188_MUTEX_EOF_DP_INTF1 (MT8188_MUTEX_SOF_DP_INTF1 << 7) #define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7) #define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7) #define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7) @@ -446,6 +464,21 @@ static const unsigned int mt8188_mutex_mod[DDP_COMPONE= NT_ID_MAX] =3D { [DDP_COMPONENT_DSI0] =3D MT8188_MUTEX_MOD_DISP_DSI0, [DDP_COMPONENT_PWM0] =3D MT8188_MUTEX_MOD2_DISP_PWM0, [DDP_COMPONENT_DP_INTF0] =3D MT8188_MUTEX_MOD_DISP_DP_INTF0, + [DDP_COMPONENT_DP_INTF1] =3D MT8188_MUTEX_MOD_DISP1_DP_INTF1, + [DDP_COMPONENT_ETHDR_MIXER] =3D MT8188_MUTEX_MOD_DISP1_DISP_MIXER, + [DDP_COMPONENT_MDP_RDMA0] =3D MT8188_MUTEX_MOD_DISP1_MDP_RDMA0, + [DDP_COMPONENT_MDP_RDMA1] =3D MT8188_MUTEX_MOD_DISP1_MDP_RDMA1, + [DDP_COMPONENT_MDP_RDMA2] =3D MT8188_MUTEX_MOD_DISP1_MDP_RDMA2, + [DDP_COMPONENT_MDP_RDMA3] =3D MT8188_MUTEX_MOD_DISP1_MDP_RDMA3, + [DDP_COMPONENT_MDP_RDMA4] =3D MT8188_MUTEX_MOD_DISP1_MDP_RDMA4, + [DDP_COMPONENT_MDP_RDMA5] =3D MT8188_MUTEX_MOD_DISP1_MDP_RDMA5, + [DDP_COMPONENT_MDP_RDMA6] =3D MT8188_MUTEX_MOD_DISP1_MDP_RDMA6, + [DDP_COMPONENT_MDP_RDMA7] =3D MT8188_MUTEX_MOD_DISP1_MDP_RDMA7, + [DDP_COMPONENT_MERGE1] =3D MT8188_MUTEX_MOD_DISP1_VPP_MERGE0, + [DDP_COMPONENT_MERGE2] =3D MT8188_MUTEX_MOD_DISP1_VPP_MERGE1, + [DDP_COMPONENT_MERGE3] =3D MT8188_MUTEX_MOD_DISP1_VPP_MERGE2, + [DDP_COMPONENT_MERGE4] =3D MT8188_MUTEX_MOD_DISP1_VPP_MERGE3, + [DDP_COMPONENT_MERGE5] =3D MT8188_MUTEX_MOD_DISP1_VPP_MERGE4, }; =20 static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] =3D { @@ -606,6 +639,8 @@ static const unsigned int mt8188_mutex_sof[DDP_MUTEX_SO= F_MAX] =3D { MT8188_MUTEX_SOF_DSI0 | MT8188_MUTEX_EOF_DSI0, [MUTEX_SOF_DP_INTF0] =3D MT8188_MUTEX_SOF_DP_INTF0 | MT8188_MUTEX_EOF_DP_INTF0, + [MUTEX_SOF_DP_INTF1] =3D + MT8188_MUTEX_SOF_DP_INTF1 | MT8188_MUTEX_EOF_DP_INTF1, }; =20 static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] =3D { --=20 2.18.0 From nobody Fri Sep 20 10:01:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D04D2CDB484 for ; Wed, 18 Oct 2023 04:37:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235064AbjJREhq (ORCPT ); Wed, 18 Oct 2023 00:37:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229584AbjJREhG (ORCPT ); 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Lin" , Moudy Ho , Hsiao Chien Sung , "Jason-JH . Lin" , Nathan Lu , , , , , Subject: [PATCH v9 08/23] soc: mediatek: Support MT8188 VDOSYS1 Padding in mtk-mmsys Date: Wed, 18 Oct 2023 12:36:35 +0800 Message-ID: <20231018043650.22532-9-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231018043650.22532-1-shawn.sung@mediatek.com> References: <20231018043650.22532-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" - Add Padding components - Add Mutex module definitions for Padding Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/soc/mediatek/mtk-mutex.c | 16 ++++++++++++++++ include/linux/soc/mediatek/mtk-mmsys.h | 8 ++++++++ 2 files changed, 24 insertions(+) diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mu= tex.c index 988a678819d9..d52ce093adb7 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -142,6 +142,14 @@ #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA5 5 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA6 6 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA7 7 +#define MT8188_MUTEX_MOD_DISP1_PADDING0 8 +#define MT8188_MUTEX_MOD_DISP1_PADDING1 9 +#define MT8188_MUTEX_MOD_DISP1_PADDING2 10 +#define MT8188_MUTEX_MOD_DISP1_PADDING3 11 +#define MT8188_MUTEX_MOD_DISP1_PADDING4 12 +#define MT8188_MUTEX_MOD_DISP1_PADDING5 13 +#define MT8188_MUTEX_MOD_DISP1_PADDING6 14 +#define MT8188_MUTEX_MOD_DISP1_PADDING7 15 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE0 20 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE1 21 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE2 22 @@ -474,6 +482,14 @@ static const unsigned int mt8188_mutex_mod[DDP_COMPONE= NT_ID_MAX] =3D { [DDP_COMPONENT_MDP_RDMA5] =3D MT8188_MUTEX_MOD_DISP1_MDP_RDMA5, [DDP_COMPONENT_MDP_RDMA6] =3D MT8188_MUTEX_MOD_DISP1_MDP_RDMA6, [DDP_COMPONENT_MDP_RDMA7] =3D MT8188_MUTEX_MOD_DISP1_MDP_RDMA7, + [DDP_COMPONENT_PADDING0] =3D MT8188_MUTEX_MOD_DISP1_PADDING0, + [DDP_COMPONENT_PADDING1] =3D MT8188_MUTEX_MOD_DISP1_PADDING1, + [DDP_COMPONENT_PADDING2] =3D MT8188_MUTEX_MOD_DISP1_PADDING2, + [DDP_COMPONENT_PADDING3] =3D MT8188_MUTEX_MOD_DISP1_PADDING3, + [DDP_COMPONENT_PADDING4] =3D MT8188_MUTEX_MOD_DISP1_PADDING4, + [DDP_COMPONENT_PADDING5] =3D MT8188_MUTEX_MOD_DISP1_PADDING5, + [DDP_COMPONENT_PADDING6] =3D MT8188_MUTEX_MOD_DISP1_PADDING6, + [DDP_COMPONENT_PADDING7] =3D MT8188_MUTEX_MOD_DISP1_PADDING7, [DDP_COMPONENT_MERGE1] =3D MT8188_MUTEX_MOD_DISP1_VPP_MERGE0, [DDP_COMPONENT_MERGE2] =3D MT8188_MUTEX_MOD_DISP1_VPP_MERGE1, [DDP_COMPONENT_MERGE3] =3D MT8188_MUTEX_MOD_DISP1_VPP_MERGE2, diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/med= iatek/mtk-mmsys.h index 2475ef914746..4885b065b849 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -62,6 +62,14 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_OVL1, + DDP_COMPONENT_PADDING0, + DDP_COMPONENT_PADDING1, + DDP_COMPONENT_PADDING2, + DDP_COMPONENT_PADDING3, + DDP_COMPONENT_PADDING4, + DDP_COMPONENT_PADDING5, + DDP_COMPONENT_PADDING6, + DDP_COMPONENT_PADDING7, DDP_COMPONENT_POSTMASK0, DDP_COMPONENT_PWM0, DDP_COMPONENT_PWM1, --=20 2.18.0 From nobody Fri Sep 20 10:01:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88578CDB47E for ; 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Lin" , Moudy Ho , Hsiao Chien Sung , "Jason-JH . Lin" , Nathan Lu , , , , , Subject: [PATCH v9 09/23] soc: mediatek: Support reset bit mapping in mmsys driver Date: Wed, 18 Oct 2023 12:36:36 +0800 Message-ID: <20231018043650.22532-10-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231018043650.22532-1-shawn.sung@mediatek.com> References: <20231018043650.22532-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--7.363700-8.000000 X-TMASE-MatchedRID: 6IKkQlwkGxfhsdkaHFW0p25IHkZABHAU0nXvwjW2mSXb6Y+fnTZUL+jk huBL0aGZ9SK5q0H2UamK0Joj0npda6m/G7eYsFM7wVaayvK71l/pJe7BSAYfSFsoEE3nOobwSI7 v7A0N15jT01A2vEikVgG2ORx9EyapQylVlmxnJkaQOktEo73GFKIf1lfNT7Zi0pEcoXqJQB0G1W 3alEv3RuLzNWBegCW2wgn7iDBesS0gBwKKRHe+rym8wnhgeYRu8Sb8LRlOeyolQIUEtjBUYtjYi PzlkU7iZOupnNkvA/U= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--7.363700-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 6CA514F979D6D1078D2995EBF42F856C09E6FB5109813BC33C8972EE05AA5D1C2000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" - Reset ID must starts from 0 and be consecutive, but the reset bits in our hardware design is not continuous, some bits are left unused, we need a map to solve the problem - Use old style 1-to-1 mapping if .rst_tb is not defined Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/soc/mediatek/mtk-mmsys.c | 9 +++++++++ drivers/soc/mediatek/mtk-mmsys.h | 3 +++ 2 files changed, 12 insertions(+) diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mm= sys.c index b1db09e19905..3a7108eefe9d 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -314,6 +314,15 @@ static int mtk_mmsys_reset_update(struct reset_control= ler_dev *rcdev, unsigned l u32 offset; u32 reg; =20 + if (mmsys->data->rst_tb) { + if (id >=3D mmsys->data->num_resets) { + dev_err(rcdev->dev, "Invalid reset ID: %lu (>=3D%u)\n", + id, mmsys->data->num_resets); + return -EINVAL; + } + id =3D mmsys->data->rst_tb[id]; + } + offset =3D (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32); id =3D id % MMSYS_SW_RESET_PER_REG; reg =3D mmsys->data->sw0_rst_offset + offset; diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mm= sys.h index 9d8507f98b7a..d370192737ca 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -78,6 +78,8 @@ #define DSI_SEL_IN_RDMA 0x1 #define DSI_SEL_IN_MASK 0x1 =20 +#define MMSYS_RST_NR(bank, bit) (((bank) * 32) + (bit)) + struct mtk_mmsys_routes { u32 from_comp; u32 to_comp; @@ -119,6 +121,7 @@ struct mtk_mmsys_driver_data { const struct mtk_mmsys_routes *routes; const unsigned int num_routes; const u16 sw0_rst_offset; + const u8 *rst_tb; const u32 num_resets; const bool is_vppsys; const u8 vsync_len; --=20 2.18.0 From nobody Fri Sep 20 10:01:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 919E5CDB47E for ; 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Wed, 18 Oct 2023 12:36:54 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 18 Oct 2023 12:36:53 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 18 Oct 2023 12:36:53 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , "CK Hu" , Krzysztof Kozlowski , Matthias Brugger , Rob Herring CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Fei Shao , Sean Paul , Johnson Wang , "Nancy . Lin" , Moudy Ho , Hsiao Chien Sung , "Jason-JH . Lin" , Nathan Lu , , , , , Subject: [PATCH v9 10/23] soc: mediatek: Add MT8188 VDOSYS reset bit map Date: Wed, 18 Oct 2023 12:36:37 +0800 Message-ID: <20231018043650.22532-11-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231018043650.22532-1-shawn.sung@mediatek.com> References: <20231018043650.22532-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--6.042400-8.000000 X-TMASE-MatchedRID: 9DomuZeNnSapk9YSiEd5IufHZObG8Jso6SXuwUgGH0hbKBBN5zqG8EiO 7+wNDdeYRHLRFcKKZXfbCHv011Gy9VSU1d+VJ4IjtG07VELUSnRfohHCqSnabgTozVi1xfq8MJK 6qaU5tN00ULOv9iNOM0q+cX2jmfqvmxh0gY/o+VmiAZ3zAhQYgn0tCKdnhB589yM15V5aWpj6C0 ePs7A07fyjtizU0rhjVyJ6Rrqx+FNSRMjv86A6CPVU14ep5TZkqBHnAYeJC8o= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--6.042400-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 1038789DEA2E8C1B014650713760DD3224CD80179D2E67DE0101FC1CDDA5378B2000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add MT8188 reset bit map for VDOSYS0 and VDOSYS1. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/soc/mediatek/mt8188-mmsys.h | 84 +++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 7 ++- 2 files changed, 90 insertions(+), 1 deletion(-) diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8= 188-mmsys.h index a9490c3c4256..6bebf1a69fc0 100644 --- a/drivers/soc/mediatek/mt8188-mmsys.h +++ b/drivers/soc/mediatek/mt8188-mmsys.h @@ -3,6 +3,10 @@ #ifndef __SOC_MEDIATEK_MT8188_MMSYS_H #define __SOC_MEDIATEK_MT8188_MMSYS_H =20 +#include +#include + +#define MT8188_VDO0_SW0_RST_B 0x190 #define MT8188_VDO0_OVL_MOUT_EN 0xf14 #define MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0) #define MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1) @@ -67,6 +71,7 @@ #define MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE BIT(18) #define MT8188_SOUT_DSC_WRAP0_OUT_TO_DISP_WDMA0 BIT(19) =20 +#define MT8188_VDO1_SW0_RST_B 0x1d0 #define MT8188_VDO1_HDR_TOP_CFG 0xd00 #define MT8188_VDO1_MIXER_IN1_ALPHA 0xd30 #define MT8188_VDO1_MIXER_IN1_PAD 0xd40 @@ -117,6 +122,85 @@ #define MT8188_VDO1_MIXER_SOUT_SEL_IN 0xf68 #define MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0 =20 +static const u8 mmsys_mt8188_vdo0_rst_tb[] =3D { + [MT8188_VDO0_RST_DISP_OVL0] =3D MMSYS_RST_NR(0, 0), + [MT8188_VDO0_RST_FAKE_ENG0] =3D MMSYS_RST_NR(0, 2), + [MT8188_VDO0_RST_DISP_CCORR0] =3D MMSYS_RST_NR(0, 4), + [MT8188_VDO0_RST_DISP_MUTEX0] =3D MMSYS_RST_NR(0, 6), + [MT8188_VDO0_RST_DISP_GAMMA0] =3D MMSYS_RST_NR(0, 8), + [MT8188_VDO0_RST_DISP_DITHER0] =3D MMSYS_RST_NR(0, 10), + [MT8188_VDO0_RST_DISP_WDMA0] =3D MMSYS_RST_NR(0, 17), + [MT8188_VDO0_RST_DISP_RDMA0] =3D MMSYS_RST_NR(0, 19), + [MT8188_VDO0_RST_DSI0] =3D MMSYS_RST_NR(0, 21), + [MT8188_VDO0_RST_DSI1] =3D MMSYS_RST_NR(0, 22), + [MT8188_VDO0_RST_DSC_WRAP0] =3D MMSYS_RST_NR(0, 23), + [MT8188_VDO0_RST_VPP_MERGE0] =3D MMSYS_RST_NR(0, 24), + [MT8188_VDO0_RST_DP_INTF0] =3D MMSYS_RST_NR(0, 25), + [MT8188_VDO0_RST_DISP_AAL0] =3D MMSYS_RST_NR(0, 26), + [MT8188_VDO0_RST_INLINEROT0] =3D MMSYS_RST_NR(0, 27), + [MT8188_VDO0_RST_APB_BUS] =3D MMSYS_RST_NR(0, 28), + [MT8188_VDO0_RST_DISP_COLOR0] =3D MMSYS_RST_NR(0, 29), + [MT8188_VDO0_RST_MDP_WROT0] =3D MMSYS_RST_NR(0, 30), + [MT8188_VDO0_RST_DISP_RSZ0] =3D MMSYS_RST_NR(0, 31), +}; + +static const u8 mmsys_mt8188_vdo1_rst_tb[] =3D { + [MT8188_VDO1_RST_SMI_LARB2] =3D MMSYS_RST_NR(0, 0), + [MT8188_VDO1_RST_SMI_LARB3] =3D MMSYS_RST_NR(0, 1), + [MT8188_VDO1_RST_GALS] =3D MMSYS_RST_NR(0, 2), + [MT8188_VDO1_RST_FAKE_ENG0] =3D MMSYS_RST_NR(0, 3), + [MT8188_VDO1_RST_FAKE_ENG1] =3D MMSYS_RST_NR(0, 4), + [MT8188_VDO1_RST_MDP_RDMA0] =3D MMSYS_RST_NR(0, 5), + [MT8188_VDO1_RST_MDP_RDMA1] =3D MMSYS_RST_NR(0, 6), + [MT8188_VDO1_RST_MDP_RDMA2] =3D MMSYS_RST_NR(0, 7), + [MT8188_VDO1_RST_MDP_RDMA3] =3D MMSYS_RST_NR(0, 8), + [MT8188_VDO1_RST_VPP_MERGE0] =3D MMSYS_RST_NR(0, 9), + [MT8188_VDO1_RST_VPP_MERGE1] =3D MMSYS_RST_NR(0, 10), + [MT8188_VDO1_RST_VPP_MERGE2] =3D MMSYS_RST_NR(0, 11), + [MT8188_VDO1_RST_VPP_MERGE3] =3D MMSYS_RST_NR(1, 0), + [MT8188_VDO1_RST_VPP_MERGE4] =3D MMSYS_RST_NR(1, 1), + [MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC] =3D MMSYS_RST_NR(1, 2), + [MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC] =3D MMSYS_RST_NR(1, 3), + [MT8188_VDO1_RST_DISP_MUTEX] =3D MMSYS_RST_NR(1, 4), + [MT8188_VDO1_RST_MDP_RDMA4] =3D MMSYS_RST_NR(1, 5), + [MT8188_VDO1_RST_MDP_RDMA5] =3D MMSYS_RST_NR(1, 6), + [MT8188_VDO1_RST_MDP_RDMA6] =3D MMSYS_RST_NR(1, 7), + [MT8188_VDO1_RST_MDP_RDMA7] =3D MMSYS_RST_NR(1, 8), + [MT8188_VDO1_RST_DP_INTF1_MMCK] =3D MMSYS_RST_NR(1, 9), + [MT8188_VDO1_RST_DPI0_MM_CK] =3D MMSYS_RST_NR(1, 10), + [MT8188_VDO1_RST_DPI1_MM_CK] =3D MMSYS_RST_NR(1, 11), + [MT8188_VDO1_RST_MERGE0_DL_ASYNC] =3D MMSYS_RST_NR(1, 13), + [MT8188_VDO1_RST_MERGE1_DL_ASYNC] =3D MMSYS_RST_NR(1, 14), + [MT8188_VDO1_RST_MERGE2_DL_ASYNC] =3D MMSYS_RST_NR(1, 15), + [MT8188_VDO1_RST_MERGE3_DL_ASYNC] =3D MMSYS_RST_NR(1, 16), + [MT8188_VDO1_RST_MERGE4_DL_ASYNC] =3D MMSYS_RST_NR(1, 17), + [MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_ASYNC] =3D MMSYS_RST_NR(1, 18), + [MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ASYNC] =3D MMSYS_RST_NR(1, 19), + [MT8188_VDO1_RST_PADDING0] =3D MMSYS_RST_NR(1, 20), + [MT8188_VDO1_RST_PADDING1] =3D MMSYS_RST_NR(1, 21), + [MT8188_VDO1_RST_PADDING2] =3D MMSYS_RST_NR(1, 22), + [MT8188_VDO1_RST_PADDING3] =3D MMSYS_RST_NR(1, 23), + [MT8188_VDO1_RST_PADDING4] =3D MMSYS_RST_NR(1, 24), + [MT8188_VDO1_RST_PADDING5] =3D MMSYS_RST_NR(1, 25), + [MT8188_VDO1_RST_PADDING6] =3D MMSYS_RST_NR(1, 26), + [MT8188_VDO1_RST_PADDING7] =3D MMSYS_RST_NR(1, 27), + [MT8188_VDO1_RST_DISP_RSZ0] =3D MMSYS_RST_NR(1, 28), + [MT8188_VDO1_RST_DISP_RSZ1] =3D MMSYS_RST_NR(1, 29), + [MT8188_VDO1_RST_DISP_RSZ2] =3D MMSYS_RST_NR(1, 30), + [MT8188_VDO1_RST_DISP_RSZ3] =3D MMSYS_RST_NR(1, 31), + [MT8188_VDO1_RST_HDR_VDO_FE0] =3D MMSYS_RST_NR(2, 0), + [MT8188_VDO1_RST_HDR_GFX_FE0] =3D MMSYS_RST_NR(2, 1), + [MT8188_VDO1_RST_HDR_VDO_BE] =3D MMSYS_RST_NR(2, 2), + [MT8188_VDO1_RST_HDR_VDO_FE1] =3D MMSYS_RST_NR(2, 16), + [MT8188_VDO1_RST_HDR_GFX_FE1] =3D MMSYS_RST_NR(2, 17), + [MT8188_VDO1_RST_DISP_MIXER] =3D MMSYS_RST_NR(2, 18), + [MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC] =3D MMSYS_RST_NR(2, 19), + [MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC] =3D MMSYS_RST_NR(2, 20), + [MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC] =3D MMSYS_RST_NR(2, 21), + [MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC] =3D MMSYS_RST_NR(2, 22), + [MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC] =3D MMSYS_RST_NR(2, 23), +}; + static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] =3D { { DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mm= sys.c index 3a7108eefe9d..a456c3e0aee7 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -87,13 +87,18 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys= 0_driver_data =3D { .clk_driver =3D "clk-mt8188-vdo0", .routes =3D mmsys_mt8188_routing_table, .num_routes =3D ARRAY_SIZE(mmsys_mt8188_routing_table), + .sw0_rst_offset =3D MT8188_VDO0_SW0_RST_B, + .rst_tb =3D mmsys_mt8188_vdo0_rst_tb, + .num_resets =3D ARRAY_SIZE(mmsys_mt8188_vdo0_rst_tb), }; =20 static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data =3D { .clk_driver =3D "clk-mt8188-vdo1", .routes =3D mmsys_mt8188_vdo1_routing_table, .num_routes =3D ARRAY_SIZE(mmsys_mt8188_vdo1_routing_table), - .num_resets =3D 96, + .sw0_rst_offset =3D MT8188_VDO1_SW0_RST_B, + .rst_tb =3D mmsys_mt8188_vdo1_rst_tb, + .num_resets =3D ARRAY_SIZE(mmsys_mt8188_vdo1_rst_tb), .vsync_len =3D 1, }; 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Wed, 18 Oct 2023 12:36:53 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 18 Oct 2023 12:36:53 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , CK Hu , Krzysztof Kozlowski , Matthias Brugger , Rob Herring CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Fei Shao , Sean Paul , Johnson Wang , "Nancy . Lin" , Moudy Ho , Hsiao Chien Sung , "Jason-JH . Lin" , Nathan Lu , , , , , Subject: [PATCH v9 11/23] drm/mediatek: Rename OVL_ADAPTOR_TYPE_RDMA Date: Wed, 18 Oct 2023 12:36:38 +0800 Message-ID: <20231018043650.22532-12-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231018043650.22532-1-shawn.sung@mediatek.com> References: <20231018043650.22532-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rename OVL_ADAPTOR_TYPE_RDMA to OVL_ADAPTOR_TYPE_MDP_RDMA to align the naming rule of mtk_ovl_adaptor_comp_id. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 22 +++++++++---------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index f2f6a5c01a6d..33b0f74937a2 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -26,7 +26,7 @@ #define MTK_OVL_ADAPTOR_LAYER_NUM 4 =20 enum mtk_ovl_adaptor_comp_type { - OVL_ADAPTOR_TYPE_RDMA =3D 0, + OVL_ADAPTOR_TYPE_MDP_RDMA =3D 0, OVL_ADAPTOR_TYPE_MERGE, OVL_ADAPTOR_TYPE_ETHDR, OVL_ADAPTOR_TYPE_NUM, @@ -61,20 +61,20 @@ struct mtk_disp_ovl_adaptor { }; =20 static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] =3D { - [OVL_ADAPTOR_TYPE_RDMA] =3D "vdo1-rdma", + [OVL_ADAPTOR_TYPE_MDP_RDMA] =3D "vdo1-rdma", [OVL_ADAPTOR_TYPE_MERGE] =3D "merge", [OVL_ADAPTOR_TYPE_ETHDR] =3D "ethdr", }; =20 static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX= ] =3D { - [OVL_ADAPTOR_MDP_RDMA0] =3D { OVL_ADAPTOR_TYPE_RDMA, 0 }, - [OVL_ADAPTOR_MDP_RDMA1] =3D { OVL_ADAPTOR_TYPE_RDMA, 1 }, - [OVL_ADAPTOR_MDP_RDMA2] =3D { OVL_ADAPTOR_TYPE_RDMA, 2 }, - [OVL_ADAPTOR_MDP_RDMA3] =3D { OVL_ADAPTOR_TYPE_RDMA, 3 }, - [OVL_ADAPTOR_MDP_RDMA4] =3D { OVL_ADAPTOR_TYPE_RDMA, 4 }, - [OVL_ADAPTOR_MDP_RDMA5] =3D { OVL_ADAPTOR_TYPE_RDMA, 5 }, - [OVL_ADAPTOR_MDP_RDMA6] =3D { OVL_ADAPTOR_TYPE_RDMA, 6 }, - [OVL_ADAPTOR_MDP_RDMA7] =3D { OVL_ADAPTOR_TYPE_RDMA, 7 }, + [OVL_ADAPTOR_MDP_RDMA0] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 0 }, + [OVL_ADAPTOR_MDP_RDMA1] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 1 }, + [OVL_ADAPTOR_MDP_RDMA2] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 2 }, + [OVL_ADAPTOR_MDP_RDMA3] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 3 }, + [OVL_ADAPTOR_MDP_RDMA4] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 4 }, + [OVL_ADAPTOR_MDP_RDMA5] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 5 }, + [OVL_ADAPTOR_MDP_RDMA6] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 6 }, + [OVL_ADAPTOR_MDP_RDMA7] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 7 }, [OVL_ADAPTOR_MERGE0] =3D { OVL_ADAPTOR_TYPE_MERGE, 1 }, [OVL_ADAPTOR_MERGE1] =3D { OVL_ADAPTOR_TYPE_MERGE, 2 }, [OVL_ADAPTOR_MERGE2] =3D { OVL_ADAPTOR_TYPE_MERGE, 3 }, @@ -387,7 +387,7 @@ static int ovl_adaptor_comp_get_id(struct device *dev, = struct device_node *node, static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] =3D { { .compatible =3D "mediatek,mt8195-vdo1-rdma", - .data =3D (void *)OVL_ADAPTOR_TYPE_RDMA, + .data =3D (void *)OVL_ADAPTOR_TYPE_MDP_RDMA, }, { .compatible =3D "mediatek,mt8195-disp-merge", .data =3D (void *)OVL_ADAPTOR_TYPE_MERGE, --=20 2.18.0 From nobody Fri Sep 20 10:01:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4A18CDB482 for ; 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Wed, 18 Oct 2023 12:36:53 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 18 Oct 2023 12:36:53 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 18 Oct 2023 12:36:53 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , CK Hu , Krzysztof Kozlowski , Matthias Brugger , Rob Herring CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Fei Shao , Sean Paul , Johnson Wang , "Nancy . Lin" , Moudy Ho , Hsiao Chien Sung , "Jason-JH . Lin" , Nathan Lu , , , , , Subject: [PATCH v9 12/23] drm/mediatek: Refine device table of OVL adaptor Date: Wed, 18 Oct 2023 12:36:39 +0800 Message-ID: <20231018043650.22532-13-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231018043650.22532-1-shawn.sung@mediatek.com> References: <20231018043650.22532-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" - Adjust indentation to align with other files - Sort device table in alphabetical order - Add sentinel to device table Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index 33b0f74937a2..1b39ee6957fc 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -385,17 +385,10 @@ static int ovl_adaptor_comp_get_id(struct device *dev= , struct device_node *node, } =20 static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] =3D { - { - .compatible =3D "mediatek,mt8195-vdo1-rdma", - .data =3D (void *)OVL_ADAPTOR_TYPE_MDP_RDMA, - }, { - .compatible =3D "mediatek,mt8195-disp-merge", - .data =3D (void *)OVL_ADAPTOR_TYPE_MERGE, - }, { - .compatible =3D "mediatek,mt8195-disp-ethdr", - .data =3D (void *)OVL_ADAPTOR_TYPE_ETHDR, - }, - {}, + { .compatible =3D "mediatek,mt8195-disp-ethdr", .data =3D (void *)OVL_ADA= PTOR_TYPE_ETHDR }, + { .compatible =3D "mediatek,mt8195-disp-merge", .data =3D (void *)OVL_ADA= PTOR_TYPE_MERGE }, + { .compatible =3D "mediatek,mt8195-vdo1-rdma", .data =3D (void *)OVL_ADAP= TOR_TYPE_MDP_RDMA }, + { /* sentinel */ } }; =20 static int compare_of(struct device *dev, void *data) --=20 2.18.0 From nobody Fri Sep 20 10:01:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE82FCDB482 for ; Wed, 18 Oct 2023 04:38:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235213AbjJREiO (ORCPT ); Wed, 18 Oct 2023 00:38:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43482 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234992AbjJREhN (ORCPT ); Wed, 18 Oct 2023 00:37:13 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E9BA1137; Tue, 17 Oct 2023 21:37:06 -0700 (PDT) X-UUID: f6c540a46d6f11ee8051498923ad61e6-20231018 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Wozuhtglut+ndUHShnMeAzlYbB4PJVGI5Nszul9Bf/4=; b=FflVIFDf1ZQYGpIkQKdohijnJDTooZB4STr4B/3FXps9tuQ8TwDwAruuv6f1s0S+X3lvreApu/yO1ttpO70zty2d1+iKa05BVCDU09r2DWqyPiGyAQLEDPCBrNJhYMBQFzeN4acbWAAN0Yg0xGUwj0I6jPEwXLwJGn4xqIg6uD0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:830d86c4-6277-426a-88ca-e84309d97db0,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5f78ec9,CLOUDID:0e2341c4-1e57-4345-9d31-31ad9818b39f,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: f6c540a46d6f11ee8051498923ad61e6-20231018 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 2126403504; Wed, 18 Oct 2023 12:36:54 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by MTKMBS14N2.mediatek.inc (172.21.101.76) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 18 Oct 2023 12:36:53 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 18 Oct 2023 12:36:53 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , "CK Hu" , Krzysztof Kozlowski , Matthias Brugger , Rob Herring CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Fei Shao , Sean Paul , Johnson Wang , "Nancy . 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Lin" , Nathan Lu , , , , , Subject: [PATCH v9 13/23] drm/mediatek: Sort OVL adaptor components Date: Wed, 18 Oct 2023 12:36:40 +0800 Message-ID: <20231018043650.22532-14-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231018043650.22532-1-shawn.sung@mediatek.com> References: <20231018043650.22532-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--7.685800-8.000000 X-TMASE-MatchedRID: quu5fX4+30yl84HKYQ35vJJAa1C/+FcuI9yVcHNDU7aOUV82NDH4ArEw JWI3UXVeT/ci3LQKeFGkV7miV6Ja8a6UR+fsf9oD9Jn/ZrGuc8GwR/wKmchi2clk/SMg0CpQo8W MkQWv6iXBcIE78YqRWo6HM5rqDwqtJaSK8G4paHjFOBYL3FhNDW7AVAZUmN5/Z4ZLVoZtDxC/ye 6c/iCV6A== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--7.685800-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 8029C103A0E2EE75ADF336BCE9F343C0F8A7AE7E552F965DAE6A8B4C0F4EA7622000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Sort OVL adaptor components' names in alphabetical order. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index 1b39ee6957fc..094e508ac70b 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -26,13 +26,14 @@ #define MTK_OVL_ADAPTOR_LAYER_NUM 4 =20 enum mtk_ovl_adaptor_comp_type { - OVL_ADAPTOR_TYPE_MDP_RDMA =3D 0, - OVL_ADAPTOR_TYPE_MERGE, OVL_ADAPTOR_TYPE_ETHDR, + OVL_ADAPTOR_TYPE_MDP_RDMA, + OVL_ADAPTOR_TYPE_MERGE, OVL_ADAPTOR_TYPE_NUM, }; =20 enum mtk_ovl_adaptor_comp_id { + OVL_ADAPTOR_ETHDR0, OVL_ADAPTOR_MDP_RDMA0, OVL_ADAPTOR_MDP_RDMA1, OVL_ADAPTOR_MDP_RDMA2, @@ -45,7 +46,6 @@ enum mtk_ovl_adaptor_comp_id { OVL_ADAPTOR_MERGE1, OVL_ADAPTOR_MERGE2, OVL_ADAPTOR_MERGE3, - OVL_ADAPTOR_ETHDR0, OVL_ADAPTOR_ID_MAX }; =20 @@ -61,12 +61,13 @@ struct mtk_disp_ovl_adaptor { }; =20 static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] =3D { + [OVL_ADAPTOR_TYPE_ETHDR] =3D "ethdr", [OVL_ADAPTOR_TYPE_MDP_RDMA] =3D "vdo1-rdma", [OVL_ADAPTOR_TYPE_MERGE] =3D "merge", - [OVL_ADAPTOR_TYPE_ETHDR] =3D "ethdr", }; =20 static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX= ] =3D { + [OVL_ADAPTOR_ETHDR0] =3D { OVL_ADAPTOR_TYPE_ETHDR, 0 }, [OVL_ADAPTOR_MDP_RDMA0] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 0 }, [OVL_ADAPTOR_MDP_RDMA1] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 1 }, [OVL_ADAPTOR_MDP_RDMA2] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 2 }, @@ -79,7 +80,6 @@ static const struct ovl_adaptor_comp_match comp_matches[O= VL_ADAPTOR_ID_MAX] =3D { [OVL_ADAPTOR_MERGE1] =3D { OVL_ADAPTOR_TYPE_MERGE, 2 }, [OVL_ADAPTOR_MERGE2] =3D { OVL_ADAPTOR_TYPE_MERGE, 3 }, [OVL_ADAPTOR_MERGE3] =3D { OVL_ADAPTOR_TYPE_MERGE, 4 }, - [OVL_ADAPTOR_ETHDR0] =3D { OVL_ADAPTOR_TYPE_ETHDR, 0 }, }; =20 void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx, @@ -313,6 +313,7 @@ size_t mtk_ovl_adaptor_get_num_formats(struct device *d= ev) =20 void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex) { + mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER); mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA0); mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA1); mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA2); @@ -325,11 +326,11 @@ void mtk_ovl_adaptor_add_comp(struct device *dev, str= uct mtk_mutex *mutex) mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE2); mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE3); mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE4); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER); } =20 void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mut= ex) { + mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER); mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA0); mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA1); mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA2); @@ -342,11 +343,11 @@ void mtk_ovl_adaptor_remove_comp(struct device *dev, = struct mtk_mutex *mutex) mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE2); mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE3); mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE4); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER); } =20 void mtk_ovl_adaptor_connect(struct device *dev, struct device *mmsys_dev,= unsigned int next) { + mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER, next); mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_M= ERGE1); mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_M= ERGE1); mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_M= ERGE2); @@ -354,11 +355,11 @@ void mtk_ovl_adaptor_connect(struct device *dev, stru= ct device *mmsys_dev, unsig mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHD= R_MIXER); mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHD= R_MIXER); mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHD= R_MIXER); - mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER, next); } =20 void mtk_ovl_adaptor_disconnect(struct device *dev, struct device *mmsys_d= ev, unsigned int next) { + mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER, next); mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MDP_RDMA0, DDP_COMPONEN= T_MERGE1); mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MDP_RDMA1, DDP_COMPONEN= T_MERGE1); mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MDP_RDMA2, DDP_COMPONEN= T_MERGE2); @@ -366,7 +367,6 @@ void mtk_ovl_adaptor_disconnect(struct device *dev, str= uct device *mmsys_dev, un mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE2, DDP_COMPONENT_E= THDR_MIXER); mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE3, DDP_COMPONENT_E= THDR_MIXER); mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE4, DDP_COMPONENT_E= THDR_MIXER); - mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER, next); } =20 static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node = *node, --=20 2.18.0 From nobody Fri Sep 20 10:01:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78CB6CDB484 for ; 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Wed, 18 Oct 2023 12:36:55 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 18 Oct 2023 12:36:53 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 18 Oct 2023 12:36:53 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , CK Hu , Krzysztof Kozlowski , Matthias Brugger , Rob Herring CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Fei Shao , Sean Paul , Johnson Wang , "Nancy . Lin" , Moudy Ho , Hsiao Chien Sung , "Jason-JH . Lin" , Nathan Lu , , , , , Subject: [PATCH v9 14/23] drm/mediatek: Add component ID to component match structure Date: Wed, 18 Oct 2023 12:36:41 +0800 Message-ID: <20231018043650.22532-15-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231018043650.22532-1-shawn.sung@mediatek.com> References: <20231018043650.22532-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add component ID to component match structure so we can configure them with a for-loop. The main reason we do such code refactoring is that there is a new hardware component called "Padding" since MT8188, while MT8195 doesn't have this module, we can't use the original logic to manage the components. While MT8195 does not define Padding in the device tree, the corresponding components will be NULL and being skipped by the functions. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 69 ++++++++----------- 1 file changed, 30 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index 094e508ac70b..60e5dfe9ef0d 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -51,6 +51,7 @@ enum mtk_ovl_adaptor_comp_id { =20 struct ovl_adaptor_comp_match { enum mtk_ovl_adaptor_comp_type type; + enum mtk_ddp_comp_id comp_id; int alias_id; }; =20 @@ -67,19 +68,19 @@ static const char * const private_comp_stem[OVL_ADAPTOR= _TYPE_NUM] =3D { }; =20 static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX= ] =3D { - [OVL_ADAPTOR_ETHDR0] =3D { OVL_ADAPTOR_TYPE_ETHDR, 0 }, - [OVL_ADAPTOR_MDP_RDMA0] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 0 }, - [OVL_ADAPTOR_MDP_RDMA1] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 1 }, - [OVL_ADAPTOR_MDP_RDMA2] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 2 }, - [OVL_ADAPTOR_MDP_RDMA3] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 3 }, - [OVL_ADAPTOR_MDP_RDMA4] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 4 }, - [OVL_ADAPTOR_MDP_RDMA5] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 5 }, - [OVL_ADAPTOR_MDP_RDMA6] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 6 }, - [OVL_ADAPTOR_MDP_RDMA7] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 7 }, - [OVL_ADAPTOR_MERGE0] =3D { OVL_ADAPTOR_TYPE_MERGE, 1 }, - [OVL_ADAPTOR_MERGE1] =3D { OVL_ADAPTOR_TYPE_MERGE, 2 }, - [OVL_ADAPTOR_MERGE2] =3D { OVL_ADAPTOR_TYPE_MERGE, 3 }, - [OVL_ADAPTOR_MERGE3] =3D { OVL_ADAPTOR_TYPE_MERGE, 4 }, + [OVL_ADAPTOR_ETHDR0] =3D { OVL_ADAPTOR_TYPE_ETHDR, DDP_COMPONENT_ETHDR_MI= XER, 0 }, + [OVL_ADAPTOR_MDP_RDMA0] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA0, 0 }, + [OVL_ADAPTOR_MDP_RDMA1] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA1, 1 }, + [OVL_ADAPTOR_MDP_RDMA2] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA2, 2 }, + [OVL_ADAPTOR_MDP_RDMA3] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA3, 3 }, + [OVL_ADAPTOR_MDP_RDMA4] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA4, 4 }, + [OVL_ADAPTOR_MDP_RDMA5] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA5, 5 }, + [OVL_ADAPTOR_MDP_RDMA6] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA6, 6 }, + [OVL_ADAPTOR_MDP_RDMA7] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA7, 7 }, + [OVL_ADAPTOR_MERGE0] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, = 1 }, + [OVL_ADAPTOR_MERGE1] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, = 2 }, + [OVL_ADAPTOR_MERGE2] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, = 3 }, + [OVL_ADAPTOR_MERGE3] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, = 4 }, }; =20 void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx, @@ -313,36 +314,26 @@ size_t mtk_ovl_adaptor_get_num_formats(struct device = *dev) =20 void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex) { - mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA0); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA1); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA2); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA3); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA4); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA5); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA6); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA7); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE1); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE2); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE3); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE4); + int i; + struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); + + for (i =3D 0; i < OVL_ADAPTOR_ID_MAX; i++) { + if (!ovl_adaptor->ovl_adaptor_comp[i]) + continue; + mtk_mutex_add_comp(mutex, comp_matches[i].comp_id); + } } =20 void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mut= ex) { - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA0); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA1); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA2); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA3); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA4); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA5); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA6); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA7); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE1); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE2); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE3); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE4); + int i; + struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); + + for (i =3D 0; i < OVL_ADAPTOR_ID_MAX; i++) { + if (!ovl_adaptor->ovl_adaptor_comp[i]) + continue; + mtk_mutex_remove_comp(mutex, comp_matches[i].comp_id); + } } =20 void mtk_ovl_adaptor_connect(struct device *dev, struct device *mmsys_dev,= unsigned int next) --=20 2.18.0 From nobody Fri Sep 20 10:01:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A7B9CDB47E for ; Wed, 18 Oct 2023 04:38:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235106AbjJREif (ORCPT ); Wed, 18 Oct 2023 00:38:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43324 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235040AbjJREhR (ORCPT ); Wed, 18 Oct 2023 00:37:17 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 17935181; 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Wed, 18 Oct 2023 12:36:55 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 18 Oct 2023 12:36:54 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 18 Oct 2023 12:36:54 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , CK Hu , Krzysztof Kozlowski , Matthias Brugger , Rob Herring CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Fei Shao , Sean Paul , Johnson Wang , "Nancy . Lin" , Moudy Ho , Hsiao Chien Sung , "Jason-JH . Lin" , Nathan Lu , , , , , Subject: [PATCH v9 15/23] drm/mediatek: Manage component's clock with function pointers Date: Wed, 18 Oct 2023 12:36:42 +0800 Message-ID: <20231018043650.22532-16-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231018043650.22532-1-shawn.sung@mediatek.com> References: <20231018043650.22532-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" By registering component related functions to the pointers, we can easily manage them within a for-loop and simplify the logic of clock control significantly. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 111 +++++++----------- 1 file changed, 44 insertions(+), 67 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index 60e5dfe9ef0d..233fced58b1a 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -53,6 +53,7 @@ struct ovl_adaptor_comp_match { enum mtk_ovl_adaptor_comp_type type; enum mtk_ddp_comp_id comp_id; int alias_id; + const struct mtk_ddp_comp_funcs *funcs; }; =20 struct mtk_disp_ovl_adaptor { @@ -67,20 +68,35 @@ static const char * const private_comp_stem[OVL_ADAPTOR= _TYPE_NUM] =3D { [OVL_ADAPTOR_TYPE_MERGE] =3D "merge", }; =20 +static const struct mtk_ddp_comp_funcs ethdr =3D { + .clk_enable =3D mtk_ethdr_clk_enable, + .clk_disable =3D mtk_ethdr_clk_disable, +}; + +static const struct mtk_ddp_comp_funcs merge =3D { + .clk_enable =3D mtk_merge_clk_enable, + .clk_disable =3D mtk_merge_clk_disable, +}; + +static const struct mtk_ddp_comp_funcs rdma =3D { + .clk_enable =3D mtk_mdp_rdma_clk_enable, + .clk_disable =3D mtk_mdp_rdma_clk_disable, +}; + static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX= ] =3D { - [OVL_ADAPTOR_ETHDR0] =3D { OVL_ADAPTOR_TYPE_ETHDR, DDP_COMPONENT_ETHDR_MI= XER, 0 }, - [OVL_ADAPTOR_MDP_RDMA0] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA0, 0 }, - [OVL_ADAPTOR_MDP_RDMA1] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA1, 1 }, - [OVL_ADAPTOR_MDP_RDMA2] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA2, 2 }, - [OVL_ADAPTOR_MDP_RDMA3] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA3, 3 }, - [OVL_ADAPTOR_MDP_RDMA4] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA4, 4 }, - [OVL_ADAPTOR_MDP_RDMA5] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA5, 5 }, - [OVL_ADAPTOR_MDP_RDMA6] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA6, 6 }, - [OVL_ADAPTOR_MDP_RDMA7] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA7, 7 }, - [OVL_ADAPTOR_MERGE0] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, = 1 }, - [OVL_ADAPTOR_MERGE1] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, = 2 }, - [OVL_ADAPTOR_MERGE2] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, = 3 }, - [OVL_ADAPTOR_MERGE3] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, = 4 }, + [OVL_ADAPTOR_ETHDR0] =3D { OVL_ADAPTOR_TYPE_ETHDR, DDP_COMPONENT_ETHDR_MI= XER, 0, ðdr }, + [OVL_ADAPTOR_MDP_RDMA0] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA0, 0, &rdma }, + [OVL_ADAPTOR_MDP_RDMA1] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA1, 1, &rdma }, + [OVL_ADAPTOR_MDP_RDMA2] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA2, 2, &rdma }, + [OVL_ADAPTOR_MDP_RDMA3] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA3, 3, &rdma }, + [OVL_ADAPTOR_MDP_RDMA4] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA4, 4, &rdma }, + [OVL_ADAPTOR_MDP_RDMA5] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA5, 5, &rdma }, + [OVL_ADAPTOR_MDP_RDMA6] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA6, 6, &rdma }, + [OVL_ADAPTOR_MDP_RDMA7] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA7, 7, &rdma }, + [OVL_ADAPTOR_MERGE0] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, = 1, &merge }, + [OVL_ADAPTOR_MERGE1] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, = 2, &merge }, + [OVL_ADAPTOR_MERGE2] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, = 3, &merge }, + [OVL_ADAPTOR_MERGE3] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, = 4, &merge }, }; =20 void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx, @@ -186,73 +202,34 @@ void mtk_ovl_adaptor_stop(struct device *dev) =20 int mtk_ovl_adaptor_clk_enable(struct device *dev) { - struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); - struct device *comp; - int ret; int i; - - for (i =3D 0; i < OVL_ADAPTOR_MERGE0; i++) { - comp =3D ovl_adaptor->ovl_adaptor_comp[i]; - ret =3D pm_runtime_get_sync(comp); - if (ret < 0) { - dev_err(dev, "Failed to enable power domain %d, err %d\n", i, ret); - goto pwr_err; - } - } + int ret; + struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); =20 for (i =3D 0; i < OVL_ADAPTOR_ID_MAX; i++) { - comp =3D ovl_adaptor->ovl_adaptor_comp[i]; - - if (i < OVL_ADAPTOR_MERGE0) - ret =3D mtk_mdp_rdma_clk_enable(comp); - else if (i < OVL_ADAPTOR_ETHDR0) - ret =3D mtk_merge_clk_enable(comp); - else - ret =3D mtk_ethdr_clk_enable(comp); + dev =3D ovl_adaptor->ovl_adaptor_comp[i]; + if (!dev) + continue; + ret =3D comp_matches[i].funcs->clk_enable(dev); if (ret) { - dev_err(dev, "Failed to enable clock %d, err %d\n", i, ret); - goto clk_err; + while (--i >=3D 0) + comp_matches[i].funcs->clk_disable(dev); + return ret; } } - - return ret; - -clk_err: - while (--i >=3D 0) { - comp =3D ovl_adaptor->ovl_adaptor_comp[i]; - if (i < OVL_ADAPTOR_MERGE0) - mtk_mdp_rdma_clk_disable(comp); - else if (i < OVL_ADAPTOR_ETHDR0) - mtk_merge_clk_disable(comp); - else - mtk_ethdr_clk_disable(comp); - } - i =3D OVL_ADAPTOR_MERGE0; - -pwr_err: - while (--i >=3D 0) - pm_runtime_put(ovl_adaptor->ovl_adaptor_comp[i]); - - return ret; + return 0; } =20 void mtk_ovl_adaptor_clk_disable(struct device *dev) { - struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); - struct device *comp; int i; + struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); =20 for (i =3D 0; i < OVL_ADAPTOR_ID_MAX; i++) { - comp =3D ovl_adaptor->ovl_adaptor_comp[i]; - - if (i < OVL_ADAPTOR_MERGE0) { - mtk_mdp_rdma_clk_disable(comp); - pm_runtime_put(comp); - } else if (i < OVL_ADAPTOR_ETHDR0) { - mtk_merge_clk_disable(comp); - } else { - mtk_ethdr_clk_disable(comp); - } + dev =3D ovl_adaptor->ovl_adaptor_comp[i]; + if (!dev) + continue; + comp_matches[i].funcs->clk_disable(dev); } } =20 --=20 2.18.0 From nobody Fri Sep 20 10:01:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5ADDDCDB482 for ; Wed, 18 Oct 2023 04:38:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235210AbjJREiK (ORCPT ); Wed, 18 Oct 2023 00:38:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42390 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229609AbjJREhP (ORCPT ); Wed, 18 Oct 2023 00:37:15 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED1D1138; Tue, 17 Oct 2023 21:37:06 -0700 (PDT) X-UUID: f6d48a6e6d6f11ee8051498923ad61e6-20231018 DKIM-Signature: v=1; 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Wed, 18 Oct 2023 12:36:54 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 18 Oct 2023 12:36:54 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 18 Oct 2023 12:36:54 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , CK Hu , Krzysztof Kozlowski , Matthias Brugger , Rob Herring CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Fei Shao , Sean Paul , Johnson Wang , "Nancy . Lin" , Moudy Ho , Hsiao Chien Sung , "Jason-JH . Lin" , Nathan Lu , , , , , Subject: [PATCH v9 16/23] drm/mediatek: Start/Stop components with function pointers Date: Wed, 18 Oct 2023 12:36:43 +0800 Message-ID: <20231018043650.22532-17-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231018043650.22532-1-shawn.sung@mediatek.com> References: <20231018043650.22532-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" By registering component related functions to the pointers, we can easily manage them within a for-loop and simplify the logic of component start/stop process. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 20 +++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index 233fced58b1a..249d2182ebc7 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -71,6 +71,8 @@ static const char * const private_comp_stem[OVL_ADAPTOR_T= YPE_NUM] =3D { static const struct mtk_ddp_comp_funcs ethdr =3D { .clk_enable =3D mtk_ethdr_clk_enable, .clk_disable =3D mtk_ethdr_clk_disable, + .start =3D mtk_ethdr_start, + .stop =3D mtk_ethdr_stop, }; =20 static const struct mtk_ddp_comp_funcs merge =3D { @@ -188,16 +190,30 @@ void mtk_ovl_adaptor_config(struct device *dev, unsig= ned int w, =20 void mtk_ovl_adaptor_start(struct device *dev) { + int i; struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); =20 - mtk_ethdr_start(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]); + for (i =3D 0; i < OVL_ADAPTOR_ID_MAX; i++) { + if (!ovl_adaptor->ovl_adaptor_comp[i] || + !comp_matches[i].funcs->start) + continue; + + comp_matches[i].funcs->start(ovl_adaptor->ovl_adaptor_comp[i]); + } } =20 void mtk_ovl_adaptor_stop(struct device *dev) { + int i; struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); =20 - mtk_ethdr_stop(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]); + for (i =3D 0; i < OVL_ADAPTOR_ID_MAX; i++) { + if (!ovl_adaptor->ovl_adaptor_comp[i] || + !comp_matches[i].funcs->stop) + continue; + + comp_matches[i].funcs->stop(ovl_adaptor->ovl_adaptor_comp[i]); + } } =20 int mtk_ovl_adaptor_clk_enable(struct device *dev) --=20 2.18.0 From nobody Fri Sep 20 10:01:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 936FFCDB484 for ; Wed, 18 Oct 2023 04:37:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235149AbjJREhb (ORCPT ); Wed, 18 Oct 2023 00:37:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57902 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229568AbjJREhF (ORCPT ); Wed, 18 Oct 2023 00:37:05 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D3143114; Tue, 17 Oct 2023 21:37:00 -0700 (PDT) X-UUID: f7927b286d6f11eea33bb35ae8d461a2-20231018 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=fBp8D9+EAwKOY3y2YVlHPUSUnL+1ODd4IO467XsPJps=; b=tj4VGs/kwLBRQCIFliSqGnu/KcTvw3OszZAOVDjnWkjcrwJarAtfZ42kvNGkwczz/+4KIgVdYZ6UvozjkzYWOB5MY85FfR1BmUtFlICMOyj3KzgjnzvnT9h60T8L83ydZv/0y7hhcrrWzsHpLSQ/+1uzr8ENj+zMfntID0+wSls=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:b06e0eea-b2a5-4b3b-989b-e68e5c7b1a68,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:5f78ec9,CLOUDID:a754ecf0-9a6e-4c39-b73e-f2bc08ca3dc5,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: f7927b286d6f11eea33bb35ae8d461a2-20231018 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 112848407; Wed, 18 Oct 2023 12:36:55 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 18 Oct 2023 12:36:54 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 18 Oct 2023 12:36:54 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , CK Hu , Krzysztof Kozlowski , Matthias Brugger , Rob Herring CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Fei Shao , Sean Paul , Johnson Wang , "Nancy . Lin" , Moudy Ho , Hsiao Chien Sung , "Jason-JH . Lin" , Nathan Lu , , , , , Subject: [PATCH v9 17/23] drm/mediatek: Support MT8188 Padding in display driver Date: Wed, 18 Oct 2023 12:36:44 +0800 Message-ID: <20231018043650.22532-18-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231018043650.22532-1-shawn.sung@mediatek.com> References: <20231018043650.22532-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Padding is a new display module on MT8188, it provides ability to add pixels to width and height of a layer with specified colors. Due to hardware design, Mixer in VDOSYS1 requires width of a layer to be 2-pixel-align, or 4-pixel-align when ETHDR is enabled, we need Padding to deal with odd width. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/Makefile | 3 +- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 4 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +- drivers/gpu/drm/mediatek/mtk_padding.c | 160 ++++++++++++++++++++++++ 5 files changed, 168 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_padding.c diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/M= akefile index d4d193f60271..5e4436403b8d 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -16,7 +16,8 @@ mediatek-drm-y :=3D mtk_disp_aal.o \ mtk_dsi.o \ mtk_dpi.o \ mtk_ethdr.o \ - mtk_mdp_rdma.o + mtk_mdp_rdma.o \ + mtk_padding.o =20 obj-$(CONFIG_DRM_MEDIATEK) +=3D mediatek-drm.o =20 diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/medi= atek/mtk_disp_drv.h index bf06ccb65652..e2b602037ac3 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -159,4 +159,8 @@ void mtk_mdp_rdma_config(struct device *dev, struct mtk= _mdp_rdma_cfg *cfg, const u32 *mtk_mdp_rdma_get_formats(struct device *dev); size_t mtk_mdp_rdma_get_num_formats(struct device *dev); =20 +int mtk_padding_clk_enable(struct device *dev); +void mtk_padding_clk_disable(struct device *dev); +void mtk_padding_start(struct device *dev); +void mtk_padding_stop(struct device *dev); #endif diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index cdce165c092e..62e6e9785443 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -1025,6 +1025,7 @@ static struct platform_driver * const mtk_drm_drivers= [] =3D { &mtk_dsi_driver, &mtk_ethdr_driver, &mtk_mdp_rdma_driver, + &mtk_padding_driver, }; =20 static int __init mtk_drm_init(void) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/media= tek/mtk_drm_drv.h index 8dca68ea1b94..d2efd715699f 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -72,5 +72,5 @@ extern struct platform_driver mtk_dpi_driver; extern struct platform_driver mtk_dsi_driver; extern struct platform_driver mtk_ethdr_driver; extern struct platform_driver mtk_mdp_rdma_driver; - +extern struct platform_driver mtk_padding_driver; #endif /* MTK_DRM_DRV_H */ diff --git a/drivers/gpu/drm/mediatek/mtk_padding.c b/drivers/gpu/drm/media= tek/mtk_padding.c new file mode 100644 index 000000000000..14efb6ab2341 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_padding.c @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "mtk_disp_drv.h" +#include "mtk_drm_crtc.h" +#include "mtk_drm_ddp_comp.h" + +#define PADDING_CONTROL_REG 0x00 +#define PADDING_BYPASS BIT(0) +#define PADDING_ENABLE BIT(1) +#define PADDING_PIC_SIZE_REG 0x04 +#define PADDING_H_REG 0x08 /* horizontal */ +#define PADDING_V_REG 0x0c /* vertical */ +#define PADDING_COLOR_REG 0x10 + +/** + * struct mtk_padding - Basic information of the Padding + * @clk: Clock of the module + * @reg: Virtual address of the Padding for CPU to access + * @cmdq_reg: CMDQ setting of the Padding + * + * Every Padding should have different clock source, register base, and + * CMDQ settings, we stored these differences all together. + */ +struct mtk_padding { + struct clk *clk; + void __iomem *reg; + struct cmdq_client_reg cmdq_reg; +}; + +int mtk_padding_clk_enable(struct device *dev) +{ + struct mtk_padding *padding =3D dev_get_drvdata(dev); + + return clk_prepare_enable(padding->clk); +} + +void mtk_padding_clk_disable(struct device *dev) +{ + struct mtk_padding *padding =3D dev_get_drvdata(dev); + + clk_disable_unprepare(padding->clk); +} + +void mtk_padding_start(struct device *dev) +{ + struct mtk_padding *padding =3D dev_get_drvdata(dev); + + writel(PADDING_ENABLE | PADDING_BYPASS, + padding->reg + PADDING_CONTROL_REG); + + /* + * Notice that even the padding is in bypass mode, + * all the settings must be cleared to 0 or + * undefined behaviors could happen + */ + writel(0, padding->reg + PADDING_PIC_SIZE_REG); + writel(0, padding->reg + PADDING_H_REG); + writel(0, padding->reg + PADDING_V_REG); + writel(0, padding->reg + PADDING_COLOR_REG); +} + +void mtk_padding_stop(struct device *dev) +{ + struct mtk_padding *padding =3D dev_get_drvdata(dev); + + writel(0, padding->reg + PADDING_CONTROL_REG); +} + +static int mtk_padding_bind(struct device *dev, struct device *master, voi= d *data) +{ + return 0; +} + +static void mtk_padding_unbind(struct device *dev, struct device *master, = void *data) +{ +} + +static const struct component_ops mtk_padding_component_ops =3D { + .bind =3D mtk_padding_bind, + .unbind =3D mtk_padding_unbind, +}; + +static int mtk_padding_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct mtk_padding *priv; + struct resource *res; + int ret; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->clk =3D devm_clk_get(dev, NULL); + if (IS_ERR(priv->clk)) { + dev_err(dev, "failed to get clk\n"); + return PTR_ERR(priv->clk); + } + + priv->reg =3D devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(priv->reg)) { + dev_err(dev, "failed to do ioremap\n"); + return PTR_ERR(priv->reg); + } + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + ret =3D cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); + if (ret) { + dev_err(dev, "failed to get gce client reg\n"); + return ret; + } +#endif + + platform_set_drvdata(pdev, priv); + + ret =3D devm_pm_runtime_enable(dev); + if (ret) + return ret; + + ret =3D component_add(dev, &mtk_padding_component_ops); + if (ret) { + pm_runtime_disable(dev); + return dev_err_probe(dev, ret, "failed to add component\n"); + } + + return 0; +} + +static int mtk_padding_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &mtk_padding_component_ops); + return 0; +} + +static const struct of_device_id mtk_padding_driver_dt_match[] =3D { + { .compatible =3D "mediatek,mt8188-padding" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, mtk_padding_driver_dt_match); + +struct platform_driver mtk_padding_driver =3D { + .probe =3D mtk_padding_probe, + .remove =3D mtk_padding_remove, + .driver =3D { + .name =3D "mediatek-disp-padding", + .owner =3D THIS_MODULE, + .of_match_table =3D mtk_padding_driver_dt_match, + }, +}; --=20 2.18.0 From nobody Fri Sep 20 10:01:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 052E6CDB482 for ; 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Lin" , Moudy Ho , Hsiao Chien Sung , "Jason-JH . Lin" , Nathan Lu , , , , , Subject: [PATCH v9 18/23] drm/mediatek: Add Padding to OVL adaptor Date: Wed, 18 Oct 2023 12:36:45 +0800 Message-ID: <20231018043650.22532-19-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231018043650.22532-1-shawn.sung@mediatek.com> References: <20231018043650.22532-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add MT8188 Padding to OVL adaptor to probe the driver. Reviewed-by: CK Hu Signed-off-by: Hsiao Chien Sung Reviewed-by: AngeloGioacchino Del Regno --- .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index 249d2182ebc7..753a7f829173 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -29,6 +29,7 @@ enum mtk_ovl_adaptor_comp_type { OVL_ADAPTOR_TYPE_ETHDR, OVL_ADAPTOR_TYPE_MDP_RDMA, OVL_ADAPTOR_TYPE_MERGE, + OVL_ADAPTOR_TYPE_PADDING, OVL_ADAPTOR_TYPE_NUM, }; =20 @@ -46,6 +47,14 @@ enum mtk_ovl_adaptor_comp_id { OVL_ADAPTOR_MERGE1, OVL_ADAPTOR_MERGE2, OVL_ADAPTOR_MERGE3, + OVL_ADAPTOR_PADDING0, + OVL_ADAPTOR_PADDING1, + OVL_ADAPTOR_PADDING2, + OVL_ADAPTOR_PADDING3, + OVL_ADAPTOR_PADDING4, + OVL_ADAPTOR_PADDING5, + OVL_ADAPTOR_PADDING6, + OVL_ADAPTOR_PADDING7, OVL_ADAPTOR_ID_MAX }; =20 @@ -66,6 +75,7 @@ static const char * const private_comp_stem[OVL_ADAPTOR_T= YPE_NUM] =3D { [OVL_ADAPTOR_TYPE_ETHDR] =3D "ethdr", [OVL_ADAPTOR_TYPE_MDP_RDMA] =3D "vdo1-rdma", [OVL_ADAPTOR_TYPE_MERGE] =3D "merge", + [OVL_ADAPTOR_TYPE_PADDING] =3D "padding", }; =20 static const struct mtk_ddp_comp_funcs ethdr =3D { @@ -80,6 +90,13 @@ static const struct mtk_ddp_comp_funcs merge =3D { .clk_disable =3D mtk_merge_clk_disable, }; =20 +static const struct mtk_ddp_comp_funcs padding =3D { + .clk_enable =3D mtk_padding_clk_enable, + .clk_disable =3D mtk_padding_clk_disable, + .start =3D mtk_padding_start, + .stop =3D mtk_padding_stop, +}; + static const struct mtk_ddp_comp_funcs rdma =3D { .clk_enable =3D mtk_mdp_rdma_clk_enable, .clk_disable =3D mtk_mdp_rdma_clk_disable, @@ -99,6 +116,14 @@ static const struct ovl_adaptor_comp_match comp_matches= [OVL_ADAPTOR_ID_MAX] =3D { [OVL_ADAPTOR_MERGE1] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, = 2, &merge }, [OVL_ADAPTOR_MERGE2] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, = 3, &merge }, [OVL_ADAPTOR_MERGE3] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, = 4, &merge }, + [OVL_ADAPTOR_PADDING0] =3D { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADD= ING0, 0, &padding }, + [OVL_ADAPTOR_PADDING1] =3D { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADD= ING1, 1, &padding }, + [OVL_ADAPTOR_PADDING2] =3D { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADD= ING2, 2, &padding }, + [OVL_ADAPTOR_PADDING3] =3D { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADD= ING3, 3, &padding }, + [OVL_ADAPTOR_PADDING4] =3D { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADD= ING4, 4, &padding }, + [OVL_ADAPTOR_PADDING5] =3D { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADD= ING5, 5, &padding }, + [OVL_ADAPTOR_PADDING6] =3D { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADD= ING6, 6, &padding }, + [OVL_ADAPTOR_PADDING7] =3D { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADD= ING7, 7, &padding }, }; =20 void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx, @@ -369,6 +394,7 @@ static int ovl_adaptor_comp_get_id(struct device *dev, = struct device_node *node, } =20 static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] =3D { + { .compatible =3D "mediatek,mt8188-padding", .data =3D (void *)OVL_ADAPTO= R_TYPE_PADDING }, { .compatible =3D "mediatek,mt8195-disp-ethdr", .data =3D (void *)OVL_ADA= PTOR_TYPE_ETHDR }, { .compatible =3D "mediatek,mt8195-disp-merge", .data =3D (void *)OVL_ADA= PTOR_TYPE_MERGE }, { .compatible =3D "mediatek,mt8195-vdo1-rdma", .data =3D (void *)OVL_ADAP= TOR_TYPE_MDP_RDMA }, --=20 2.18.0 From nobody Fri Sep 20 10:01:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 525B9CDB484 for ; Wed, 18 Oct 2023 04:38:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235239AbjJREik (ORCPT ); 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Lin" , Moudy Ho , Hsiao Chien Sung , "Jason-JH . Lin" , Nathan Lu , , , , , Subject: [PATCH v9 19/23] drm/mediatek: Return error if MDP RDMA failed to enable the clock Date: Wed, 18 Oct 2023 12:36:46 +0800 Message-ID: <20231018043650.22532-20-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231018043650.22532-1-shawn.sung@mediatek.com> References: <20231018043650.22532-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--2.708200-8.000000 X-TMASE-MatchedRID: dXJslEWlJ68PRVepDWIjx2NW0DAjL5p+Wot5Z16+u77vnm3ZesFzgvKC 81FnsF5IrUhQzMxACbr/9kP++bIewpcFdomgH0lnFEUknJ/kEl5q8/xv2Um1avoLR4+zsDTtrXT /QMyU2NxH9jHR2PGQD2j/1IQ2AqP08KC9+XOIoEH6RbO+ZghcVQIK4nTjGJzqA2KUQ0lkfh7GF2 Hf257q/N5paBsuHYsdG11BE5QqteN2a1GxGYqQBIlk9PZkM+7M8PZB/MwMuOEiHbpOSZI3d8C+k sT6a9fy X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--2.708200-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: CCA9D36BCEC2C426F4342BA2F5B9DB2CC651E91EEE6B34EB5009BE12E577917B2000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Return the result of clk_prepare_enable() instead of always returns 0. Fixes: f8946e2b6bb2 ("drm/mediatek: Add display MDP RDMA support for MT8195= ") Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/medi= atek/mtk_mdp_rdma.c index 5746f06220c1..cb36a961786f 100644 --- a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c @@ -247,8 +247,7 @@ int mtk_mdp_rdma_clk_enable(struct device *dev) { struct mtk_mdp_rdma *rdma =3D dev_get_drvdata(dev); =20 - clk_prepare_enable(rdma->clk); - return 0; + return clk_prepare_enable(rdma->clk); } =20 void mtk_mdp_rdma_clk_disable(struct device *dev) --=20 2.18.0 From nobody Fri Sep 20 10:01:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68E45CDB47E for ; Wed, 18 Oct 2023 04:38:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235078AbjJREiA (ORCPT ); Wed, 18 Oct 2023 00:38:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43450 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234947AbjJREhM (ORCPT ); Wed, 18 Oct 2023 00:37:12 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 136F7120; Tue, 17 Oct 2023 21:37:02 -0700 (PDT) X-UUID: f7f36a8c6d6f11eea33bb35ae8d461a2-20231018 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=WTOeBIDjwXjGhqKsLqsXHoxBxxG+10elJsW9pXcqeO0=; b=AWBEEaWCI4Q8BZrlLhEmV9wGYgCBFs5GsK1wH68rCAhQqeHSW8ReyEUULYMOp58Rs8VrVlW6VJyp8uTWTLKsk494YMEkRVKJlfmTPRa2l2onJ0J7ed9S2cixMsyRf66V5l7PmpVFfiDz32Dxe1SkHYQ5vbU7JmslJN4IEteencM=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:30884643-6bee-4da2-9a8a-14c71876d0ee,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:5f78ec9,CLOUDID:1e2341c4-1e57-4345-9d31-31ad9818b39f,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: f7f36a8c6d6f11eea33bb35ae8d461a2-20231018 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1834920141; Wed, 18 Oct 2023 12:36:56 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 18 Oct 2023 12:36:55 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 18 Oct 2023 12:36:55 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , CK Hu , Krzysztof Kozlowski , Matthias Brugger , Rob Herring CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Fei Shao , Sean Paul , Johnson Wang , "Nancy . Lin" , Moudy Ho , Hsiao Chien Sung , "Jason-JH . Lin" , Nathan Lu , , , , , Subject: [PATCH v9 20/23] drm/mediatek: Remove the redundant driver data for DPI Date: Wed, 18 Oct 2023 12:36:47 +0800 Message-ID: <20231018043650.22532-21-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231018043650.22532-1-shawn.sung@mediatek.com> References: <20231018043650.22532-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" DPI input is in 1T2P mode on both MT8195 and MT8188. Remove the redundant driver data to align the settings, or the screen will glitch. Fixes: 2847cd7e6403 ("drm/mediatek: Add mt8188 dpi compatibles and platform= data") Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_dpi.c | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 1bf6041dd88b..d633f1ca3e71 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -967,20 +967,6 @@ static const struct mtk_dpi_conf mt8186_conf =3D { .csc_enable_bit =3D CSC_ENABLE, }; =20 -static const struct mtk_dpi_conf mt8188_dpintf_conf =3D { - .cal_factor =3D mt8195_dpintf_calculate_factor, - .max_clock_khz =3D 600000, - .output_fmts =3D mt8195_output_fmts, - .num_output_fmts =3D ARRAY_SIZE(mt8195_output_fmts), - .pixels_per_iter =3D 4, - .input_2pixel =3D false, - .dimension_mask =3D DPINTF_HPW_MASK, - .hvsize_mask =3D DPINTF_HSIZE_MASK, - .channel_swap_shift =3D DPINTF_CH_SWAP, - .yuv422_en_bit =3D DPINTF_YUV422_EN, - .csc_enable_bit =3D DPINTF_CSC_ENABLE, -}; - static const struct mtk_dpi_conf mt8192_conf =3D { .cal_factor =3D mt8183_calculate_factor, .reg_h_fre_con =3D 0xe0, @@ -1104,7 +1090,7 @@ static const struct of_device_id mtk_dpi_of_ids[] =3D= { { .compatible =3D "mediatek,mt8173-dpi", .data =3D &mt8173_conf }, { .compatible =3D "mediatek,mt8183-dpi", .data =3D &mt8183_conf }, { .compatible =3D "mediatek,mt8186-dpi", .data =3D &mt8186_conf }, - { .compatible =3D "mediatek,mt8188-dp-intf", .data =3D &mt8188_dpintf_con= f }, + { .compatible =3D "mediatek,mt8188-dp-intf", .data =3D &mt8195_dpintf_con= f }, { .compatible =3D "mediatek,mt8192-dpi", .data =3D &mt8192_conf }, { .compatible =3D "mediatek,mt8195-dp-intf", .data =3D &mt8195_dpintf_con= f }, { /* sentinel */ }, --=20 2.18.0 From nobody Fri Sep 20 10:01:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE766CDB47E for ; Wed, 18 Oct 2023 04:38:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235232AbjJREi3 (ORCPT ); Wed, 18 Oct 2023 00:38:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43406 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229960AbjJREhL (ORCPT ); Wed, 18 Oct 2023 00:37:11 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF75F12C; Tue, 17 Oct 2023 21:37:04 -0700 (PDT) X-UUID: f83243386d6f11eea33bb35ae8d461a2-20231018 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=mEL9/fhI8H1OiHxV2ftXuZpY23MuQ9WuJPFzjUyfFPI=; b=QuoO8tcurqJzsdwQUcvzVxubSjDyovMjUxaREOU6KD6IF/aEm9xLa5TlydkNEGGL9U9b8cwjxDGJAst7KiPV3cCGxfluYA3myvF/wc3X4k+XUCgMDDL96KuqhM+Mwh67YjYeW4CrrSqtGEFGJGm+OCEvO8Ze4bp1x5tWgoiswaE=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:27fb2572-d02d-41d3-8e1d-b5f744663824,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5f78ec9,CLOUDID:c654ecf0-9a6e-4c39-b73e-f2bc08ca3dc5,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: f83243386d6f11eea33bb35ae8d461a2-20231018 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 907582089; Wed, 18 Oct 2023 12:36:56 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 18 Oct 2023 12:36:55 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 18 Oct 2023 12:36:55 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , "CK Hu" , Krzysztof Kozlowski , Matthias Brugger , Rob Herring CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Fei Shao , Sean Paul , Johnson Wang , "Nancy . Lin" , Moudy Ho , Hsiao Chien Sung , "Jason-JH . Lin" , Nathan Lu , , , , , Subject: [PATCH v9 21/23] drm/mediatek: Fix underrun in VDO1 when switches off the layer Date: Wed, 18 Oct 2023 12:36:48 +0800 Message-ID: <20231018043650.22532-22-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231018043650.22532-1-shawn.sung@mediatek.com> References: <20231018043650.22532-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--0.429600-8.000000 X-TMASE-MatchedRID: aRklFmtZ23BQlz7zzALRPqKa0xB73sAA7yWPaQc4INS0rcU5V/oSe8Ht HEmxq9+YYM3P0vRsc0DnftxNodBrx0c58yUI8WvNQ4srjeRbxTZCX8V1FiRRkjdlsYL2g/87xhL ap7By3FlX6UIPOG+iLYAGGZdCG6IYHxPMjOKY7A8LbigRnpKlKZvjAepGmdoOuzWZSe9bpwlKMn xvHPr3Lj/S/4Fp/m7C70j4gBQf6c8A81qNtiL9iCjCD/8vFIPkWsiUW0takmD4VH37RoClPds5P cWL6yHKSZrfNhP3sgUBh9AgBSEFrJm+YJspVvj2xkvrHlT8euJ0YHKn7N1oOA== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--0.429600-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: B69116BBDFA26A38753769A567F83B654D12FAFD761723071AD6C13AB233A24B2000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Do not reset Merge while using CMDQ because reset API doesn't wait for frame done event as CMDQ does and could lead to underrun when the layer is switching off. Fixes: aaf94f7c3ae6 ("drm/mediatek: Add display merge async reset control") Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_merge.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/me= diatek/mtk_disp_merge.c index fd14a59bc951..c19fb1836034 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c @@ -104,7 +104,7 @@ void mtk_merge_stop_cmdq(struct device *dev, struct cmd= q_pkt *cmdq_pkt) mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CTRL); =20 - if (priv->async_clk) + if (!cmdq_pkt && priv->async_clk) reset_control_reset(priv->reset_ctl); } =20 --=20 2.18.0 From nobody Fri Sep 20 10:01:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5AAFCDB485 for ; Wed, 18 Oct 2023 04:38:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235227AbjJREiX (ORCPT ); Wed, 18 Oct 2023 00:38:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42500 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234920AbjJREhL (ORCPT ); Wed, 18 Oct 2023 00:37:11 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D861212B; Tue, 17 Oct 2023 21:37:04 -0700 (PDT) X-UUID: f7f560946d6f11eea33bb35ae8d461a2-20231018 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=gbjXlNeTaWOAgDiP7qRRiuPNtFIqTcPeM3WN/tA9eQc=; b=ryoyhtcAHbLBDDANTvUppiSI1ByEbt9C68EBbUX65/c9Ho5QarPp1+S1dSpMFb3f2yNTvXKkjrkrf9imdXgnfPMqjm8/kK9ZGh0TSceFgdZlE412pF+n4Bb5VfosbbeOJEV+vAaJ3WRj5tHA/RnqLNG/FH1NIivWTrT1NjnpDmE=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:73db61d0-2d51-4da6-9096-b620122767fa,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:5f78ec9,CLOUDID:1d392a15-4929-4845-9571-38c601e9c3c9,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: f7f560946d6f11eea33bb35ae8d461a2-20231018 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1464819507; Wed, 18 Oct 2023 12:36:56 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 18 Oct 2023 12:36:55 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 18 Oct 2023 12:36:55 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , CK Hu , Krzysztof Kozlowski , Matthias Brugger , Rob Herring CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Fei Shao , Sean Paul , Johnson Wang , "Nancy . Lin" , Moudy Ho , Hsiao Chien Sung , "Jason-JH . Lin" , Nathan Lu , , , , , Subject: [PATCH v9 22/23] drm/mediatek: Power on devices in OVL adaptor when atomic enable Date: Wed, 18 Oct 2023 12:36:49 +0800 Message-ID: <20231018043650.22532-23-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231018043650.22532-1-shawn.sung@mediatek.com> References: <20231018043650.22532-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Different from OVL, OVL adaptor is a pseudo device so we didn't define it in the device tree, consequently, pm_runtime_resume_and_get() called by .atomic_enable() powers on no device in OVL adaptor and leads to power outage in the corresponding IOMMU. To resolve the issue, we implement a function to power on the RDMAs in OVL adaptor, and the system will make sure the IOMMU is powered on as well because of the device link (iommus) in the RDMA nodes in DTS. Signed-off-by: Hsiao Chien Sung Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 4 ++ .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 63 +++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 28 +++------ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 20 ++++++ drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 16 +++++ 6 files changed, 112 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/medi= atek/mtk_disp_drv.h index e2b602037ac3..c44f5b31bab5 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -109,6 +109,8 @@ void mtk_ovl_adaptor_connect(struct device *dev, struct= device *mmsys_dev, unsigned int next); void mtk_ovl_adaptor_disconnect(struct device *dev, struct device *mmsys_d= ev, unsigned int next); +int mtk_ovl_adaptor_power_on(struct device *dev); +void mtk_ovl_adaptor_power_off(struct device *dev); int mtk_ovl_adaptor_clk_enable(struct device *dev); void mtk_ovl_adaptor_clk_disable(struct device *dev); void mtk_ovl_adaptor_config(struct device *dev, unsigned int w, @@ -150,6 +152,8 @@ void mtk_rdma_disable_vblank(struct device *dev); const u32 *mtk_rdma_get_formats(struct device *dev); size_t mtk_rdma_get_num_formats(struct device *dev); =20 +int mtk_mdp_rdma_power_on(struct device *dev); +void mtk_mdp_rdma_power_off(struct device *dev); int mtk_mdp_rdma_clk_enable(struct device *dev); void mtk_mdp_rdma_clk_disable(struct device *dev); void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index 753a7f829173..35bbce35b7b5 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -98,6 +98,8 @@ static const struct mtk_ddp_comp_funcs padding =3D { }; =20 static const struct mtk_ddp_comp_funcs rdma =3D { + .power_on =3D mtk_mdp_rdma_power_on, + .power_off =3D mtk_mdp_rdma_power_off, .clk_enable =3D mtk_mdp_rdma_clk_enable, .clk_disable =3D mtk_mdp_rdma_clk_disable, }; @@ -241,6 +243,67 @@ void mtk_ovl_adaptor_stop(struct device *dev) } } =20 +/** + * power_off - Power off the devices in OVL adaptor + * @dev: Device to be powered off + * @num: Number of the devices to be powered off + * + * Calls the .power_off() ovl_adaptor component callback if it is present. + */ +static inline void power_off(struct device *dev, unsigned int num) +{ + int i; + struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); + + if (num > OVL_ADAPTOR_ID_MAX) + num =3D OVL_ADAPTOR_ID_MAX; + + for (i =3D num - 1; i >=3D 0; i--) { + if (!ovl_adaptor->ovl_adaptor_comp[i] || + !comp_matches[i].funcs->power_off) + continue; + + comp_matches[i].funcs->power_off(ovl_adaptor->ovl_adaptor_comp[i]); + } +} + +/** + * mtk_ovl_adaptor_power_on - Power on the devices in OVL adaptor + * @dev: Device to be powered on + * + * Different from OVL, OVL adaptor is a pseudo device so + * we didn't define it in the device tree, pm_runtime_resume_and_get() + * called by .atomic_enable() power on no device in OVL adaptor, + * we have to implement a function to do the job instead. + * + * Return: Zero for success or negative number for failure. + */ +int mtk_ovl_adaptor_power_on(struct device *dev) +{ + int i, ret; + struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); + + for (i =3D 0; i < OVL_ADAPTOR_ID_MAX; i++) { + if (!ovl_adaptor->ovl_adaptor_comp[i] || + !comp_matches[i].funcs->power_on) + continue; + + ret =3D comp_matches[i].funcs->power_on(ovl_adaptor->ovl_adaptor_comp[i]= ); + if (ret < 0) { + dev_err(ovl_adaptor->ovl_adaptor_comp[i], + "Failed to power on: %d\n", ret); + power_off(dev, i); + return ret; + } + } + return 0; +} + +void mtk_ovl_adaptor_power_off(struct device *dev) +{ + power_off(dev, OVL_ADAPTOR_ID_MAX); +} + int mtk_ovl_adaptor_clk_enable(struct device *dev) { int i; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/medi= atek/mtk_drm_crtc.c index a0b2ba3cbcdb..c7edd80be428 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include @@ -362,22 +361,16 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *= mtk_crtc, struct drm_atomic drm_connector_list_iter_end(&conn_iter); } =20 - ret =3D pm_runtime_resume_and_get(crtc->dev->dev); - if (ret < 0) { - DRM_ERROR("Failed to enable power domain: %d\n", ret); - return ret; - } - ret =3D mtk_mutex_prepare(mtk_crtc->mutex); if (ret < 0) { DRM_ERROR("Failed to enable mutex clock: %d\n", ret); - goto err_pm_runtime_put; + goto error; } =20 ret =3D mtk_crtc_ddp_clk_enable(mtk_crtc); if (ret < 0) { DRM_ERROR("Failed to enable component clocks: %d\n", ret); - goto err_mutex_unprepare; + goto error; } =20 for (i =3D 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { @@ -426,16 +419,13 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *= mtk_crtc, struct drm_atomic =20 return 0; =20 -err_mutex_unprepare: +error: mtk_mutex_unprepare(mtk_crtc->mutex); -err_pm_runtime_put: - pm_runtime_put(crtc->dev->dev); return ret; } =20 static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) { - struct drm_device *drm =3D mtk_crtc->base.dev; struct drm_crtc *crtc =3D &mtk_crtc->base; int i; =20 @@ -465,8 +455,6 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *m= tk_crtc) mtk_crtc_ddp_clk_disable(mtk_crtc); mtk_mutex_unprepare(mtk_crtc->mutex); =20 - pm_runtime_put(drm->dev); - if (crtc->state->event && !crtc->state->active) { spin_lock_irq(&crtc->dev->event_lock); drm_crtc_send_vblank_event(crtc, crtc->state->event); @@ -774,7 +762,7 @@ static void mtk_drm_crtc_atomic_enable(struct drm_crtc = *crtc, return; } =20 - ret =3D pm_runtime_resume_and_get(comp->dev); + ret =3D mtk_ddp_comp_power_on(comp); if (ret < 0) { DRM_DEV_ERROR(comp->dev, "Failed to enable power domain: %d\n", ret); return; @@ -782,7 +770,7 @@ static void mtk_drm_crtc_atomic_enable(struct drm_crtc = *crtc, =20 ret =3D mtk_crtc_ddp_hw_init(mtk_crtc, state); if (ret) { - pm_runtime_put(comp->dev); + mtk_ddp_comp_power_off(comp); return; } =20 @@ -795,7 +783,7 @@ static void mtk_drm_crtc_atomic_disable(struct drm_crtc= *crtc, { struct mtk_drm_crtc *mtk_crtc =3D to_mtk_crtc(crtc); struct mtk_ddp_comp *comp =3D mtk_crtc->ddp_comp[0]; - int i, ret; + int i; =20 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); if (!mtk_crtc->enabled) @@ -825,9 +813,7 @@ static void mtk_drm_crtc_atomic_disable(struct drm_crtc= *crtc, =20 drm_crtc_vblank_off(crtc); mtk_crtc_ddp_hw_fini(mtk_crtc); - ret =3D pm_runtime_put(comp->dev); - if (ret < 0) - DRM_DEV_ERROR(comp->dev, "Failed to disable power domain: %d\n", ret); + mtk_ddp_comp_power_off(comp); =20 mtk_crtc->enabled =3D false; } diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/= mediatek/mtk_drm_ddp_comp.c index 10402e07a4a7..9940909c7435 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -396,6 +396,8 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe =3D { }; =20 static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor =3D { + .power_on =3D mtk_ovl_adaptor_power_on, + .power_off =3D mtk_ovl_adaptor_power_off, .clk_enable =3D mtk_ovl_adaptor_clk_enable, .clk_disable =3D mtk_ovl_adaptor_clk_disable, .config =3D mtk_ovl_adaptor_config, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/= mediatek/mtk_drm_ddp_comp.h index 1c1d670cfe41..2597dd7ac0d2 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -7,6 +7,7 @@ #define MTK_DRM_DDP_COMP_H =20 #include +#include #include #include #include @@ -46,6 +47,8 @@ enum mtk_ddp_comp_type { struct mtk_ddp_comp; struct cmdq_pkt; struct mtk_ddp_comp_funcs { + int (*power_on)(struct device *dev); + void (*power_off)(struct device *dev); int (*clk_enable)(struct device *dev); void (*clk_disable)(struct device *dev); void (*config)(struct device *dev, unsigned int w, @@ -91,6 +94,23 @@ struct mtk_ddp_comp { int encoder_index; }; =20 +static inline int mtk_ddp_comp_power_on(struct mtk_ddp_comp *comp) +{ + if (comp->funcs && comp->funcs->power_on) + return comp->funcs->power_on(comp->dev); + else + return pm_runtime_resume_and_get(comp->dev); + return 0; +} + +static inline void mtk_ddp_comp_power_off(struct mtk_ddp_comp *comp) +{ + if (comp->funcs && comp->funcs->power_off) + comp->funcs->power_off(comp->dev); + else + pm_runtime_put(comp->dev); +} + static inline int mtk_ddp_comp_clk_enable(struct mtk_ddp_comp *comp) { if (comp->funcs && comp->funcs->clk_enable) diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/medi= atek/mtk_mdp_rdma.c index cb36a961786f..8feeb6dce217 100644 --- a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c @@ -243,6 +243,22 @@ size_t mtk_mdp_rdma_get_num_formats(struct device *dev) return ARRAY_SIZE(formats); } =20 +int mtk_mdp_rdma_power_on(struct device *dev) +{ + int ret =3D pm_runtime_resume_and_get(dev); + + if (ret < 0) { + dev_err(dev, "Failed to power on: %d\n", ret); + return ret; + } + return 0; +} + +void mtk_mdp_rdma_power_off(struct device *dev) +{ + pm_runtime_put(dev); +} + int mtk_mdp_rdma_clk_enable(struct device *dev) { struct mtk_mdp_rdma *rdma =3D dev_get_drvdata(dev); --=20 2.18.0 From nobody Fri Sep 20 10:01:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 491FBCDB47E for ; Wed, 18 Oct 2023 04:38:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235114AbjJREih (ORCPT ); Wed, 18 Oct 2023 00:38:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48258 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235051AbjJREhS (ORCPT ); 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Lin" , Moudy Ho , Hsiao Chien Sung , "Jason-JH . Lin" , Nathan Lu , , , , , Subject: [PATCH v9 23/23] drm/mediatek: Support MT8188 VDOSYS1 in display driver Date: Wed, 18 Oct 2023 12:36:50 +0800 Message-ID: <20231018043650.22532-24-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231018043650.22532-1-shawn.sung@mediatek.com> References: <20231018043650.22532-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--6.544100-8.000000 X-TMASE-MatchedRID: k6EjByr1NNCA1UdczcLx7jvfsoCuAcP+uLwbhNl9B5VcKZwALwMGs43y qnCHUnfZLYexjI/F2s67aBKK8e6y8yUtdpGicV4RKaMQ6tw7oDJMkOX0UoduuQqiCYa6w8tv5pf 3ZiBJgsHc0NDBaoYShZjXlVZ6P0cvj2hRzH1UwuAURSScn+QSXt0H8LFZNFG7bkV4e2xSge4sw3 GEmIriBSUhMPBH5sX4M517nGGNRDAnSTeZe+bs5kuFvzEYSdV+ X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--6.544100-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 6E07A7877B63CCB3C2FBE579486332D138706BCC3CB03C55AC1BDD9B991DECE02000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" - The mmsys_dev_num in MT8188 VDOSYS0 was set to 1 since VDOSYS1 was not available before. Increase it to support VDOSYS1 in display driver. - Add compatible name for MT8188 VDOSYS1 (shares the same driver data with MT8195 VDOSYS1) Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index 62e6e9785443..eecfeb8fbde1 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -303,7 +303,7 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys= 0_driver_data =3D { .main_len =3D ARRAY_SIZE(mt8188_mtk_ddp_main), .conn_routes =3D mt8188_mtk_ddp_main_routes, .conn_routes_num =3D ARRAY_SIZE(mt8188_mtk_ddp_main_routes), - .mmsys_dev_num =3D 1, + .mmsys_dev_num =3D 2, }; =20 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data =3D { @@ -344,6 +344,8 @@ static const struct of_device_id mtk_drm_of_ids[] =3D { .data =3D &mt8186_mmsys_driver_data}, { .compatible =3D "mediatek,mt8188-vdosys0", .data =3D &mt8188_vdosys0_driver_data}, + { .compatible =3D "mediatek,mt8188-vdosys1", + .data =3D &mt8195_vdosys1_driver_data}, { .compatible =3D "mediatek,mt8192-mmsys", .data =3D &mt8192_mmsys_driver_data}, { .compatible =3D "mediatek,mt8195-mmsys", --=20 2.18.0