From nobody Wed Dec 17 14:38:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00F74CDB47E for ; Wed, 18 Oct 2023 22:51:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232177AbjJRWvR (ORCPT ); Wed, 18 Oct 2023 18:51:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231549AbjJRWvK (ORCPT ); Wed, 18 Oct 2023 18:51:10 -0400 Received: from mail-oo1-xc29.google.com (mail-oo1-xc29.google.com [IPv6:2607:f8b0:4864:20::c29]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7D44C115 for ; Wed, 18 Oct 2023 15:51:07 -0700 (PDT) Received: by mail-oo1-xc29.google.com with SMTP id 006d021491bc7-581cb88f645so1494702eaf.1 for ; Wed, 18 Oct 2023 15:51:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697669467; x=1698274267; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=S1uOkf1NiZkarUauiGeyDxtxxY4fQFa9Lo8cXzDP0vs=; b=AcmNrYpDQWgcZUNnm5umYc02Clq9qBGBqRGWriv2E0EGAXrZy4XhPr0b9c9Oh5MnUv 8m+W625HkPj15OjLfhc28KXfARQjFiI6wmVpcjlzlWvyczMFxOKXbdP0cRBWFZzH8YyO vx5QQxcm+bxxuZQWq93anzAUZ4yA7zk6GrLDzJ2XfG7TC9je7KeRxZ3O4IRrH1K7iyqv hPi9bIqWTYTUTQ6odaSrdumnSPC7WfWd4fB2fx3qXyjL1LUuZbp1lmc7R4VaSvKa9g5/ CLLIG/3MPcI0qy7EukESkSr844lUQ27H7zUthrFUPA/0NBg+QYSleNpeyMO4kAydvzng cLeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697669467; x=1698274267; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=S1uOkf1NiZkarUauiGeyDxtxxY4fQFa9Lo8cXzDP0vs=; b=GHCEtk7Zppu/1S1/s6bpjlY2t8SKWmdWAz2zVng70k0UunFYWm9QoKHJEj9aXecZM+ lvsD3RulDkUMVmiNaKoWnYHCn3hB27DQIKAsx/FQJX0Bfxu5nyVLjSPNCv/QJ9vBSOeG JNwVmmuAaUMFHzm5AEf+Pg77eiBugd3+qMEXIvhpqd/GQFMzFZ81H+fpWHHNblOJfwnW ibNfxQUVaThAT+lYM+jYLed5oGTNj9A3L4rznPuuOCcnDeTjWpT9g0dcY7PxAe+T4hk2 FDGGRICzfhsQjh70riV1rYXk4OfZzjzX5P55YRAM4aoBL54D/O36ZWauCYktBA22lZEx hJDg== X-Gm-Message-State: AOJu0YwuAJvrpxqydW9KD87fc9y9KhrjUWUGeGnN6csMzeEjJ0wEJGn8 txlrknBiCG8FPWInVMPBOcel7g== X-Google-Smtp-Source: AGHT+IEtzWz8g24fWgfdHYEKhHWGC54JwBMSLU7IRf5/BYXnJUN90eqa3OVgEHJ/ffOIkrQrMaT9yA== X-Received: by 2002:a4a:c50a:0:b0:582:1a20:7cb8 with SMTP id i10-20020a4ac50a000000b005821a207cb8mr702837ooq.0.1697669466854; Wed, 18 Oct 2023 15:51:06 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id r195-20020a4a37cc000000b00581e7506f2fsm641134oor.9.2023.10.18.15.51.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 15:51:06 -0700 (PDT) From: Charlie Jenkins Date: Wed, 18 Oct 2023 15:51:02 -0700 Subject: [PATCH v5 2/3] riscv: Add remaining module relocations MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231018-module_relocations-v5-2-dfee32d4dfc3@rivosinc.com> References: <20231018-module_relocations-v5-0-dfee32d4dfc3@rivosinc.com> In-Reply-To: <20231018-module_relocations-v5-0-dfee32d4dfc3@rivosinc.com> To: linux-riscv@lists.infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Cc: Eric Biederman , Kees Cook , Paul Walmsley , Palmer Dabbelt , Albert Ou , Andreas Schwab , Emil Renner Berthing , Samuel Holland , Charlie Jenkins X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add all final module relocations and add error logs explaining the ones that are not supported. Signed-off-by: Charlie Jenkins --- arch/riscv/include/uapi/asm/elf.h | 5 +- arch/riscv/kernel/module.c | 220 +++++++++++++++++++++++++++++++++-= ---- 2 files changed, 199 insertions(+), 26 deletions(-) diff --git a/arch/riscv/include/uapi/asm/elf.h b/arch/riscv/include/uapi/as= m/elf.h index d696d6610231..11a71b8533d5 100644 --- a/arch/riscv/include/uapi/asm/elf.h +++ b/arch/riscv/include/uapi/asm/elf.h @@ -49,6 +49,7 @@ typedef union __riscv_fp_state elf_fpregset_t; #define R_RISCV_TLS_DTPREL64 9 #define R_RISCV_TLS_TPREL32 10 #define R_RISCV_TLS_TPREL64 11 +#define R_RISCV_IRELATIVE 58 =20 /* Relocation types not used by the dynamic linker */ #define R_RISCV_BRANCH 16 @@ -81,7 +82,6 @@ typedef union __riscv_fp_state elf_fpregset_t; #define R_RISCV_ALIGN 43 #define R_RISCV_RVC_BRANCH 44 #define R_RISCV_RVC_JUMP 45 -#define R_RISCV_LUI 46 #define R_RISCV_GPREL_I 47 #define R_RISCV_GPREL_S 48 #define R_RISCV_TPREL_I 49 @@ -93,6 +93,9 @@ typedef union __riscv_fp_state elf_fpregset_t; #define R_RISCV_SET16 55 #define R_RISCV_SET32 56 #define R_RISCV_32_PCREL 57 +#define R_RISCV_PLT32 59 +#define R_RISCV_SET_ULEB128 60 +#define R_RISCV_SUB_ULEB128 61 =20 =20 #endif /* _UAPI_ASM_RISCV_ELF_H */ diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index a9e94e939cb5..3a3d342c09be 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/module.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -269,6 +270,12 @@ static int apply_r_riscv_align_rela(struct module *me,= void *location, return -EINVAL; } =20 +static int apply_r_riscv_add8_rela(struct module *me, void *location, Elf_= Addr v) +{ + *(u8 *)location +=3D (u8)v; + return 0; +} + static int apply_r_riscv_add16_rela(struct module *me, void *location, Elf_Addr v) { @@ -290,6 +297,12 @@ static int apply_r_riscv_add64_rela(struct module *me,= void *location, return 0; } =20 +static int apply_r_riscv_sub8_rela(struct module *me, void *location, Elf_= Addr v) +{ + *(u8 *)location -=3D (u8)v; + return 0; +} + static int apply_r_riscv_sub16_rela(struct module *me, void *location, Elf_Addr v) { @@ -311,31 +324,162 @@ static int apply_r_riscv_sub64_rela(struct module *m= e, void *location, return 0; } =20 -static int (*reloc_handlers_rela[]) (struct module *me, void *location, - Elf_Addr v) =3D { - [R_RISCV_32] =3D apply_r_riscv_32_rela, - [R_RISCV_64] =3D apply_r_riscv_64_rela, - [R_RISCV_BRANCH] =3D apply_r_riscv_branch_rela, - [R_RISCV_JAL] =3D apply_r_riscv_jal_rela, - [R_RISCV_RVC_BRANCH] =3D apply_r_riscv_rvc_branch_rela, - [R_RISCV_RVC_JUMP] =3D apply_r_riscv_rvc_jump_rela, - [R_RISCV_PCREL_HI20] =3D apply_r_riscv_pcrel_hi20_rela, - [R_RISCV_PCREL_LO12_I] =3D apply_r_riscv_pcrel_lo12_i_rela, - [R_RISCV_PCREL_LO12_S] =3D apply_r_riscv_pcrel_lo12_s_rela, - [R_RISCV_HI20] =3D apply_r_riscv_hi20_rela, - [R_RISCV_LO12_I] =3D apply_r_riscv_lo12_i_rela, - [R_RISCV_LO12_S] =3D apply_r_riscv_lo12_s_rela, - [R_RISCV_GOT_HI20] =3D apply_r_riscv_got_hi20_rela, - [R_RISCV_CALL_PLT] =3D apply_r_riscv_call_plt_rela, - [R_RISCV_CALL] =3D apply_r_riscv_call_rela, - [R_RISCV_RELAX] =3D apply_r_riscv_relax_rela, - [R_RISCV_ALIGN] =3D apply_r_riscv_align_rela, - [R_RISCV_ADD16] =3D apply_r_riscv_add16_rela, - [R_RISCV_ADD32] =3D apply_r_riscv_add32_rela, - [R_RISCV_ADD64] =3D apply_r_riscv_add64_rela, - [R_RISCV_SUB16] =3D apply_r_riscv_sub16_rela, - [R_RISCV_SUB32] =3D apply_r_riscv_sub32_rela, - [R_RISCV_SUB64] =3D apply_r_riscv_sub64_rela, +static int dynamic_linking_not_supported(struct module *me, void *location, + Elf_Addr v) +{ + pr_err("%s: Dynamic linking not supported in kernel modules PC =3D %p\n", + me->name, location); + return -EINVAL; +} + +static int tls_not_supported(struct module *me, void *location, Elf_Addr v) +{ + pr_err("%s: Thread local storage not supported in kernel modules PC =3D %= p\n", + me->name, location); + return -EINVAL; +} + +static int apply_r_riscv_sub6_rela(struct module *me, void *location, Elf_= Addr v) +{ + *(u8 *)location =3D (*(u8 *)location - ((u8)v & 0x3F)) & 0x3F; + return 0; +} + +static int apply_r_riscv_set6_rela(struct module *me, void *location, Elf_= Addr v) +{ + *(u8 *)location =3D ((*(u8 *)location & 0xc0) | ((u8)v & 0x3F)); + return 0; +} + +static int apply_r_riscv_set8_rela(struct module *me, void *location, Elf_= Addr v) +{ + *(u8 *)location =3D (u8)v; + return 0; +} + +static int apply_r_riscv_set16_rela(struct module *me, void *location, + Elf_Addr v) +{ + *(u16 *)location =3D (u16)v; + return 0; +} + +static int apply_r_riscv_set32_rela(struct module *me, void *location, + Elf_Addr v) +{ + *(u32 *)location =3D (u32)v; + return 0; +} + +static int apply_r_riscv_32_pcrel_rela(struct module *me, void *location, + Elf_Addr v) +{ + *(u32 *)location =3D v - (unsigned long)location; + return 0; +} + +static int apply_r_riscv_plt32_rela(struct module *me, void *location, + Elf_Addr v) +{ + ptrdiff_t offset =3D (void *)v - location; + + if (!riscv_insn_valid_32bit_offset(offset)) { + /* Only emit the plt entry if offset over 32-bit range */ + if (IS_ENABLED(CONFIG_MODULE_SECTIONS)) { + offset =3D (void *)module_emit_plt_entry(me, v) - location; + } else { + pr_err("%s: target %016llx can not be addressed by the 32-bit offset fr= om PC =3D %p\n", + me->name, (long long)v, location); + return -EINVAL; + } + } + + *(u32 *)location =3D (u32)offset; + return 0; +} + +static int apply_r_riscv_set_uleb128(struct module *me, void *location, El= f_Addr v) +{ + /* + * Relocation is only performed if R_RISCV_SET_ULEB128 is followed by + * R_RISCV_SUB_ULEB128 so do computation there + */ + return 0; +} + +static int apply_r_riscv_sub_uleb128(struct module *me, void *location, El= f_Addr v) +{ + if (v >=3D 128) { + pr_err("%s: uleb128 must be in [0, 127] (not %ld) at PC =3D %p\n", + me->name, (unsigned long)v, location); + return -EINVAL; + } + + *(u32 *)location =3D (*(u32 *)location & ~((u32)127)) | (v & 127); + return 0; +} + +/* + * Relocations defined in the riscv-elf-psabi-doc. + * This handles static linking only. + */ +static int (*reloc_handlers_rela[])(struct module *me, u32 *location, + Elf_Addr v) =3D { + [R_RISCV_32] =3D apply_r_riscv_32_rela, + [R_RISCV_64] =3D apply_r_riscv_64_rela, + [R_RISCV_RELATIVE] =3D dynamic_linking_not_supported, + [R_RISCV_COPY] =3D dynamic_linking_not_supported, + [R_RISCV_JUMP_SLOT] =3D dynamic_linking_not_supported, + [R_RISCV_TLS_DTPMOD32] =3D dynamic_linking_not_supported, + [R_RISCV_TLS_DTPMOD64] =3D dynamic_linking_not_supported, + [R_RISCV_TLS_DTPREL32] =3D dynamic_linking_not_supported, + [R_RISCV_TLS_DTPREL64] =3D dynamic_linking_not_supported, + [R_RISCV_TLS_TPREL32] =3D dynamic_linking_not_supported, + [R_RISCV_TLS_TPREL64] =3D dynamic_linking_not_supported, + /* 12-15 undefined */ + [R_RISCV_BRANCH] =3D apply_r_riscv_branch_rela, + [R_RISCV_JAL] =3D apply_r_riscv_jal_rela, + [R_RISCV_CALL] =3D apply_r_riscv_call_rela, + [R_RISCV_CALL_PLT] =3D apply_r_riscv_call_plt_rela, + [R_RISCV_GOT_HI20] =3D apply_r_riscv_got_hi20_rela, + [R_RISCV_TLS_GOT_HI20] =3D tls_not_supported, + [R_RISCV_TLS_GD_HI20] =3D tls_not_supported, + [R_RISCV_PCREL_HI20] =3D apply_r_riscv_pcrel_hi20_rela, + [R_RISCV_PCREL_LO12_I] =3D apply_r_riscv_pcrel_lo12_i_rela, + [R_RISCV_PCREL_LO12_S] =3D apply_r_riscv_pcrel_lo12_s_rela, + [R_RISCV_HI20] =3D apply_r_riscv_hi20_rela, + [R_RISCV_LO12_I] =3D apply_r_riscv_lo12_i_rela, + [R_RISCV_LO12_S] =3D apply_r_riscv_lo12_s_rela, + [R_RISCV_TPREL_HI20] =3D tls_not_supported, + [R_RISCV_TPREL_LO12_I] =3D tls_not_supported, + [R_RISCV_TPREL_LO12_S] =3D tls_not_supported, + [R_RISCV_TPREL_ADD] =3D tls_not_supported, + [R_RISCV_ADD8] =3D apply_r_riscv_add8_rela, + [R_RISCV_ADD16] =3D apply_r_riscv_add16_rela, + [R_RISCV_ADD32] =3D apply_r_riscv_add32_rela, + [R_RISCV_ADD64] =3D apply_r_riscv_add64_rela, + [R_RISCV_SUB8] =3D apply_r_riscv_sub8_rela, + [R_RISCV_SUB16] =3D apply_r_riscv_sub16_rela, + [R_RISCV_SUB32] =3D apply_r_riscv_sub32_rela, + [R_RISCV_SUB64] =3D apply_r_riscv_sub64_rela, + /* 41-42 reserved for future standard use */ + [R_RISCV_ALIGN] =3D apply_r_riscv_align_rela, + [R_RISCV_RVC_BRANCH] =3D apply_r_riscv_rvc_branch_rela, + [R_RISCV_RVC_JUMP] =3D apply_r_riscv_rvc_jump_rela, + /* 46-50 reserved for future standard use */ + [R_RISCV_RELAX] =3D apply_r_riscv_relax_rela, + [R_RISCV_SUB6] =3D apply_r_riscv_sub6_rela, + [R_RISCV_SET6] =3D apply_r_riscv_set6_rela, + [R_RISCV_SET8] =3D apply_r_riscv_set8_rela, + [R_RISCV_SET16] =3D apply_r_riscv_set16_rela, + [R_RISCV_SET32] =3D apply_r_riscv_set32_rela, + [R_RISCV_32_PCREL] =3D apply_r_riscv_32_pcrel_rela, + [R_RISCV_IRELATIVE] =3D dynamic_linking_not_supported, + [R_RISCV_PLT32] =3D apply_r_riscv_plt32_rela, + [R_RISCV_SET_ULEB128] =3D apply_r_riscv_set_uleb128, + [R_RISCV_SUB_ULEB128] =3D apply_r_riscv_sub_uleb128, + /* 62-191 reserved for future standard use */ + /* 192-255 nonstandard ABI extensions */ }; =20 int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, @@ -349,6 +493,9 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *s= trtab, unsigned int i, type; Elf_Addr v; int res; + bool uleb128_set_exists =3D false; + u32 *uleb128_set_loc; + unsigned long uleb128_set_sym_val; =20 pr_debug("Applying relocate section %u to %u\n", relsec, sechdrs[relsec].sh_info); @@ -426,6 +573,29 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *= strtab, me->name); return -EINVAL; } + } else if (type =3D=3D R_RISCV_SET_ULEB128) { + if (uleb128_set_exists) { + pr_err("%s: riscv psABI requires the next ULEB128 relocation to come a= fter a R_RISCV_SET_ULEB128 is an R_RISCV_SUB_ULEB128, not another R_RISCV_S= ET_ULEB128.\n", + me->name); + return -EINVAL; + } + uleb128_set_exists =3D true; + uleb128_set_loc =3D location; + uleb128_set_sym_val =3D + ((Elf_Sym *)sechdrs[symindex].sh_addr + + ELF_RISCV_R_SYM(rel[i].r_info)) + ->st_value + + rel[i].r_addend; + } else if (type =3D=3D R_RISCV_SUB_ULEB128) { + if (uleb128_set_exists && uleb128_set_loc =3D=3D location) { + /* Calculate set and subtraction */ + v =3D uleb128_set_sym_val - v; + } else { + pr_err("%s: R_RISCV_SUB_ULEB128 must always be paired with the first R= _RISCV_SET_ULEB128 that comes before it. PC =3D %p\n", + me->name, location); + return -EINVAL; + } + uleb128_set_exists =3D false; } =20 res =3D handler(me, location, v); --=20 2.42.0