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RISC-V instructions are in fact an ordered list of 16bit little-endian "parcels", so access the instruction as such. This should also make the code work in case someone builds a big-endian RISC-V machine. Signed-off-by: Emil Renner Berthing Signed-off-by: Charlie Jenkins --- arch/riscv/kernel/module.c | 153 +++++++++++++++++++++++------------------= ---- 1 file changed, 77 insertions(+), 76 deletions(-) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 7c651d55fcbd..a9e94e939cb5 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/module.c @@ -27,68 +27,86 @@ static bool riscv_insn_valid_32bit_offset(ptrdiff_t val) #endif } =20 -static int apply_r_riscv_32_rela(struct module *me, u32 *location, Elf_Add= r v) +static int riscv_insn_rmw(void *location, u32 keep, u32 set) +{ + u16 *parcel =3D location; + u32 insn =3D (u32)le16_to_cpu(parcel[0]) | (u32)le16_to_cpu(parcel[1]) <<= 16; + + insn &=3D keep; + insn |=3D set; + + parcel[0] =3D cpu_to_le32(insn); + parcel[1] =3D cpu_to_le16(insn >> 16); + return 0; +} + +static int riscv_insn_rvc_rmw(void *location, u16 keep, u16 set) +{ + u16 *parcel =3D location; + + *parcel =3D cpu_to_le16((le16_to_cpu(*parcel) & keep) | set); + return 0; +} + +static int apply_r_riscv_32_rela(struct module *me, void *location, Elf_Ad= dr v) { if (v !=3D (u32)v) { pr_err("%s: value %016llx out of range for 32-bit field\n", me->name, (long long)v); return -EINVAL; } - *location =3D v; + *(u32 *)location =3D v; return 0; } =20 -static int apply_r_riscv_64_rela(struct module *me, u32 *location, Elf_Add= r v) +static int apply_r_riscv_64_rela(struct module *me, void *location, Elf_Ad= dr v) { *(u64 *)location =3D v; return 0; } =20 -static int apply_r_riscv_branch_rela(struct module *me, u32 *location, +static int apply_r_riscv_branch_rela(struct module *me, void *location, Elf_Addr v) { - ptrdiff_t offset =3D (void *)v - (void *)location; + ptrdiff_t offset =3D (void *)v - location; u32 imm12 =3D (offset & 0x1000) << (31 - 12); u32 imm11 =3D (offset & 0x800) >> (11 - 7); u32 imm10_5 =3D (offset & 0x7e0) << (30 - 10); u32 imm4_1 =3D (offset & 0x1e) << (11 - 4); =20 - *location =3D (*location & 0x1fff07f) | imm12 | imm11 | imm10_5 | imm4_1; - return 0; + return riscv_insn_rmw(location, 0x1fff07f, imm12 | imm11 | imm10_5 | imm4= _1); } =20 -static int apply_r_riscv_jal_rela(struct module *me, u32 *location, +static int apply_r_riscv_jal_rela(struct module *me, void *location, Elf_Addr v) { - ptrdiff_t offset =3D (void *)v - (void *)location; + ptrdiff_t offset =3D (void *)v - location; u32 imm20 =3D (offset & 0x100000) << (31 - 20); u32 imm19_12 =3D (offset & 0xff000); u32 imm11 =3D (offset & 0x800) << (20 - 11); u32 imm10_1 =3D (offset & 0x7fe) << (30 - 10); =20 - *location =3D (*location & 0xfff) | imm20 | imm19_12 | imm11 | imm10_1; - return 0; + return riscv_insn_rmw(location, 0xfff, imm20 | imm19_12 | imm11 | imm10_1= ); } =20 -static int apply_r_riscv_rvc_branch_rela(struct module *me, u32 *location, +static int apply_r_riscv_rvc_branch_rela(struct module *me, void *location, Elf_Addr v) { - ptrdiff_t offset =3D (void *)v - (void *)location; + ptrdiff_t offset =3D (void *)v - location; u16 imm8 =3D (offset & 0x100) << (12 - 8); u16 imm7_6 =3D (offset & 0xc0) >> (6 - 5); u16 imm5 =3D (offset & 0x20) >> (5 - 2); u16 imm4_3 =3D (offset & 0x18) << (12 - 5); u16 imm2_1 =3D (offset & 0x6) << (12 - 10); =20 - *(u16 *)location =3D (*(u16 *)location & 0xe383) | - imm8 | imm7_6 | imm5 | imm4_3 | imm2_1; - return 0; + return riscv_insn_rvc_rmw(location, 0xe383, + imm8 | imm7_6 | imm5 | imm4_3 | imm2_1); } =20 -static int apply_r_riscv_rvc_jump_rela(struct module *me, u32 *location, +static int apply_r_riscv_rvc_jump_rela(struct module *me, void *location, Elf_Addr v) { - ptrdiff_t offset =3D (void *)v - (void *)location; + ptrdiff_t offset =3D (void *)v - location; u16 imm11 =3D (offset & 0x800) << (12 - 11); u16 imm10 =3D (offset & 0x400) >> (10 - 8); u16 imm9_8 =3D (offset & 0x300) << (12 - 11); @@ -98,16 +116,14 @@ static int apply_r_riscv_rvc_jump_rela(struct module *= me, u32 *location, u16 imm4 =3D (offset & 0x10) << (12 - 5); u16 imm3_1 =3D (offset & 0xe) << (12 - 10); =20 - *(u16 *)location =3D (*(u16 *)location & 0xe003) | - imm11 | imm10 | imm9_8 | imm7 | imm6 | imm5 | imm4 | imm3_1; - return 0; + return riscv_insn_rvc_rmw(location, 0xe003, + imm11 | imm10 | imm9_8 | imm7 | imm6 | imm5 | imm4 | imm3_1); } =20 -static int apply_r_riscv_pcrel_hi20_rela(struct module *me, u32 *location, +static int apply_r_riscv_pcrel_hi20_rela(struct module *me, void *location, Elf_Addr v) { - ptrdiff_t offset =3D (void *)v - (void *)location; - s32 hi20; + ptrdiff_t offset =3D (void *)v - location; =20 if (!riscv_insn_valid_32bit_offset(offset)) { pr_err( @@ -116,23 +132,20 @@ static int apply_r_riscv_pcrel_hi20_rela(struct modul= e *me, u32 *location, return -EINVAL; } =20 - hi20 =3D (offset + 0x800) & 0xfffff000; - *location =3D (*location & 0xfff) | hi20; - return 0; + return riscv_insn_rmw(location, 0xfff, (offset + 0x800) & 0xfffff000); } =20 -static int apply_r_riscv_pcrel_lo12_i_rela(struct module *me, u32 *locatio= n, +static int apply_r_riscv_pcrel_lo12_i_rela(struct module *me, void *locati= on, Elf_Addr v) { /* * v is the lo12 value to fill. It is calculated before calling this * handler. */ - *location =3D (*location & 0xfffff) | ((v & 0xfff) << 20); - return 0; + return riscv_insn_rmw(location, 0xfffff, (v & 0xfff) << 20); } =20 -static int apply_r_riscv_pcrel_lo12_s_rela(struct module *me, u32 *locatio= n, +static int apply_r_riscv_pcrel_lo12_s_rela(struct module *me, void *locati= on, Elf_Addr v) { /* @@ -142,15 +155,12 @@ static int apply_r_riscv_pcrel_lo12_s_rela(struct mod= ule *me, u32 *location, u32 imm11_5 =3D (v & 0xfe0) << (31 - 11); u32 imm4_0 =3D (v & 0x1f) << (11 - 4); =20 - *location =3D (*location & 0x1fff07f) | imm11_5 | imm4_0; - return 0; + return riscv_insn_rmw(location, 0x1fff07f, imm11_5 | imm4_0); } =20 -static int apply_r_riscv_hi20_rela(struct module *me, u32 *location, +static int apply_r_riscv_hi20_rela(struct module *me, void *location, Elf_Addr v) { - s32 hi20; - if (IS_ENABLED(CONFIG_CMODEL_MEDLOW)) { pr_err( "%s: target %016llx can not be addressed by the 32-bit offset from PC = =3D %p\n", @@ -158,22 +168,20 @@ static int apply_r_riscv_hi20_rela(struct module *me,= u32 *location, return -EINVAL; } =20 - hi20 =3D ((s32)v + 0x800) & 0xfffff000; - *location =3D (*location & 0xfff) | hi20; - return 0; + return riscv_insn_rmw(location, 0xfff, ((s32)v + 0x800) & 0xfffff000); } =20 -static int apply_r_riscv_lo12_i_rela(struct module *me, u32 *location, +static int apply_r_riscv_lo12_i_rela(struct module *me, void *location, Elf_Addr v) { /* Skip medlow checking because of filtering by HI20 already */ s32 hi20 =3D ((s32)v + 0x800) & 0xfffff000; s32 lo12 =3D ((s32)v - hi20); - *location =3D (*location & 0xfffff) | ((lo12 & 0xfff) << 20); - return 0; + + return riscv_insn_rmw(location, 0xfffff, (lo12 & 0xfff) << 20); } =20 -static int apply_r_riscv_lo12_s_rela(struct module *me, u32 *location, +static int apply_r_riscv_lo12_s_rela(struct module *me, void *location, Elf_Addr v) { /* Skip medlow checking because of filtering by HI20 already */ @@ -181,20 +189,18 @@ static int apply_r_riscv_lo12_s_rela(struct module *m= e, u32 *location, s32 lo12 =3D ((s32)v - hi20); u32 imm11_5 =3D (lo12 & 0xfe0) << (31 - 11); u32 imm4_0 =3D (lo12 & 0x1f) << (11 - 4); - *location =3D (*location & 0x1fff07f) | imm11_5 | imm4_0; - return 0; + + return riscv_insn_rmw(location, 0x1fff07f, imm11_5 | imm4_0); } =20 -static int apply_r_riscv_got_hi20_rela(struct module *me, u32 *location, +static int apply_r_riscv_got_hi20_rela(struct module *me, void *location, Elf_Addr v) { - ptrdiff_t offset =3D (void *)v - (void *)location; - s32 hi20; + ptrdiff_t offset =3D (void *)v - location; =20 /* Always emit the got entry */ if (IS_ENABLED(CONFIG_MODULE_SECTIONS)) { - offset =3D module_emit_got_entry(me, v); - offset =3D (void *)offset - (void *)location; + offset =3D (void *)module_emit_got_entry(me, v) - location; } else { pr_err( "%s: can not generate the GOT entry for symbol =3D %016llx from PC =3D= %p\n", @@ -202,22 +208,19 @@ static int apply_r_riscv_got_hi20_rela(struct module = *me, u32 *location, return -EINVAL; } =20 - hi20 =3D (offset + 0x800) & 0xfffff000; - *location =3D (*location & 0xfff) | hi20; - return 0; + return riscv_insn_rmw(location, 0xfff, (offset + 0x800) & 0xfffff000); } =20 -static int apply_r_riscv_call_plt_rela(struct module *me, u32 *location, +static int apply_r_riscv_call_plt_rela(struct module *me, void *location, Elf_Addr v) { - ptrdiff_t offset =3D (void *)v - (void *)location; + ptrdiff_t offset =3D (void *)v - location; u32 hi20, lo12; =20 if (!riscv_insn_valid_32bit_offset(offset)) { /* Only emit the plt entry if offset over 32-bit range */ if (IS_ENABLED(CONFIG_MODULE_SECTIONS)) { - offset =3D module_emit_plt_entry(me, v); - offset =3D (void *)offset - (void *)location; + offset =3D (void *)module_emit_plt_entry(me, v) - location; } else { pr_err( "%s: target %016llx can not be addressed by the 32-bit offset from PC= =3D %p\n", @@ -228,15 +231,14 @@ static int apply_r_riscv_call_plt_rela(struct module = *me, u32 *location, =20 hi20 =3D (offset + 0x800) & 0xfffff000; lo12 =3D (offset - hi20) & 0xfff; - *location =3D (*location & 0xfff) | hi20; - *(location + 1) =3D (*(location + 1) & 0xfffff) | (lo12 << 20); - return 0; + riscv_insn_rmw(location, 0xfff, hi20); + return riscv_insn_rmw(location + 4, 0xfffff, lo12 << 20); } =20 -static int apply_r_riscv_call_rela(struct module *me, u32 *location, +static int apply_r_riscv_call_rela(struct module *me, void *location, Elf_Addr v) { - ptrdiff_t offset =3D (void *)v - (void *)location; + ptrdiff_t offset =3D (void *)v - location; u32 hi20, lo12; =20 if (!riscv_insn_valid_32bit_offset(offset)) { @@ -248,18 +250,17 @@ static int apply_r_riscv_call_rela(struct module *me,= u32 *location, =20 hi20 =3D (offset + 0x800) & 0xfffff000; lo12 =3D (offset - hi20) & 0xfff; - *location =3D (*location & 0xfff) | hi20; - *(location + 1) =3D (*(location + 1) & 0xfffff) | (lo12 << 20); - return 0; + riscv_insn_rmw(location, 0xfff, hi20); + return riscv_insn_rmw(location + 4, 0xfffff, lo12 << 20); } =20 -static int apply_r_riscv_relax_rela(struct module *me, u32 *location, +static int apply_r_riscv_relax_rela(struct module *me, void *location, Elf_Addr v) { return 0; } =20 -static int apply_r_riscv_align_rela(struct module *me, u32 *location, +static int apply_r_riscv_align_rela(struct module *me, void *location, Elf_Addr v) { pr_err( @@ -268,49 +269,49 @@ static int apply_r_riscv_align_rela(struct module *me= , u32 *location, return -EINVAL; } =20 -static int apply_r_riscv_add16_rela(struct module *me, u32 *location, +static int apply_r_riscv_add16_rela(struct module *me, void *location, Elf_Addr v) { *(u16 *)location +=3D (u16)v; return 0; } =20 -static int apply_r_riscv_add32_rela(struct module *me, u32 *location, +static int apply_r_riscv_add32_rela(struct module *me, void *location, Elf_Addr v) { *(u32 *)location +=3D (u32)v; return 0; } =20 -static int apply_r_riscv_add64_rela(struct module *me, u32 *location, +static int apply_r_riscv_add64_rela(struct module *me, void *location, Elf_Addr v) { *(u64 *)location +=3D (u64)v; return 0; } =20 -static int apply_r_riscv_sub16_rela(struct module *me, u32 *location, +static int apply_r_riscv_sub16_rela(struct module *me, void *location, Elf_Addr v) { *(u16 *)location -=3D (u16)v; return 0; } =20 -static int apply_r_riscv_sub32_rela(struct module *me, u32 *location, +static int apply_r_riscv_sub32_rela(struct module *me, void *location, Elf_Addr v) { *(u32 *)location -=3D (u32)v; return 0; } =20 -static int apply_r_riscv_sub64_rela(struct module *me, u32 *location, +static int apply_r_riscv_sub64_rela(struct module *me, void *location, Elf_Addr v) { *(u64 *)location -=3D (u64)v; return 0; } =20 -static int (*reloc_handlers_rela[]) (struct module *me, u32 *location, +static int (*reloc_handlers_rela[]) (struct module *me, void *location, Elf_Addr v) =3D { [R_RISCV_32] =3D apply_r_riscv_32_rela, [R_RISCV_64] =3D apply_r_riscv_64_rela, @@ -342,9 +343,9 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *s= trtab, struct module *me) { Elf_Rela *rel =3D (void *) sechdrs[relsec].sh_addr; - int (*handler)(struct module *me, u32 *location, Elf_Addr v); + int (*handler)(struct module *me, void *location, Elf_Addr v); Elf_Sym *sym; - u32 *location; + void *location; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231018-module_relocations-v5-2-dfee32d4dfc3@rivosinc.com> References: <20231018-module_relocations-v5-0-dfee32d4dfc3@rivosinc.com> In-Reply-To: <20231018-module_relocations-v5-0-dfee32d4dfc3@rivosinc.com> To: linux-riscv@lists.infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Cc: Eric Biederman , Kees Cook , Paul Walmsley , Palmer Dabbelt , Albert Ou , Andreas Schwab , Emil Renner Berthing , Samuel Holland , Charlie Jenkins X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add all final module relocations and add error logs explaining the ones that are not supported. Signed-off-by: Charlie Jenkins --- arch/riscv/include/uapi/asm/elf.h | 5 +- arch/riscv/kernel/module.c | 220 +++++++++++++++++++++++++++++++++-= ---- 2 files changed, 199 insertions(+), 26 deletions(-) diff --git a/arch/riscv/include/uapi/asm/elf.h b/arch/riscv/include/uapi/as= m/elf.h index d696d6610231..11a71b8533d5 100644 --- a/arch/riscv/include/uapi/asm/elf.h +++ b/arch/riscv/include/uapi/asm/elf.h @@ -49,6 +49,7 @@ typedef union __riscv_fp_state elf_fpregset_t; #define R_RISCV_TLS_DTPREL64 9 #define R_RISCV_TLS_TPREL32 10 #define R_RISCV_TLS_TPREL64 11 +#define R_RISCV_IRELATIVE 58 =20 /* Relocation types not used by the dynamic linker */ #define R_RISCV_BRANCH 16 @@ -81,7 +82,6 @@ typedef union __riscv_fp_state elf_fpregset_t; #define R_RISCV_ALIGN 43 #define R_RISCV_RVC_BRANCH 44 #define R_RISCV_RVC_JUMP 45 -#define R_RISCV_LUI 46 #define R_RISCV_GPREL_I 47 #define R_RISCV_GPREL_S 48 #define R_RISCV_TPREL_I 49 @@ -93,6 +93,9 @@ typedef union __riscv_fp_state elf_fpregset_t; #define R_RISCV_SET16 55 #define R_RISCV_SET32 56 #define R_RISCV_32_PCREL 57 +#define R_RISCV_PLT32 59 +#define R_RISCV_SET_ULEB128 60 +#define R_RISCV_SUB_ULEB128 61 =20 =20 #endif /* _UAPI_ASM_RISCV_ELF_H */ diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index a9e94e939cb5..3a3d342c09be 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/module.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -269,6 +270,12 @@ static int apply_r_riscv_align_rela(struct module *me,= void *location, return -EINVAL; } =20 +static int apply_r_riscv_add8_rela(struct module *me, void *location, Elf_= Addr v) +{ + *(u8 *)location +=3D (u8)v; + return 0; +} + static int apply_r_riscv_add16_rela(struct module *me, void *location, Elf_Addr v) { @@ -290,6 +297,12 @@ static int apply_r_riscv_add64_rela(struct module *me,= void *location, return 0; } =20 +static int apply_r_riscv_sub8_rela(struct module *me, void *location, Elf_= Addr v) +{ + *(u8 *)location -=3D (u8)v; + return 0; +} + static int apply_r_riscv_sub16_rela(struct module *me, void *location, Elf_Addr v) { @@ -311,31 +324,162 @@ static int apply_r_riscv_sub64_rela(struct module *m= e, void *location, return 0; } =20 -static int (*reloc_handlers_rela[]) (struct module *me, void *location, - Elf_Addr v) =3D { - [R_RISCV_32] =3D apply_r_riscv_32_rela, - [R_RISCV_64] =3D apply_r_riscv_64_rela, - [R_RISCV_BRANCH] =3D apply_r_riscv_branch_rela, - [R_RISCV_JAL] =3D apply_r_riscv_jal_rela, - [R_RISCV_RVC_BRANCH] =3D apply_r_riscv_rvc_branch_rela, - [R_RISCV_RVC_JUMP] =3D apply_r_riscv_rvc_jump_rela, - [R_RISCV_PCREL_HI20] =3D apply_r_riscv_pcrel_hi20_rela, - [R_RISCV_PCREL_LO12_I] =3D apply_r_riscv_pcrel_lo12_i_rela, - [R_RISCV_PCREL_LO12_S] =3D apply_r_riscv_pcrel_lo12_s_rela, - [R_RISCV_HI20] =3D apply_r_riscv_hi20_rela, - [R_RISCV_LO12_I] =3D apply_r_riscv_lo12_i_rela, - [R_RISCV_LO12_S] =3D apply_r_riscv_lo12_s_rela, - [R_RISCV_GOT_HI20] =3D apply_r_riscv_got_hi20_rela, - [R_RISCV_CALL_PLT] =3D apply_r_riscv_call_plt_rela, - [R_RISCV_CALL] =3D apply_r_riscv_call_rela, - [R_RISCV_RELAX] =3D apply_r_riscv_relax_rela, - [R_RISCV_ALIGN] =3D apply_r_riscv_align_rela, - [R_RISCV_ADD16] =3D apply_r_riscv_add16_rela, - [R_RISCV_ADD32] =3D apply_r_riscv_add32_rela, - [R_RISCV_ADD64] =3D apply_r_riscv_add64_rela, - [R_RISCV_SUB16] =3D apply_r_riscv_sub16_rela, - [R_RISCV_SUB32] =3D apply_r_riscv_sub32_rela, - [R_RISCV_SUB64] =3D apply_r_riscv_sub64_rela, +static int dynamic_linking_not_supported(struct module *me, void *location, + Elf_Addr v) +{ + pr_err("%s: Dynamic linking not supported in kernel modules PC =3D %p\n", + me->name, location); + return -EINVAL; +} + +static int tls_not_supported(struct module *me, void *location, Elf_Addr v) +{ + pr_err("%s: Thread local storage not supported in kernel modules PC =3D %= p\n", + me->name, location); + return -EINVAL; +} + +static int apply_r_riscv_sub6_rela(struct module *me, void *location, Elf_= Addr v) +{ + *(u8 *)location =3D (*(u8 *)location - ((u8)v & 0x3F)) & 0x3F; + return 0; +} + +static int apply_r_riscv_set6_rela(struct module *me, void *location, Elf_= Addr v) +{ + *(u8 *)location =3D ((*(u8 *)location & 0xc0) | ((u8)v & 0x3F)); + return 0; +} + +static int apply_r_riscv_set8_rela(struct module *me, void *location, Elf_= Addr v) +{ + *(u8 *)location =3D (u8)v; + return 0; +} + +static int apply_r_riscv_set16_rela(struct module *me, void *location, + Elf_Addr v) +{ + *(u16 *)location =3D (u16)v; + return 0; +} + +static int apply_r_riscv_set32_rela(struct module *me, void *location, + Elf_Addr v) +{ + *(u32 *)location =3D (u32)v; + return 0; +} + +static int apply_r_riscv_32_pcrel_rela(struct module *me, void *location, + Elf_Addr v) +{ + *(u32 *)location =3D v - (unsigned long)location; + return 0; +} + +static int apply_r_riscv_plt32_rela(struct module *me, void *location, + Elf_Addr v) +{ + ptrdiff_t offset =3D (void *)v - location; + + if (!riscv_insn_valid_32bit_offset(offset)) { + /* Only emit the plt entry if offset over 32-bit range */ + if (IS_ENABLED(CONFIG_MODULE_SECTIONS)) { + offset =3D (void *)module_emit_plt_entry(me, v) - location; + } else { + pr_err("%s: target %016llx can not be addressed by the 32-bit offset fr= om PC =3D %p\n", + me->name, (long long)v, location); + return -EINVAL; + } + } + + *(u32 *)location =3D (u32)offset; + return 0; +} + +static int apply_r_riscv_set_uleb128(struct module *me, void *location, El= f_Addr v) +{ + /* + * Relocation is only performed if R_RISCV_SET_ULEB128 is followed by + * R_RISCV_SUB_ULEB128 so do computation there + */ + return 0; +} + +static int apply_r_riscv_sub_uleb128(struct module *me, void *location, El= f_Addr v) +{ + if (v >=3D 128) { + pr_err("%s: uleb128 must be in [0, 127] (not %ld) at PC =3D %p\n", + me->name, (unsigned long)v, location); + return -EINVAL; + } + + *(u32 *)location =3D (*(u32 *)location & ~((u32)127)) | (v & 127); + return 0; +} + +/* + * Relocations defined in the riscv-elf-psabi-doc. + * This handles static linking only. + */ +static int (*reloc_handlers_rela[])(struct module *me, u32 *location, + Elf_Addr v) =3D { + [R_RISCV_32] =3D apply_r_riscv_32_rela, + [R_RISCV_64] =3D apply_r_riscv_64_rela, + [R_RISCV_RELATIVE] =3D dynamic_linking_not_supported, + [R_RISCV_COPY] =3D dynamic_linking_not_supported, + [R_RISCV_JUMP_SLOT] =3D dynamic_linking_not_supported, + [R_RISCV_TLS_DTPMOD32] =3D dynamic_linking_not_supported, + [R_RISCV_TLS_DTPMOD64] =3D dynamic_linking_not_supported, + [R_RISCV_TLS_DTPREL32] =3D dynamic_linking_not_supported, + [R_RISCV_TLS_DTPREL64] =3D dynamic_linking_not_supported, + [R_RISCV_TLS_TPREL32] =3D dynamic_linking_not_supported, + [R_RISCV_TLS_TPREL64] =3D dynamic_linking_not_supported, + /* 12-15 undefined */ + [R_RISCV_BRANCH] =3D apply_r_riscv_branch_rela, + [R_RISCV_JAL] =3D apply_r_riscv_jal_rela, + [R_RISCV_CALL] =3D apply_r_riscv_call_rela, + [R_RISCV_CALL_PLT] =3D apply_r_riscv_call_plt_rela, + [R_RISCV_GOT_HI20] =3D apply_r_riscv_got_hi20_rela, + [R_RISCV_TLS_GOT_HI20] =3D tls_not_supported, + [R_RISCV_TLS_GD_HI20] =3D tls_not_supported, + [R_RISCV_PCREL_HI20] =3D apply_r_riscv_pcrel_hi20_rela, + [R_RISCV_PCREL_LO12_I] =3D apply_r_riscv_pcrel_lo12_i_rela, + [R_RISCV_PCREL_LO12_S] =3D apply_r_riscv_pcrel_lo12_s_rela, + [R_RISCV_HI20] =3D apply_r_riscv_hi20_rela, + [R_RISCV_LO12_I] =3D apply_r_riscv_lo12_i_rela, + [R_RISCV_LO12_S] =3D apply_r_riscv_lo12_s_rela, + [R_RISCV_TPREL_HI20] =3D tls_not_supported, + [R_RISCV_TPREL_LO12_I] =3D tls_not_supported, + [R_RISCV_TPREL_LO12_S] =3D tls_not_supported, + [R_RISCV_TPREL_ADD] =3D tls_not_supported, + [R_RISCV_ADD8] =3D apply_r_riscv_add8_rela, + [R_RISCV_ADD16] =3D apply_r_riscv_add16_rela, + [R_RISCV_ADD32] =3D apply_r_riscv_add32_rela, + [R_RISCV_ADD64] =3D apply_r_riscv_add64_rela, + [R_RISCV_SUB8] =3D apply_r_riscv_sub8_rela, + [R_RISCV_SUB16] =3D apply_r_riscv_sub16_rela, + [R_RISCV_SUB32] =3D apply_r_riscv_sub32_rela, + [R_RISCV_SUB64] =3D apply_r_riscv_sub64_rela, + /* 41-42 reserved for future standard use */ + [R_RISCV_ALIGN] =3D apply_r_riscv_align_rela, + [R_RISCV_RVC_BRANCH] =3D apply_r_riscv_rvc_branch_rela, + [R_RISCV_RVC_JUMP] =3D apply_r_riscv_rvc_jump_rela, + /* 46-50 reserved for future standard use */ + [R_RISCV_RELAX] =3D apply_r_riscv_relax_rela, + [R_RISCV_SUB6] =3D apply_r_riscv_sub6_rela, + [R_RISCV_SET6] =3D apply_r_riscv_set6_rela, + [R_RISCV_SET8] =3D apply_r_riscv_set8_rela, + [R_RISCV_SET16] =3D apply_r_riscv_set16_rela, + [R_RISCV_SET32] =3D apply_r_riscv_set32_rela, + [R_RISCV_32_PCREL] =3D apply_r_riscv_32_pcrel_rela, + [R_RISCV_IRELATIVE] =3D dynamic_linking_not_supported, + [R_RISCV_PLT32] =3D apply_r_riscv_plt32_rela, + [R_RISCV_SET_ULEB128] =3D apply_r_riscv_set_uleb128, + [R_RISCV_SUB_ULEB128] =3D apply_r_riscv_sub_uleb128, + /* 62-191 reserved for future standard use */ + /* 192-255 nonstandard ABI extensions */ }; =20 int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, @@ -349,6 +493,9 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *s= trtab, unsigned int i, type; Elf_Addr v; int res; + bool uleb128_set_exists =3D false; + u32 *uleb128_set_loc; + unsigned long uleb128_set_sym_val; =20 pr_debug("Applying relocate section %u to %u\n", relsec, sechdrs[relsec].sh_info); @@ -426,6 +573,29 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *= strtab, me->name); return -EINVAL; } + } else if (type =3D=3D R_RISCV_SET_ULEB128) { + if (uleb128_set_exists) { + pr_err("%s: riscv psABI requires the next ULEB128 relocation to come a= fter a R_RISCV_SET_ULEB128 is an R_RISCV_SUB_ULEB128, not another R_RISCV_S= ET_ULEB128.\n", + me->name); + return -EINVAL; + } + uleb128_set_exists =3D true; + uleb128_set_loc =3D location; + uleb128_set_sym_val =3D + ((Elf_Sym *)sechdrs[symindex].sh_addr + + ELF_RISCV_R_SYM(rel[i].r_info)) + ->st_value + + rel[i].r_addend; + } else if (type =3D=3D R_RISCV_SUB_ULEB128) { + if (uleb128_set_exists && uleb128_set_loc =3D=3D location) { + /* Calculate set and subtraction */ + v =3D uleb128_set_sym_val - v; + } else { + pr_err("%s: R_RISCV_SUB_ULEB128 must always be paired with the first R= _RISCV_SET_ULEB128 that comes before it. PC =3D %p\n", + me->name, location); + return -EINVAL; + } + uleb128_set_exists =3D false; } =20 res =3D handler(me, location, v); --=20 2.42.0 From nobody Wed Dec 17 12:55:21 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD27BCDB482 for ; Wed, 18 Oct 2023 22:51:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232229AbjJRWvT (ORCPT ); Wed, 18 Oct 2023 18:51:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42950 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232067AbjJRWvL (ORCPT ); Wed, 18 Oct 2023 18:51:11 -0400 Received: from mail-oo1-xc30.google.com (mail-oo1-xc30.google.com [IPv6:2607:f8b0:4864:20::c30]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0CD47114 for ; Wed, 18 Oct 2023 15:51:09 -0700 (PDT) Received: by mail-oo1-xc30.google.com with SMTP id 006d021491bc7-57b6a7e0deeso4491857eaf.2 for ; Wed, 18 Oct 2023 15:51:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697669468; x=1698274268; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ozAkGUmu/g2vPdjYsuI5geKJqXaONTU37MWQT8rh8Io=; b=B4lQAJsjc2Sl4uH5NsCrkZf7xslIf3rnbAgI+7Y5kskkHl1SgWtJ9QB4lxij8ArfgV IZ4bPp1+pRSHzueONc8A61n5CRKG6F3qUbZoG+vcXx07COkF/0xVGi4URtDPzZ6jbKlL c+UznHUqyqA3R8dEdC2a9PfBuRNML9K1ayeWSFFMv7vGmsuovaD2Q76Y6EWpHwigYNe6 Eh2tPA/0Rcr34OZzS3SHFVS+kDLMW27cxBnbGkJh5Fb0Ac9Hck6TbhGlAsf+3/qpfhs1 gGDJTYkDbrItZdE33qEPDVkGU3UH3pybzftboWpMQUU7yoH0YiBhEJPV2lBne4gpXXWL dhog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697669468; x=1698274268; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ozAkGUmu/g2vPdjYsuI5geKJqXaONTU37MWQT8rh8Io=; b=cjmActUg/qV2k4A80U3KsNjUTFIli1LrY+fuZQlmso5P7IWeeTyUMoVjue9CS2dZ3n nUjlToLuGOc23/CEakUErB/PU1pC4iN8FXKHZMt4jXlBKrBID/ZXiwI/HYbPzkX2qHUA E5LZ3FmBHnrBixz2fQOxVuFPR1Hyy275a0AhbPGTixb3weuOc0ibB8yCHU9EvnwMarcC WnqZd1AfImv+gmAJctNRRkJSkZAvgUjyAR3B76ckjD25h0qyV5xX7KQiQmNEFfBnYOsp DRNBWR+uNgmGyFEI8t6qAmxxvgLgqfWq5hq6XDRoVfC9NymHif/PXfUo04IQK0sGnpEm lRnw== X-Gm-Message-State: AOJu0Yxx6rN9uZvW7BQE4fAScXpK7oTLaHwunCKc64pZ28ukMhjmHJ4+ P1yf1lIk0DJGur0W6aks9yqa/A== X-Google-Smtp-Source: AGHT+IHNA+QzIyRBjLZTBxsb6UeEKgsbDuMnE4kRFrzU3mKQZGgci8IZ+QjZBkEHu6Jx3kRgx05QMg== X-Received: by 2002:a4a:c50c:0:b0:573:3fe0:cdd6 with SMTP id i12-20020a4ac50c000000b005733fe0cdd6mr553181ooq.6.1697669468275; Wed, 18 Oct 2023 15:51:08 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id r195-20020a4a37cc000000b00581e7506f2fsm641134oor.9.2023.10.18.15.51.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 15:51:07 -0700 (PDT) From: Charlie Jenkins Date: Wed, 18 Oct 2023 15:51:03 -0700 Subject: [PATCH v5 3/3] riscv: Add tests for riscv module loading MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231018-module_relocations-v5-3-dfee32d4dfc3@rivosinc.com> References: <20231018-module_relocations-v5-0-dfee32d4dfc3@rivosinc.com> In-Reply-To: <20231018-module_relocations-v5-0-dfee32d4dfc3@rivosinc.com> To: linux-riscv@lists.infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Cc: Eric Biederman , Kees Cook , Paul Walmsley , Palmer Dabbelt , Albert Ou , Andreas Schwab , Emil Renner Berthing , Samuel Holland , Charlie Jenkins X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add test cases for the two main groups of relocations added: SUB and SET, along with uleb128 which is a bit different because SUB and SET are required to happen together. Signed-off-by: Charlie Jenkins --- arch/riscv/Kconfig.debug | 1 + arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/tests/Kconfig.debug | 35 +++++++++ arch/riscv/kernel/tests/Makefile | 1 + arch/riscv/kernel/tests/module_test/Makefile | 15 ++++ .../tests/module_test/test_module_linking_main.c | 85 ++++++++++++++++++= ++++ arch/riscv/kernel/tests/module_test/test_set16.S | 23 ++++++ arch/riscv/kernel/tests/module_test/test_set32.S | 20 +++++ arch/riscv/kernel/tests/module_test/test_set6.S | 23 ++++++ arch/riscv/kernel/tests/module_test/test_set8.S | 23 ++++++ arch/riscv/kernel/tests/module_test/test_sub16.S | 22 ++++++ arch/riscv/kernel/tests/module_test/test_sub32.S | 22 ++++++ arch/riscv/kernel/tests/module_test/test_sub6.S | 22 ++++++ arch/riscv/kernel/tests/module_test/test_sub64.S | 27 +++++++ arch/riscv/kernel/tests/module_test/test_sub8.S | 22 ++++++ arch/riscv/kernel/tests/module_test/test_uleb128.S | 20 +++++ 16 files changed, 362 insertions(+) diff --git a/arch/riscv/Kconfig.debug b/arch/riscv/Kconfig.debug index e69de29bb2d1..eafe17ebf710 100644 --- a/arch/riscv/Kconfig.debug +++ b/arch/riscv/Kconfig.debug @@ -0,0 +1 @@ +source "arch/riscv/kernel/tests/Kconfig.debug" diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 95cf25d48405..bb99657252f4 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -57,6 +57,7 @@ obj-y +=3D stacktrace.o obj-y +=3D cacheinfo.o obj-y +=3D patch.o obj-y +=3D probes/ +obj-y +=3D tests/ obj-$(CONFIG_MMU) +=3D vdso.o vdso/ =20 obj-$(CONFIG_RISCV_M_MODE) +=3D traps_misaligned.o diff --git a/arch/riscv/kernel/tests/Kconfig.debug b/arch/riscv/kernel/test= s/Kconfig.debug new file mode 100644 index 000000000000..5dba64e8e977 --- /dev/null +++ b/arch/riscv/kernel/tests/Kconfig.debug @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0-only +menu "arch/riscv/kernel Testing and Coverage" + +config AS_HAS_ULEB128 + def_bool $(as-instr,.reloc label$(comma) R_RISCV_SET_ULEB128$(comma) 127\= n.reloc label$(comma) R_RISCV_SUB_ULEB128$(comma) 127\nlabel:\n.word 0) + +menuconfig RUNTIME_KERNEL_TESTING_MENU + bool "arch/riscv/kernel runtime Testing" + def_bool y + help + Enable riscv kernel runtime testing. + +if RUNTIME_KERNEL_TESTING_MENU + +config RISCV_MODULE_LINKING_KUNIT + bool "KUnit test riscv module linking at runtime" if !KUNIT_ALL_TES= TS + depends on KUNIT + default KUNIT_ALL_TESTS + help + Enable this option to test riscv module linking at boot. This will + enable a module called "test_module_linking". + + KUnit tests run during boot and output the results to the debug l= og + in TAP format (http://testanything.org/). Only useful for kernel = devs + running the KUnit test harness, and not intended for inclusion in= to a + production build. + + For more information on KUnit and unit tests in general please re= fer + to the KUnit documentation in Documentation/dev-tools/kunit/. + + If unsure, say N. + +endif # RUNTIME_TESTING_MENU + +endmenu # "arch/riscv/kernel runtime Testing" diff --git a/arch/riscv/kernel/tests/Makefile b/arch/riscv/kernel/tests/Mak= efile new file mode 100644 index 000000000000..7d6c76cffe20 --- /dev/null +++ b/arch/riscv/kernel/tests/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_RISCV_MODULE_LINKING_KUNIT) +=3D module_test/ diff --git a/arch/riscv/kernel/tests/module_test/Makefile b/arch/riscv/kern= el/tests/module_test/Makefile new file mode 100644 index 000000000000..d7a6fd8943de --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/Makefile @@ -0,0 +1,15 @@ +obj-m +=3D test_module_linking.o + +test_sub :=3D test_sub6.o test_sub8.o test_sub16.o test_sub32.o test_sub64= .o + +test_set :=3D test_set6.o test_set8.o test_set16.o test_set32.o + +test_module_linking-objs +=3D $(test_sub) + +test_module_linking-objs +=3D $(test_set) + +ifeq ($(CONFIG_AS_HAS_ULEB128),y) +test_module_linking-objs +=3D test_uleb128.o +endif + +test_module_linking-objs +=3D test_module_linking_main.o diff --git a/arch/riscv/kernel/tests/module_test/test_module_linking_main.c= b/arch/riscv/kernel/tests/module_test/test_module_linking_main.c new file mode 100644 index 000000000000..49820352f1df --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_module_linking_main.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Rivos Inc. + */ + +#include +#include +#include +#include + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Test module linking"); + +extern int test_set32(void); +extern int test_set16(void); +extern int test_set8(void); +extern int test_set6(void); +extern long test_sub64(void); +extern int test_sub32(void); +extern int test_sub16(void); +extern int test_sub8(void); +extern int test_sub6(void); + +#ifdef CONFIG_AS_HAS_ULEB128 +extern int test_uleb(void); +#endif + +#define CHECK_EQ(lhs, rhs) KUNIT_ASSERT_EQ(test, lhs, rhs) + +void run_test_set(struct kunit *test); +void run_test_sub(struct kunit *test); +void run_test_uleb(struct kunit *test); + +void run_test_set(struct kunit *test) +{ + int val32 =3D test_set32(); + int val16 =3D test_set16(); + int val8 =3D test_set8(); + int val6 =3D test_set6(); + + CHECK_EQ(val32, 0); + CHECK_EQ(val16, 0); + CHECK_EQ(val8, 0); + CHECK_EQ(val6, 0); +} + +void run_test_sub(struct kunit *test) +{ + int val64 =3D test_sub64(); + int val32 =3D test_sub32(); + int val16 =3D test_sub16(); + int val8 =3D test_sub8(); + int val6 =3D test_sub6(); + + CHECK_EQ(val64, 0); + CHECK_EQ(val32, 0); + CHECK_EQ(val16, 0); + CHECK_EQ(val8, 0); + CHECK_EQ(val6, 0); +} + +#ifdef CONFIG_AS_HAS_ULEB128 +void run_test_uleb(struct kunit *test) +{ + int valuleb =3D test_uleb(); + + CHECK_EQ(valuleb, 0); +} +#endif + +static struct kunit_case __refdata riscv_module_linking_test_cases[] =3D { + KUNIT_CASE(run_test_set), + KUNIT_CASE(run_test_sub), +#ifdef CONFIG_AS_HAS_ULEB128 + KUNIT_CASE(run_test_uleb), +#endif + {} +}; + +static struct kunit_suite riscv_module_linking_test_suite =3D { + .name =3D "riscv_checksum", + .test_cases =3D riscv_module_linking_test_cases, +}; + +kunit_test_suites(&riscv_module_linking_test_suite); diff --git a/arch/riscv/kernel/tests/module_test/test_set16.S b/arch/riscv/= kernel/tests/module_test/test_set16.S new file mode 100644 index 000000000000..2be0e441a12e --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_set16.S @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_set16 +test_set16: + lw a0, set16 + la t0, set16 +#ifdef CONFIG_32BIT + slli t0, t0, 16 + srli t0, t0, 16 +#else + slli t0, t0, 48 + srli t0, t0, 48 +#endif + sub a0, a0, t0 + ret +.data +set16: + .reloc set16, R_RISCV_SET16, set16 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_set32.S b/arch/riscv/= kernel/tests/module_test/test_set32.S new file mode 100644 index 000000000000..de0444537e67 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_set32.S @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_set32 +test_set32: + lw a0, set32 + la t0, set32 +#ifndef CONFIG_32BIT + slli t0, t0, 32 + srli t0, t0, 32 +#endif + sub a0, a0, t0 + ret +.data +set32: + .reloc set32, R_RISCV_SET32, set32 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_set6.S b/arch/riscv/k= ernel/tests/module_test/test_set6.S new file mode 100644 index 000000000000..c39ce4c219eb --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_set6.S @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_set6 +test_set6: + lw a0, set6 + la t0, set6 +#ifdef CONFIG_32BIT + slli t0, t0, 26 + srli t0, t0, 26 +#else + slli t0, t0, 58 + srli t0, t0, 58 +#endif + sub a0, a0, t0 + ret +.data +set6: + .reloc set6, R_RISCV_SET6, set6 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_set8.S b/arch/riscv/k= ernel/tests/module_test/test_set8.S new file mode 100644 index 000000000000..a656173f6f99 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_set8.S @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_set8 +test_set8: + lw a0, set8 + la t0, set8 +#ifdef CONFIG_32BIT + slli t0, t0, 24 + srli t0, t0, 24 +#else + slli t0, t0, 56 + srli t0, t0, 56 +#endif + sub a0, a0, t0 + ret +.data +set8: + .reloc set8, R_RISCV_SET8, set8 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub16.S b/arch/riscv/= kernel/tests/module_test/test_sub16.S new file mode 100644 index 000000000000..c561e155d1db --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub16.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub16 +test_sub16: + lh a0, sub16 + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub16: + .reloc sub16, R_RISCV_ADD16, second + .reloc sub16, R_RISCV_SUB16, first + .half 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub32.S b/arch/riscv/= kernel/tests/module_test/test_sub32.S new file mode 100644 index 000000000000..93232c70cae6 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub32.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub32 +test_sub32: + lw a0, sub32 + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub32: + .reloc sub32, R_RISCV_ADD32, second + .reloc sub32, R_RISCV_SUB32, first + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub6.S b/arch/riscv/k= ernel/tests/module_test/test_sub6.S new file mode 100644 index 000000000000..d9c9526ceb62 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub6.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub6 +test_sub6: + lb a0, sub6 + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub6: + .reloc sub6, R_RISCV_SET6, second + .reloc sub6, R_RISCV_SUB6, first + .byte 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub64.S b/arch/riscv/= kernel/tests/module_test/test_sub64.S new file mode 100644 index 000000000000..6d260e2a5d98 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub64.S @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub64 +test_sub64: +#ifdef CONFIG_32BIT + lw a0, sub64 +#else + ld a0, sub64 +#endif + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub64: + .reloc sub64, R_RISCV_ADD64, second + .reloc sub64, R_RISCV_SUB64, first + .word 0 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub8.S b/arch/riscv/k= ernel/tests/module_test/test_sub8.S new file mode 100644 index 000000000000..af7849115d4d --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub8.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub8 +test_sub8: + lb a0, sub8 + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub8: + .reloc sub8, R_RISCV_ADD8, second + .reloc sub8, R_RISCV_SUB8, first + .byte 0 diff --git a/arch/riscv/kernel/tests/module_test/test_uleb128.S b/arch/risc= v/kernel/tests/module_test/test_uleb128.S new file mode 100644 index 000000000000..db9f301092d0 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_uleb128.S @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_uleb +test_uleb: + ld a0, second + addi a0, a0, -127 + ret +.data +first: + .rept 127 + .byte 0 + .endr +second: + .reloc second, R_RISCV_SET_ULEB128, second + .reloc second, R_RISCV_SUB_ULEB128, first + .dword 0 --=20 2.42.0