From nobody Fri Sep 20 09:36:13 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39E1DCDB474 for ; Tue, 17 Oct 2023 19:06:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343849AbjJQTGA (ORCPT ); Tue, 17 Oct 2023 15:06:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51342 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235009AbjJQTFw (ORCPT ); Tue, 17 Oct 2023 15:05:52 -0400 Received: from mail-ed1-x531.google.com (mail-ed1-x531.google.com [IPv6:2a00:1450:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E339C109 for ; Tue, 17 Oct 2023 12:05:49 -0700 (PDT) Received: by mail-ed1-x531.google.com with SMTP id 4fb4d7f45d1cf-53e08b60febso9379069a12.1 for ; Tue, 17 Oct 2023 12:05:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1697569548; x=1698174348; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=M4DYHyP5rpJlCrGLu/7YVXYPDawqI0/vUMpje/5y6E4=; b=F3Dzh9O5loghM9/63y5qKCEjs50agFE3KNtQITEcATMR6zxbZK2FyBfTkZqKUboLlZ ZlTDjKy9vVG1y3u9sNX7lD0CIEVdP3Nz9nqA/qW1xCEYihg7eJqeSETW7jixk5uwja+M OfEIx+pg4sDYuyKoYol+Xg2tVtIFa70VVvl/nB2dhryg5xpl2YaA1CgmYmFQMaJfzaZd kDZt77hfTWFN/eB+RTZaNyeAPhv4olQgLLGtMsUYr0ex6+zXTaKwyptAfaBDtC4j7mIF y3PAQyIT3ZI1N3XaC6JB6eVcr63t6TU/QYo+4Vh7CGKYVjJOST+4IaDwfHrUnrvD75DP RmPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697569548; x=1698174348; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=M4DYHyP5rpJlCrGLu/7YVXYPDawqI0/vUMpje/5y6E4=; b=sXs5R+VsIjy+pGSz0qu80Vyn3M5LAG8tHtYutXl/egTeuYdLtYQdoDIlasIKrKZpQL Ch08Xcw3dvsUbHIIBvyI1yzN9sUx3kuYNVHr80pTGiRRUlac6xAHpTx1SNwcor4Lqmcy rCO7Gvsw46Yl076Vi/TwvJp0ZH+VQnd5Idwdr8zDF2baddez6jLym/NsVElmUY37pcPM 7hD/GxQH8fGUqBob9mtxCZhmJUSUxZbomUTMdwx1/w3rWThMFgrsZE4k5sEpOpSiFUnS UYTs72jq40j5hnp8TQZsMSA++Nuz9v+ZW2D9cehM4BXQNAuVZk+cOiPsprc5m+o5Pt8B LFjw== X-Gm-Message-State: AOJu0Ywz7MVR60vtseeMieFhppso8d6gfkTikmecajhBB+7yMVxonFvO zAfIGtHVndR252HIFbcblDTghQ== X-Google-Smtp-Source: AGHT+IE1d8gzvI8UJeLw/gO6durUM9+szimEzBZasfn/1pv7K2XCfq9TUaKMIAHdmRwjNmbGs2YMjQ== X-Received: by 2002:a05:6402:5202:b0:53e:f9ef:ca6b with SMTP id s2-20020a056402520200b0053ef9efca6bmr2682060edd.7.1697569547959; Tue, 17 Oct 2023 12:05:47 -0700 (PDT) Received: from ryzen9.fritz.box ([2a01:2a8:8f03:b001:fe65:a70:2777:ab31]) by smtp.gmail.com with ESMTPSA id bq14-20020a056402214e00b00537963f692esm1637990edb.0.2023.10.17.12.05.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 12:05:47 -0700 (PDT) From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= To: daniel.lezcano@linaro.org, angelogioacchino.delregno@collabora.com, rafael@kernel.org, amitk@kernel.org, rui.zhang@intel.com, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, dunlap@infradead.org, e.xingchen@zte.com.cn, p.zabel@pengutronix.de Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, wenst@chromium.org, ames.lo@mediatek.com, rex-bc.chen@mediatek.com, nfraprado@collabora.com, abailon@baylibre.com, amergnat@baylibre.com, khilman@baylibre.com Subject: [PATCH v5 1/5] dt-bindings: thermal: mediatek: Add LVTS thermal controller definition for mt8192 Date: Tue, 17 Oct 2023 21:05:41 +0200 Message-ID: <20231017190545.157282-2-bero@baylibre.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017190545.157282-1-bero@baylibre.com> References: <20231017190545.157282-1-bero@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Balsam CHIHI Add LVTS thermal controller definition for MT8192. Signed-off-by: Balsam CHIHI Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Signed-off-by: Bernhard Rosenkr=C3=A4nzer Reviewed-by: Matthias Brugger Reviewed-by: Alexandre Mergnat --- .../thermal/mediatek,lvts-thermal.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/dt-bindings/thermal/mediatek,lvts-thermal.h b/include/= dt-bindings/thermal/mediatek,lvts-thermal.h index 8fa5a46675c46..5e9eb62174268 100644 --- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h +++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h @@ -26,4 +26,23 @@ #define MT8195_AP_CAM0 15 #define MT8195_AP_CAM1 16 =20 +#define MT8192_MCU_BIG_CPU0 0 +#define MT8192_MCU_BIG_CPU1 1 +#define MT8192_MCU_BIG_CPU2 2 +#define MT8192_MCU_BIG_CPU3 3 +#define MT8192_MCU_LITTLE_CPU0 4 +#define MT8192_MCU_LITTLE_CPU1 5 +#define MT8192_MCU_LITTLE_CPU2 6 +#define MT8192_MCU_LITTLE_CPU3 7 + +#define MT8192_AP_VPU0 8 +#define MT8192_AP_VPU1 9 +#define MT8192_AP_GPU0 10 +#define MT8192_AP_GPU1 11 +#define MT8192_AP_INFRA 12 +#define MT8192_AP_CAM 13 +#define MT8192_AP_MD0 14 +#define MT8192_AP_MD1 15 +#define MT8192_AP_MD2 16 + #endif /* __MEDIATEK_LVTS_DT_H */ --=20 2.42.0 From nobody Fri Sep 20 09:36:13 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9740ACDB485 for ; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Balsam CHIHI Add suspend and resume support to LVTS driver. Signed-off-by: Balsam CHIHI [bero@baylibre.com: suspend/resume in noirq phase] Co-developed-by: Bernhard Rosenkr=C3=A4nzer Signed-off-by: Bernhard Rosenkr=C3=A4nzer Reviewed-by: Matthias Brugger Reviewed-by: Alexandre Mergnat Reviewed-by: AngeloGioacchino Del Regno --- drivers/thermal/mediatek/lvts_thermal.c | 37 +++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/medi= atek/lvts_thermal.c index 877a0e5ac3fd3..c5a03bdf63e9d 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -1254,6 +1254,38 @@ static void lvts_remove(struct platform_device *pdev) lvts_debugfs_exit(lvts_td); } =20 +static int lvts_suspend(struct device *dev) +{ + struct lvts_domain *lvts_td; + int i; + + lvts_td =3D dev_get_drvdata(dev); + + for (i =3D 0; i < lvts_td->num_lvts_ctrl; i++) + lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); + + clk_disable_unprepare(lvts_td->clk); + + return 0; +} + +static int lvts_resume(struct device *dev) +{ + struct lvts_domain *lvts_td; + int i, ret; + + lvts_td =3D dev_get_drvdata(dev); + + ret =3D clk_prepare_enable(lvts_td->clk); + if (ret) + return ret; + + for (i =3D 0; i < lvts_td->num_lvts_ctrl; i++) + lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], true); + + return 0; +} + static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] =3D { { .cal_offset =3D { 0x04, 0x07 }, @@ -1350,12 +1382,17 @@ static const struct of_device_id lvts_of_match[] = =3D { }; MODULE_DEVICE_TABLE(of, lvts_of_match); =20 +static const struct dev_pm_ops lvts_pm_ops =3D { + NOIRQ_SYSTEM_SLEEP_PM_OPS(lvts_suspend, lvts_resume) +}; + static struct platform_driver lvts_driver =3D { .probe =3D lvts_probe, .remove_new =3D lvts_remove, .driver =3D { .name =3D "mtk-lvts-thermal", .of_match_table =3D lvts_of_match, + .pm =3D &lvts_pm_ops, }, }; module_platform_driver(lvts_driver); --=20 2.42.0 From nobody Fri Sep 20 09:36:13 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4AE7C41513 for ; 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Tue, 17 Oct 2023 12:05:50 -0700 (PDT) Received: from ryzen9.fritz.box ([2a01:2a8:8f03:b001:fe65:a70:2777:ab31]) by smtp.gmail.com with ESMTPSA id bq14-20020a056402214e00b00537963f692esm1637990edb.0.2023.10.17.12.05.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 12:05:49 -0700 (PDT) From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= To: daniel.lezcano@linaro.org, angelogioacchino.delregno@collabora.com, rafael@kernel.org, amitk@kernel.org, rui.zhang@intel.com, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, dunlap@infradead.org, e.xingchen@zte.com.cn, p.zabel@pengutronix.de Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, wenst@chromium.org, ames.lo@mediatek.com, rex-bc.chen@mediatek.com, nfraprado@collabora.com, abailon@baylibre.com, amergnat@baylibre.com, khilman@baylibre.com Subject: [PATCH v5 3/5] thermal/drivers/mediatek/lvts_thermal: Add mt8192 support Date: Tue, 17 Oct 2023 21:05:43 +0200 Message-ID: <20231017190545.157282-4-bero@baylibre.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017190545.157282-1-bero@baylibre.com> References: <20231017190545.157282-1-bero@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Balsam CHIHI Add LVTS Driver support for MT8192. Co-developed-by: N=C3=ADcolas F. R. A. Prado Signed-off-by: N=C3=ADcolas F. R. A. Prado Signed-off-by: Balsam CHIHI Reviewed-by: N=C3=ADcolas F. R. A. Prado [bero@baylibre.com: cosmetic changes, rebase] Signed-off-by: Bernhard Rosenkr=C3=A4nzer Reviewed-by: Matthias Brugger Reviewed-by: Alexandre Mergnat Reviewed-by: AngeloGioacchino Del Regno --- drivers/thermal/mediatek/lvts_thermal.c | 95 +++++++++++++++++++++++++ 1 file changed, 95 insertions(+) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/medi= atek/lvts_thermal.c index c5a03bdf63e9d..487401424951d 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -89,6 +89,7 @@ #define LVTS_MSR_READ_TIMEOUT_US 400 #define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2) =20 +#define LVTS_HW_SHUTDOWN_MT8192 105000 #define LVTS_HW_SHUTDOWN_MT8195 105000 =20 #define LVTS_MINIMUM_THRESHOLD 20000 @@ -1286,6 +1287,88 @@ static int lvts_resume(struct device *dev) return 0; } =20 +static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] =3D { + { + .cal_offset =3D { 0x04, 0x08 }, + .lvts_sensor =3D { + { .dt_id =3D MT8192_MCU_BIG_CPU0 }, + { .dt_id =3D MT8192_MCU_BIG_CPU1 } + }, + .num_lvts_sensor =3D 2, + .offset =3D 0x0, + .hw_tshut_temp =3D LVTS_HW_SHUTDOWN_MT8192, + .mode =3D LVTS_MSR_FILTERED_MODE, + }, + { + .cal_offset =3D { 0x0c, 0x10 }, + .lvts_sensor =3D { + { .dt_id =3D MT8192_MCU_BIG_CPU2 }, + { .dt_id =3D MT8192_MCU_BIG_CPU3 } + }, + .num_lvts_sensor =3D 2, + .offset =3D 0x100, + .hw_tshut_temp =3D LVTS_HW_SHUTDOWN_MT8192, + .mode =3D LVTS_MSR_FILTERED_MODE, + }, + { + .cal_offset =3D { 0x14, 0x18, 0x1c, 0x20 }, + .lvts_sensor =3D { + { .dt_id =3D MT8192_MCU_LITTLE_CPU0 }, + { .dt_id =3D MT8192_MCU_LITTLE_CPU1 }, + { .dt_id =3D MT8192_MCU_LITTLE_CPU2 }, + { .dt_id =3D MT8192_MCU_LITTLE_CPU3 } + }, + .num_lvts_sensor =3D 4, + .offset =3D 0x200, + .hw_tshut_temp =3D LVTS_HW_SHUTDOWN_MT8192, + .mode =3D LVTS_MSR_FILTERED_MODE, + } +}; + +static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] =3D { + { + .cal_offset =3D { 0x24, 0x28 }, + .lvts_sensor =3D { + { .dt_id =3D MT8192_AP_VPU0 }, + { .dt_id =3D MT8192_AP_VPU1 } + }, + .num_lvts_sensor =3D 2, + .offset =3D 0x0, + .hw_tshut_temp =3D LVTS_HW_SHUTDOWN_MT8192, + }, + { + .cal_offset =3D { 0x2c, 0x30 }, + .lvts_sensor =3D { + { .dt_id =3D MT8192_AP_GPU0 }, + { .dt_id =3D MT8192_AP_GPU1 } + }, + .num_lvts_sensor =3D 2, + .offset =3D 0x100, + .hw_tshut_temp =3D LVTS_HW_SHUTDOWN_MT8192, + }, + { + .cal_offset =3D { 0x34, 0x38 }, + .lvts_sensor =3D { + { .dt_id =3D MT8192_AP_INFRA }, + { .dt_id =3D MT8192_AP_CAM }, + }, + .num_lvts_sensor =3D 2, + .offset =3D 0x200, + .hw_tshut_temp =3D LVTS_HW_SHUTDOWN_MT8192, + }, + { + .cal_offset =3D { 0x3c, 0x40, 0x44 }, + .lvts_sensor =3D { + { .dt_id =3D MT8192_AP_MD0 }, + { .dt_id =3D MT8192_AP_MD1 }, + { .dt_id =3D MT8192_AP_MD2 } + }, + .num_lvts_sensor =3D 3, + .offset =3D 0x300, + .hw_tshut_temp =3D LVTS_HW_SHUTDOWN_MT8192, + } +}; + static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] =3D { { .cal_offset =3D { 0x04, 0x07 }, @@ -1365,6 +1448,16 @@ static const struct lvts_ctrl_data mt8195_lvts_ap_da= ta_ctrl[] =3D { } }; =20 +static const struct lvts_data mt8192_lvts_mcu_data =3D { + .lvts_ctrl =3D mt8192_lvts_mcu_data_ctrl, + .num_lvts_ctrl =3D ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl), +}; + +static const struct lvts_data mt8192_lvts_ap_data =3D { + .lvts_ctrl =3D mt8192_lvts_ap_data_ctrl, + .num_lvts_ctrl =3D ARRAY_SIZE(mt8192_lvts_ap_data_ctrl), +}; + static const struct lvts_data mt8195_lvts_mcu_data =3D { .lvts_ctrl =3D mt8195_lvts_mcu_data_ctrl, .num_lvts_ctrl =3D ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), @@ -1376,6 +1469,8 @@ static const struct lvts_data mt8195_lvts_ap_data =3D= { }; =20 static const struct of_device_id lvts_of_match[] =3D { + { .compatible =3D "mediatek,mt8192-lvts-mcu", .data =3D &mt8192_lvts_mcu_= data }, + { .compatible =3D "mediatek,mt8192-lvts-ap", .data =3D &mt8192_lvts_ap_da= ta }, { .compatible =3D "mediatek,mt8195-lvts-mcu", .data =3D &mt8195_lvts_mcu_= data }, { .compatible =3D "mediatek,mt8195-lvts-ap", .data =3D &mt8195_lvts_ap_da= ta }, {}, --=20 2.42.0 From nobody Fri Sep 20 09:36:13 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97F2ACDB483 for ; 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Tue, 17 Oct 2023 12:05:51 -0700 (PDT) Received: from ryzen9.fritz.box ([2a01:2a8:8f03:b001:fe65:a70:2777:ab31]) by smtp.gmail.com with ESMTPSA id bq14-20020a056402214e00b00537963f692esm1637990edb.0.2023.10.17.12.05.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 12:05:51 -0700 (PDT) From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= To: daniel.lezcano@linaro.org, angelogioacchino.delregno@collabora.com, rafael@kernel.org, amitk@kernel.org, rui.zhang@intel.com, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, dunlap@infradead.org, e.xingchen@zte.com.cn, p.zabel@pengutronix.de Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, wenst@chromium.org, ames.lo@mediatek.com, rex-bc.chen@mediatek.com, nfraprado@collabora.com, abailon@baylibre.com, amergnat@baylibre.com, khilman@baylibre.com Subject: [PATCH v5 4/5] arm64: dts: mediatek: mt8192: Add thermal nodes and thermal zones Date: Tue, 17 Oct 2023 21:05:44 +0200 Message-ID: <20231017190545.157282-5-bero@baylibre.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017190545.157282-1-bero@baylibre.com> References: <20231017190545.157282-1-bero@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Balsam CHIHI Add thermal nodes and thermal zones for the mt8192. The mt8192 SoC has several hotspots around the CPUs. Specify the targeted temperature threshold to apply the mitigation and define the associated cooling devices. Signed-off-by: Balsam CHIHI Reviewed-by: N=C3=ADcolas F. R. A. Prado [bero@baylibre.com: cosmetic changes, reduce lvts_ap size] Signed-off-by: Bernhard Rosenkr=C3=A4nzer Reviewed-by: Alexandre Mergnat Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 454 +++++++++++++++++++++++ 1 file changed, 454 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 69f4cded5dbbf..238f6eb258323 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -14,6 +14,8 @@ #include #include #include +#include +#include =20 / { compatible =3D "mediatek,mt8192"; @@ -72,6 +74,7 @@ cpu0: cpu@0 { next-level-cache =3D <&l2_0>; performance-domains =3D <&performance 0>; capacity-dmips-mhz =3D <427>; + #cooling-cells =3D <2>; }; =20 cpu1: cpu@100 { @@ -90,6 +93,7 @@ cpu1: cpu@100 { next-level-cache =3D <&l2_0>; performance-domains =3D <&performance 0>; capacity-dmips-mhz =3D <427>; + #cooling-cells =3D <2>; }; =20 cpu2: cpu@200 { @@ -108,6 +112,7 @@ cpu2: cpu@200 { next-level-cache =3D <&l2_0>; performance-domains =3D <&performance 0>; capacity-dmips-mhz =3D <427>; + #cooling-cells =3D <2>; }; =20 cpu3: cpu@300 { @@ -126,6 +131,7 @@ cpu3: cpu@300 { next-level-cache =3D <&l2_0>; performance-domains =3D <&performance 0>; capacity-dmips-mhz =3D <427>; + #cooling-cells =3D <2>; }; =20 cpu4: cpu@400 { @@ -144,6 +150,7 @@ cpu4: cpu@400 { next-level-cache =3D <&l2_1>; performance-domains =3D <&performance 1>; capacity-dmips-mhz =3D <1024>; + #cooling-cells =3D <2>; }; =20 cpu5: cpu@500 { @@ -162,6 +169,7 @@ cpu5: cpu@500 { next-level-cache =3D <&l2_1>; performance-domains =3D <&performance 1>; capacity-dmips-mhz =3D <1024>; + #cooling-cells =3D <2>; }; =20 cpu6: cpu@600 { @@ -180,6 +188,7 @@ cpu6: cpu@600 { next-level-cache =3D <&l2_1>; performance-domains =3D <&performance 1>; capacity-dmips-mhz =3D <1024>; + #cooling-cells =3D <2>; }; =20 cpu7: cpu@700 { @@ -198,6 +207,7 @@ cpu7: cpu@700 { next-level-cache =3D <&l2_1>; performance-domains =3D <&performance 1>; capacity-dmips-mhz =3D <1024>; + #cooling-cells =3D <2>; }; =20 cpu-map { @@ -788,6 +798,17 @@ spi0: spi@1100a000 { status =3D "disabled"; }; =20 + lvts_ap: thermal-sensor@1100b000 { + compatible =3D "mediatek,mt8192-lvts-ap"; + reg =3D <0 0x1100b000 0 0xc00>; + interrupts =3D ; + clocks =3D <&infracfg CLK_INFRA_THERM>; + resets =3D <&infracfg MT8192_INFRA_RST0_THERM_CTRL_SWRST>; + nvmem-cells =3D <&lvts_e_data1>; + nvmem-cell-names =3D "lvts-calib-data-1"; + #thermal-sensor-cells =3D <1>; + }; + pwm0: pwm@1100e000 { compatible =3D "mediatek,mt8183-disp-pwm"; reg =3D <0 0x1100e000 0 0x1000>; @@ -1114,6 +1135,17 @@ nor_flash: spi@11234000 { status =3D "disabled"; }; =20 + lvts_mcu: thermal-sensor@11278000 { + compatible =3D "mediatek,mt8192-lvts-mcu"; + reg =3D <0 0x11278000 0 0x1000>; + interrupts =3D ; + clocks =3D <&infracfg CLK_INFRA_THERM>; + resets =3D <&infracfg MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST>; + nvmem-cells =3D <&lvts_e_data1>; + nvmem-cell-names =3D "lvts-calib-data-1"; + #thermal-sensor-cells =3D <1>; + }; + efuse: efuse@11c10000 { compatible =3D "mediatek,mt8192-efuse", "mediatek,efuse"; reg =3D <0 0x11c10000 0 0x1000>; @@ -1899,4 +1931,426 @@ larb2: larb@1f002000 { power-domains =3D <&spm MT8192_POWER_DOMAIN_MDP>; }; }; + + thermal_zones: thermal-zones { + cpu0-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_mcu MT8192_MCU_LITTLE_CPU0>; + + trips { + cpu0_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu0_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu0_alert>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu1-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_mcu MT8192_MCU_LITTLE_CPU1>; + + trips { + cpu1_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu1_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu1_alert>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu2-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_mcu MT8192_MCU_LITTLE_CPU2>; + + trips { + cpu2_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu2_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu2_alert>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu3-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_mcu MT8192_MCU_LITTLE_CPU3>; + + trips { + cpu3_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu3_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu3_alert>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu4-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_mcu MT8192_MCU_BIG_CPU0>; + + trips { + cpu4_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu4_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu4_alert>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu5-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_mcu MT8192_MCU_BIG_CPU1>; + + trips { + cpu5_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu5_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu5_alert>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu6-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_mcu MT8192_MCU_BIG_CPU2>; + + trips { + cpu6_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu6_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu6_alert>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu7-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_mcu MT8192_MCU_BIG_CPU3>; + + trips { + cpu7_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu7_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu7_alert>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + vpu0-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8192_AP_VPU0>; + + trips { + vpu0_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + vpu0_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + vpu1-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8192_AP_VPU1>; + + trips { + vpu1_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + vpu1_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + gpu0-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8192_AP_GPU0>; + + trips { + gpu0_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + gpu0_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + gpu1-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8192_AP_GPU1>; + + trips { + gpu1_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + gpu1_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + infra-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8192_AP_INFRA>; + + trips { + infra_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + infra_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cam-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8192_AP_CAM>; + + trips { + cam_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cam_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + md0-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8192_AP_MD0>; + + trips { + md0_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + md0_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + md1-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8192_AP_MD1>; + + trips { + md1_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + md1_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + md2-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8192_AP_MD2>; + + trips { + md2_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + md2_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + }; }; --=20 2.42.0 From nobody Fri Sep 20 09:36:13 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E0F4CDB483 for ; Tue, 17 Oct 2023 19:06:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234934AbjJQTGN (ORCPT ); Tue, 17 Oct 2023 15:06:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46992 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344121AbjJQTF4 (ORCPT ); Tue, 17 Oct 2023 15:05:56 -0400 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 55FB6FF for ; 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Tue, 17 Oct 2023 12:05:52 -0700 (PDT) From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= To: daniel.lezcano@linaro.org, angelogioacchino.delregno@collabora.com, rafael@kernel.org, amitk@kernel.org, rui.zhang@intel.com, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, dunlap@infradead.org, e.xingchen@zte.com.cn, p.zabel@pengutronix.de Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, wenst@chromium.org, ames.lo@mediatek.com, rex-bc.chen@mediatek.com, nfraprado@collabora.com, abailon@baylibre.com, amergnat@baylibre.com, khilman@baylibre.com Subject: [PATCH v5 5/5] thermal/drivers/mediatek/lvts_thermal: Update calibration data documentation Date: Tue, 17 Oct 2023 21:05:45 +0200 Message-ID: <20231017190545.157282-6-bero@baylibre.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017190545.157282-1-bero@baylibre.com> References: <20231017190545.157282-1-bero@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Balsam CHIHI Update LVTS calibration data documentation for mt8192 and mt8195. Signed-off-by: Balsam CHIHI Reviewed-by: N=C3=ADcolas F. R. A. Prado [bero@baylibre.com: Fix issues pointed out by N=C3=ADcolas F. R. A. Prado <= nfraprado@collabora.com>] Signed-off-by: Bernhard Rosenkr=C3=A4nzer Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat --- drivers/thermal/mediatek/lvts_thermal.c | 31 +++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/medi= atek/lvts_thermal.c index 487401424951d..15fcf573f5cc5 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -604,7 +604,34 @@ static int lvts_sensor_init(struct device *dev, struct= lvts_ctrl *lvts_ctrl, * The efuse blob values follows the sensor enumeration per thermal * controller. The decoding of the stream is as follow: * - * stream index map for MCU Domain : + * MT8192 : + * Stream index map for MCU Domain mt8192 : + * + * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> + * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 | 0x0A | = 0x0B + * + * <-----sensor#2-----> <-----sensor#3-----> + * 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 | 0x13 + * + * <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-= ----> <-----sensor#7-----> + * 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | = 0x1E | 0x1F | 0x20 | 0x21 | 0x22 | 0x23 + * + * Stream index map for AP Domain mt8192 : + * + * <-----sensor#0-----> <-----sensor#1-----> + * 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A | 0x2B + * + * <-----sensor#2-----> <-----sensor#3-----> + * 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33 + * + * <-----sensor#4-----> <-----sensor#5-----> + * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B + * + * <-----sensor#6-----> <-----sensor#7-----> <-----sensor#8-= ----> + * 0x3C | 0x3D | 0x3E | 0x3F | 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | = 0x46 | 0x47 + * + * MT8195 : + * Stream index map for MCU Domain mt8195 : * * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 @@ -615,7 +642,7 @@ static int lvts_sensor_init(struct device *dev, struct = lvts_ctrl *lvts_ctrl, * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----se= nsor#6-----> <-----sensor#7-----> * 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | = 0x1D | 0x1E | 0x1F | 0x20 | 0x21 * - * stream index map for AP Domain : + * Stream index map for AP Domain mt8195 : * * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1-----> * 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A --=20 2.42.0