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([2a01:e0a:999:a3a0:96:820c:ecf7:a817]) by smtp.gmail.com with ESMTPSA id fj7-20020a05600c0c8700b0040772138bb7sm9873393wmb.2.2023.10.17.06.15.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 06:15:26 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz Subject: [PATCH v2 01/19] riscv: hwprobe: factorize hwprobe ISA extension reporting Date: Tue, 17 Oct 2023 15:14:38 +0200 Message-ID: <20231017131456.2053396-2-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017131456.2053396-1-cleger@rivosinc.com> References: <20231017131456.2053396-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Factorize ISA extension reporting by using a macro rather than copy/pasting extension names. This will allow adding new extensions more easily. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Evan Green --- arch/riscv/kernel/sys_riscv.c | 32 ++++++++++++++++++-------------- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 473159b5f303..e207874e686e 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -145,20 +145,24 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pa= ir, for_each_cpu(cpu, cpus) { struct riscv_isainfo *isainfo =3D &hart_isa[cpu]; =20 - if (riscv_isa_extension_available(isainfo->isa, ZBA)) - pair->value |=3D RISCV_HWPROBE_EXT_ZBA; - else - missing |=3D RISCV_HWPROBE_EXT_ZBA; - - if (riscv_isa_extension_available(isainfo->isa, ZBB)) - pair->value |=3D RISCV_HWPROBE_EXT_ZBB; - else - missing |=3D RISCV_HWPROBE_EXT_ZBB; - - if (riscv_isa_extension_available(isainfo->isa, ZBS)) - pair->value |=3D RISCV_HWPROBE_EXT_ZBS; - else - missing |=3D RISCV_HWPROBE_EXT_ZBS; +#define CHECK_ISA_EXT(__ext) \ + do { \ + if (riscv_isa_extension_available(isainfo->isa, __ext)) \ + pair->value |=3D RISCV_HWPROBE_EXT_##__ext; \ + else \ + missing |=3D RISCV_HWPROBE_EXT_##__ext; \ + } while (false) + + /* + * Only use CHECK_ISA_EXT() for extensions which can be exposed + * to userspace, regardless of the kernel's configuration, as no + * other checks, besides presence in the hart_isa bitmap, are + * made. + */ + CHECK_ISA_EXT(ZBA); + CHECK_ISA_EXT(ZBB); + CHECK_ISA_EXT(ZBS); +#undef CHECK_ISA_EXT } =20 /* Now turn off reporting features if any CPU is missing it. */ --=20 2.42.0 From nobody Thu Jan 1 23:52:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66B36CDB474 for ; Tue, 17 Oct 2023 13:15:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343854AbjJQNPn (ORCPT ); Tue, 17 Oct 2023 09:15:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343592AbjJQNPc (ORCPT ); Tue, 17 Oct 2023 09:15:32 -0400 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 31F2CFB for ; Tue, 17 Oct 2023 06:15:30 -0700 (PDT) Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-40651b22977so10009645e9.1 for ; Tue, 17 Oct 2023 06:15:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697548528; x=1698153328; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Q+qm4/TAsuUsyMqC2dQJYqFkQNRJUQO9ctbV40HqJn4=; b=hQ514CwH0j42gvOkXJfV+YAZbhqW7kjsV9RECUZUP+oI1JkQycrLDGBvFzd5MGy8F9 ecN99295TqslqXvJC4+wacqzfNiUZVD/5Q0sxcL9TeXPgxg+37uxPh6N3XeIda6JNoBp YILa4zkGZwrhOAJrpkn3JW/VIe4Z0MBgw03PsOcQh94UiSVLQk7vPnpFuB7CTCKW/X62 tbq+lASiK7NjIPf4uvm4PmFbKZpIgP1q/up77n3mFeW1lFElM3xpwQtZHq7ABS+aI4Pk HBnyj4k348yRUQKj8JapMOe5keRP9su+pzfkpRp+jSUcQCIpfcaKyBKKf984fb3trUYn uSUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697548528; x=1698153328; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Q+qm4/TAsuUsyMqC2dQJYqFkQNRJUQO9ctbV40HqJn4=; b=aqfS4sPq7xl6JiadM1S1/BGPUiNIEvxP5eiBCVd69LL/95jHM496M2cg+ogIL/lpO2 zNz5TlEmGpXKnVJZRBeDiAEZp46l7EogUR+imPJklK5dei9XCsxutZYLYFdSCl5vJ46m rRxx+IzjeFxbMWpl4yZl6DorPspBIjxG5s3tTEpV/cvSt9nX6rHbJKJgPkL9Q4bnSqD7 0DOT0OLxK9PuG3gQq78jbOgT30W/88nHElOlSAmWjFiDCQEK4mmZhA08vd4f5csNKJfQ AHUL+aOIeHvMoWv2RuJ8A30Vg+JfUbzwNOH3R2ylJPjuKIbjs9aaALQugHEklikYLWAO stpQ== X-Gm-Message-State: AOJu0YyM9JFjjjxoZmgxbUMxhMaB4FvrsA6Q1PXbLL12EBLPTvEVx4Yi idA58AKkGp0UNVKPuBM+Adj2sA== X-Google-Smtp-Source: AGHT+IFwvpP6te3nte1X3kpkcIZvEv7NTNdwIhPdz7lcem9dtQZwsDEgtR+7PS/ddcn3SDkn023Ubg== X-Received: by 2002:a05:600c:210b:b0:405:4721:800 with SMTP id u11-20020a05600c210b00b0040547210800mr1657967wml.1.1697548528573; Tue, 17 Oct 2023 06:15:28 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:96:820c:ecf7:a817]) by smtp.gmail.com with ESMTPSA id fj7-20020a05600c0c8700b0040772138bb7sm9873393wmb.2.2023.10.17.06.15.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 06:15:28 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Conor Dooley Subject: [PATCH v2 02/19] riscv: add ISA extension parsing for scalar crypto Date: Tue, 17 Oct 2023 15:14:39 +0200 Message-ID: <20231017131456.2053396-3-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017131456.2053396-1-cleger@rivosinc.com> References: <20231017131456.2053396-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Evan Green The Scalar Crypto specification defines Zk as a shorthand for the Zkn, Zkr and Zkt extensions. The same follows for both Zkn, Zks and Zbk, which are all shorthands for various other extensions. The detailed breakdown can be found in their dt-binding entries. Since Zkn also implies the Zbkb, Zbkc and Zbkx extensions, simply passing "zk" through a DT should enable all of Zbkb, Zbkc, Zbkx, Zkn, Zkr and Zkt. For example, setting the "riscv,isa" DT property to "rv64imafdc_zk" should generate the following cpuinfo output: "rv64imafdc_zicntr_zicsr_zifencei_zihpm_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_z= kt" riscv_isa_ext_data grows a pair of new members, to permit setting the relevant bits for "bundled" extensions, both while parsing the ISA string and the new dedicated extension properties Co-developed-by: Conor Dooley Signed-off-by: Conor Dooley Signed-off-by: Evan Green Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- arch/riscv/include/asm/hwcap.h | 13 +++++ arch/riscv/kernel/cpufeature.c | 103 ++++++++++++++++++++++++++------- 2 files changed, 96 insertions(+), 20 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index b7b58258f6c7..ab80d822c847 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -58,6 +58,17 @@ #define RISCV_ISA_EXT_ZICSR 40 #define RISCV_ISA_EXT_ZIFENCEI 41 #define RISCV_ISA_EXT_ZIHPM 42 +#define RISCV_ISA_EXT_ZBC 43 +#define RISCV_ISA_EXT_ZBKB 44 +#define RISCV_ISA_EXT_ZBKC 45 +#define RISCV_ISA_EXT_ZBKX 46 +#define RISCV_ISA_EXT_ZKND 47 +#define RISCV_ISA_EXT_ZKNE 48 +#define RISCV_ISA_EXT_ZKNH 49 +#define RISCV_ISA_EXT_ZKR 50 +#define RISCV_ISA_EXT_ZKSED 51 +#define RISCV_ISA_EXT_ZKSH 52 +#define RISCV_ISA_EXT_ZKT 53 =20 #define RISCV_ISA_EXT_MAX 64 =20 @@ -77,6 +88,8 @@ struct riscv_isa_ext_data { const unsigned int id; const char *name; const char *property; + const unsigned int *bundle_ids; + const unsigned int bundle_size; }; =20 extern const struct riscv_isa_ext_data riscv_isa_ext[]; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 1cfbba65d11a..d3682fdfd9f1 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -111,6 +111,39 @@ static bool riscv_isa_extension_check(int id) .id =3D _id, \ } =20 +#define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) { \ + .name =3D #_name, \ + .property =3D #_name, \ + .bundle_ids =3D _bundled_exts, \ + .bundle_size =3D ARRAY_SIZE(_bundled_exts) \ +} + +static const unsigned int riscv_zk_bundled_exts[] =3D { + RISCV_ISA_EXT_ZBKB, + RISCV_ISA_EXT_ZBKC, + RISCV_ISA_EXT_ZBKX, + RISCV_ISA_EXT_ZKND, + RISCV_ISA_EXT_ZKNE, + RISCV_ISA_EXT_ZKR, + RISCV_ISA_EXT_ZKT, +}; + +static const unsigned int riscv_zkn_bundled_exts[] =3D { + RISCV_ISA_EXT_ZBKB, + RISCV_ISA_EXT_ZBKC, + RISCV_ISA_EXT_ZBKX, + RISCV_ISA_EXT_ZKND, + RISCV_ISA_EXT_ZKNE, + RISCV_ISA_EXT_ZKNH, +}; + +static const unsigned int riscv_zks_bundled_exts[] =3D { + RISCV_ISA_EXT_ZBKB, + RISCV_ISA_EXT_ZBKC, + RISCV_ISA_EXT_ZKSED, + RISCV_ISA_EXT_ZKSH +}; + /* * The canonical order of ISA extension names in the ISA string is defined= in * chapter 27 of the unprivileged specification. @@ -173,7 +206,21 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), + __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC), + __RISCV_ISA_EXT_DATA(zbkb, RISCV_ISA_EXT_ZBKB), + __RISCV_ISA_EXT_DATA(zbkc, RISCV_ISA_EXT_ZBKC), + __RISCV_ISA_EXT_DATA(zbkx, RISCV_ISA_EXT_ZBKX), __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), + __RISCV_ISA_EXT_BUNDLE(zk, riscv_zk_bundled_exts), + __RISCV_ISA_EXT_BUNDLE(zkn, riscv_zkn_bundled_exts), + __RISCV_ISA_EXT_DATA(zknd, RISCV_ISA_EXT_ZKND), + __RISCV_ISA_EXT_DATA(zkne, RISCV_ISA_EXT_ZKNE), + __RISCV_ISA_EXT_DATA(zknh, RISCV_ISA_EXT_ZKNH), + __RISCV_ISA_EXT_DATA(zkr, RISCV_ISA_EXT_ZKR), + __RISCV_ISA_EXT_BUNDLE(zks, riscv_zks_bundled_exts), + __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT), + __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED), + __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), @@ -185,6 +232,26 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { =20 const size_t riscv_isa_ext_count =3D ARRAY_SIZE(riscv_isa_ext); =20 +static void __init match_isa_ext(const struct riscv_isa_ext_data *ext, con= st char *name, + const char *name_end, struct riscv_isainfo *isainfo) +{ + if ((name_end - name =3D=3D strlen(ext->name)) && + !strncasecmp(name, ext->name, name_end - name)) { + /* + * If this is a bundle, enable all the ISA extensions that + * comprise the bundle. + */ + if (ext->bundle_size) { + for (int i =3D 0; i < ext->bundle_size; i++) { + if (riscv_isa_extension_check(ext->bundle_ids[i])) + set_bit(ext->bundle_ids[i], isainfo->isa); + } + } else if (riscv_isa_extension_check(ext->id)) { + set_bit(ext->id, isainfo->isa); + } + } +} + static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struc= t riscv_isainfo *isainfo, unsigned long *isa2hwcap, const char *isa) { @@ -316,14 +383,6 @@ static void __init riscv_parse_isa_string(unsigned lon= g *this_hwcap, struct risc if (*isa =3D=3D '_') ++isa; =20 -#define SET_ISA_EXT_MAP(name, bit) \ - do { \ - if ((ext_end - ext =3D=3D strlen(name)) && \ - !strncasecmp(ext, name, strlen(name)) && \ - riscv_isa_extension_check(bit)) \ - set_bit(bit, isainfo->isa); \ - } while (false) \ - if (unlikely(ext_err)) continue; if (!ext_long) { @@ -335,10 +394,8 @@ static void __init riscv_parse_isa_string(unsigned lon= g *this_hwcap, struct risc } } else { for (int i =3D 0; i < riscv_isa_ext_count; i++) - SET_ISA_EXT_MAP(riscv_isa_ext[i].name, - riscv_isa_ext[i].id); + match_isa_ext(&riscv_isa_ext[i], ext, ext_end, isainfo); } -#undef SET_ISA_EXT_MAP } } =20 @@ -437,18 +494,24 @@ static int __init riscv_fill_hwcap_from_ext_list(unsi= gned long *isa2hwcap) } =20 for (int i =3D 0; i < riscv_isa_ext_count; i++) { - if (of_property_match_string(cpu_node, "riscv,isa-extensions", - riscv_isa_ext[i].property) < 0) - continue; + const struct riscv_isa_ext_data ext =3D riscv_isa_ext[i]; =20 - if (!riscv_isa_extension_check(riscv_isa_ext[i].id)) + if (of_property_match_string(cpu_node, "riscv,isa-extensions", + ext.property) < 0) continue; =20 - /* Only single letter extensions get set in hwcap */ - if (strnlen(riscv_isa_ext[i].name, 2) =3D=3D 1) - this_hwcap |=3D isa2hwcap[riscv_isa_ext[i].id]; - - set_bit(riscv_isa_ext[i].id, isainfo->isa); + if (ext.bundle_size) { + for (int j =3D 0; j < ext.bundle_size; j++) { + if (riscv_isa_extension_check(ext.bundle_ids[i])) + set_bit(ext.bundle_ids[j], isainfo->isa); + } + } else if (riscv_isa_extension_check(ext.id)) { + set_bit(ext.id, isainfo->isa); + + /* Only single letter extensions get set in hwcap */ + if (strnlen(riscv_isa_ext[i].name, 2) =3D=3D 1) + this_hwcap |=3D isa2hwcap[riscv_isa_ext[i].id]; + } } =20 of_node_put(cpu_node); --=20 2.42.0 From nobody Thu Jan 1 23:52:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C5F1CDB474 for ; Tue, 17 Oct 2023 13:15:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343867AbjJQNPr (ORCPT ); Tue, 17 Oct 2023 09:15:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57720 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343655AbjJQNPd (ORCPT ); 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([2a01:e0a:999:a3a0:96:820c:ecf7:a817]) by smtp.gmail.com with ESMTPSA id fj7-20020a05600c0c8700b0040772138bb7sm9873393wmb.2.2023.10.17.06.15.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 06:15:29 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz Subject: [PATCH v2 03/19] riscv: hwprobe: add support for scalar crypto ISA extensions Date: Tue, 17 Oct 2023 15:14:40 +0200 Message-ID: <20231017131456.2053396-4-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017131456.2053396-1-cleger@rivosinc.com> References: <20231017131456.2053396-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Export the following scalar crypto extensions through hwprobe: - Zbkb - Zbkc - Zbkx - Zknd - Zkne - Zknh - Zksed - Zksh - Zkt Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- Documentation/riscv/hwprobe.rst | 30 +++++++++++++++++++++++++++ arch/riscv/include/uapi/asm/hwprobe.h | 10 +++++++++ arch/riscv/kernel/sys_riscv.c | 10 +++++++++ 3 files changed, 50 insertions(+) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.= rst index a52996b22f75..968895562d42 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -77,6 +77,36 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as d= efined in version 1.0 of the Bit-Manipulation ISA extensions. =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZBC` The Zbc extension is supported, as de= fined + in version 1.0 of the Scalar Crypto ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZBKB` The Zbkb extension is supported, as + defined in version 1.0 of the Scalar Crypto ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZBKC` The Zbkc extension is supported, as + defined in version 1.0 of the Scalar Crypto ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZBKX` The Zbkx extension is supported, as + defined in version 1.0 of the Scalar Crypto ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKND` The Zknd extension is supported, as + defined in version 1.0 of the Scalar Crypto ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKNE` The Zkne extension is supported, as + defined in version 1.0 of the Scalar Crypto ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKNH` The Zknh extension is supported, as + defined in version 1.0 of the Scalar Crypto ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKSED` The Zksed extension is supported, as + defined in version 1.0 of the Scalar Crypto ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKSH` The Zksh extension is supported, as + defined in version 1.0 of the Scalar Crypto ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKT` The Zkt extension is supported, as de= fined + in version 1.0 of the Scalar Crypto ISA extensions. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 006bfb48343d..89d0e37a01e9 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -29,6 +29,16 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZBA (1 << 3) #define RISCV_HWPROBE_EXT_ZBB (1 << 4) #define RISCV_HWPROBE_EXT_ZBS (1 << 5) +#define RISCV_HWPROBE_EXT_ZBC (1 << 6) +#define RISCV_HWPROBE_EXT_ZBKB (1 << 7) +#define RISCV_HWPROBE_EXT_ZBKC (1 << 8) +#define RISCV_HWPROBE_EXT_ZBKX (1 << 9) +#define RISCV_HWPROBE_EXT_ZKND (1 << 10) +#define RISCV_HWPROBE_EXT_ZKNE (1 << 11) +#define RISCV_HWPROBE_EXT_ZKNH (1 << 12) +#define RISCV_HWPROBE_EXT_ZKSED (1 << 13) +#define RISCV_HWPROBE_EXT_ZKSH (1 << 14) +#define RISCV_HWPROBE_EXT_ZKT (1 << 15) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index e207874e686e..2b50c661da90 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -162,6 +162,16 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pai= r, CHECK_ISA_EXT(ZBA); CHECK_ISA_EXT(ZBB); CHECK_ISA_EXT(ZBS); + CHECK_ISA_EXT(ZBC); + CHECK_ISA_EXT(ZBKB); + CHECK_ISA_EXT(ZBKC); + CHECK_ISA_EXT(ZBKX); + CHECK_ISA_EXT(ZKND); + CHECK_ISA_EXT(ZKNE); + CHECK_ISA_EXT(ZKNH); + CHECK_ISA_EXT(ZKSED); + CHECK_ISA_EXT(ZKSH); + CHECK_ISA_EXT(ZKT); #undef CHECK_ISA_EXT } =20 --=20 2.42.0 From nobody Thu Jan 1 23:52:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85A08CDB474 for ; Tue, 17 Oct 2023 13:15:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234964AbjJQNPu (ORCPT ); Tue, 17 Oct 2023 09:15:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57732 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343802AbjJQNPd (ORCPT ); Tue, 17 Oct 2023 09:15:33 -0400 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE1E5101 for ; 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([2a01:e0a:999:a3a0:96:820c:ecf7:a817]) by smtp.gmail.com with ESMTPSA id fj7-20020a05600c0c8700b0040772138bb7sm9873393wmb.2.2023.10.17.06.15.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 06:15:30 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz Subject: [PATCH v2 04/19] dt-bindings: riscv: add scalar crypto ISA extensions description Date: Tue, 17 Oct 2023 15:14:41 +0200 Message-ID: <20231017131456.2053396-5-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017131456.2053396-1-cleger@rivosinc.com> References: <20231017131456.2053396-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add description for scalar crypto ISA extensions which can now be reported through hwprobe for userspace usage. These extensions are the following: - Zbkb - Zbkc - Zbkx - Zknd - Zkne - Zknh - Zkr - Zksed - Zksh - Zkt Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- .../devicetree/bindings/riscv/extensions.yaml | 77 +++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index cc1f546fdbdc..96ed3d22d3c4 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -184,12 +184,89 @@ properties: multiplication as ratified at commit 6d33919 ("Merge pull requ= est #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitm= anip. =20 + - const: zbkb + description: + The standard Zbkb bitmanip instructions for cryptography as ra= tified + in version 1.0 of RISC-V Cryptography Extensions Volume I + specification. + + - const: zbkc + description: + The standard Zbkc carry-less multiply instructions as ratified + in version 1.0 of RISC-V Cryptography Extensions Volume I + specification. + + - const: zbkx + description: + The standard Zbkx crossbar permutation instructions as ratified + in version 1.0 of RISC-V Cryptography Extensions Volume I + specification. + - const: zbs description: | The standard Zbs bit-manipulation extension for single-bit instructions as ratified at commit 6d33919 ("Merge pull reques= t #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. =20 + - const: zk + description: + The standard Zk Standard Scalar cryptography extension as rati= fied + in version 1.0 of RISC-V Cryptography Extensions Volume I + specification. + + - const: zkn + description: + The standard Zkn NIST algorithm suite extensions as ratified in + version 1.0 of RISC-V Cryptography Extensions Volume I + specification. + + - const: zknd + description: | + The standard Zknd for NIST suite: AES decryption instructions = as + ratified in version 1.0 of RISC-V Cryptography Extensions Volu= me I + specification. + + - const: zkne + description: | + The standard Zkne for NIST suite: AES encryption instructions = as + ratified in version 1.0 of RISC-V Cryptography Extensions Volu= me I + specification. + + - const: zknh + description: | + The standard Zknh for NIST suite: hash function instructions as + ratified in version 1.0 of RISC-V Cryptography Extensions Volu= me I + specification. + + - const: zkr + description: + The standard Zkr entropy source extension as ratified in versi= on + 1.0 of RISC-V Cryptography Extensions Volume I specification. + + - const: zks + description: + The standard Zks ShangMi algorithm suite extensions as ratifie= d in + version 1.0 of RISC-V Cryptography Extensions Volume I + specification. + + - const: zksed + description: | + The standard Zksed for ShangMi suite: SM4 block cipher instruc= tions + as ratified in version 1.0 of RISC-V Cryptography Extensions + Volume I specification. + + - const: zksh + description: | + The standard Zksh for ShangMi suite: SM3 hash function instruc= tions + as ratified in version 1.0 of RISC-V Cryptography Extensions + Volume I specification. + + - const: zkt + description: + The standard Zkt for data independent execution latency as rat= ified + in version 1.0 of RISC-V Cryptography Extensions Volume I + specification. + - const: zicbom description: The standard Zicbom extension for base cache management operat= ions as --=20 2.42.0 From nobody Thu Jan 1 23:52:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A635C41513 for ; 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([2a01:e0a:999:a3a0:96:820c:ecf7:a817]) by smtp.gmail.com with ESMTPSA id fj7-20020a05600c0c8700b0040772138bb7sm9873393wmb.2.2023.10.17.06.15.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 06:15:30 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz Subject: [PATCH v2 05/19] riscv: add ISA extension parsing for vector crypto extensions Date: Tue, 17 Oct 2023 15:14:42 +0200 Message-ID: <20231017131456.2053396-6-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017131456.2053396-1-cleger@rivosinc.com> References: <20231017131456.2053396-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add parsing of some Zv* vector crypto ISA extensions that are mentioned in "RISC-V Cryptography Extensions Volume II" [1]. These ISA extensions are the following: - Zvbb: Vector Basic Bit-manipulation - Zvbc: Vector Carryless Multiplication - Zvkb: Vector Cryptography Bit-manipulation - Zvkg: Vector GCM/GMAC. - Zvkned: NIST Suite: Vector AES Block Cipher - Zvknh[ab]: NIST Suite: Vector SHA-2 Secure Hash - Zvksed: ShangMi Suite: SM4 Block Cipher - Zvksh: ShangMi Suite: SM3 Secure Hash - Zvkn: NIST Algorithm Suite - Zvknc: NIST Algorithm Suite with carryless multiply - Zvkng: NIST Algorithm Suite with GCM. - Zvks: ShangMi Algorithm Suite - Zvksc: ShangMi Algorithm Suite with carryless multiplication - Zvksg: ShangMi Algorithm Suite with GCM. - Zvkt: Vector Data-Independent Execution Latency. Link: https://drive.google.com/file/d/1gb9OLH-DhbCgWp7VwpPOVrrY6f3oSJLL/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- arch/riscv/include/asm/hwcap.h | 10 ++++++ arch/riscv/kernel/cpufeature.c | 56 ++++++++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index ab80d822c847..a2fac23b0cc0 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -69,6 +69,16 @@ #define RISCV_ISA_EXT_ZKSED 51 #define RISCV_ISA_EXT_ZKSH 52 #define RISCV_ISA_EXT_ZKT 53 +#define RISCV_ISA_EXT_ZVBB 54 +#define RISCV_ISA_EXT_ZVBC 55 +#define RISCV_ISA_EXT_ZVKB 56 +#define RISCV_ISA_EXT_ZVKG 57 +#define RISCV_ISA_EXT_ZVKNED 58 +#define RISCV_ISA_EXT_ZVKNHA 59 +#define RISCV_ISA_EXT_ZVKNHB 60 +#define RISCV_ISA_EXT_ZVKSED 61 +#define RISCV_ISA_EXT_ZVKSH 62 +#define RISCV_ISA_EXT_ZVKT 63 =20 #define RISCV_ISA_EXT_MAX 64 =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index d3682fdfd9f1..8cf0b8b442ae 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -144,6 +144,46 @@ static const unsigned int riscv_zks_bundled_exts[] =3D= { RISCV_ISA_EXT_ZKSH }; =20 +#define RISCV_ISA_EXT_ZVKN \ + RISCV_ISA_EXT_ZVKNED, \ + RISCV_ISA_EXT_ZVKNHB, \ + RISCV_ISA_EXT_ZVKB, \ + RISCV_ISA_EXT_ZVKT + +static const unsigned int riscv_zvkn_bundled_exts[] =3D { + RISCV_ISA_EXT_ZVKN +}; + +static const unsigned int riscv_zvknc_bundled_exts[] =3D { + RISCV_ISA_EXT_ZVKN, + RISCV_ISA_EXT_ZVBC, +}; + +static const unsigned int riscv_zvkng_bundled_exts[] =3D { + RISCV_ISA_EXT_ZVKN, + RISCV_ISA_EXT_ZVKG, +}; + +#define RISCV_ISA_EXT_ZVKS \ + RISCV_ISA_EXT_ZVKSED, \ + RISCV_ISA_EXT_ZVKSH, \ + RISCV_ISA_EXT_ZVKB, \ + RISCV_ISA_EXT_ZVKT + +static const unsigned int riscv_zvks_bundled_exts[] =3D { + RISCV_ISA_EXT_ZVKS +}; + +static const unsigned int riscv_zvksc_bundled_exts[] =3D { + RISCV_ISA_EXT_ZVKS, + RISCV_ISA_EXT_ZVBC, +}; + +static const unsigned int riscv_zvksg_bundled_exts[] =3D { + RISCV_ISA_EXT_ZVKS, + RISCV_ISA_EXT_ZVKG, +}; + /* * The canonical order of ISA extension names in the ISA string is defined= in * chapter 27 of the unprivileged specification. @@ -221,6 +261,22 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT), __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED), __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH), + __RISCV_ISA_EXT_DATA(zvbb, RISCV_ISA_EXT_ZVBB), + __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC), + __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB), + __RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG), + __RISCV_ISA_EXT_BUNDLE(zvkn, riscv_zvkn_bundled_exts), + __RISCV_ISA_EXT_BUNDLE(zvknc, riscv_zvknc_bundled_exts), + __RISCV_ISA_EXT_DATA(zvkned, RISCV_ISA_EXT_ZVKNED), + __RISCV_ISA_EXT_BUNDLE(zvkng, riscv_zvkng_bundled_exts), + __RISCV_ISA_EXT_DATA(zvknha, RISCV_ISA_EXT_ZVKNHA), + __RISCV_ISA_EXT_DATA(zvknhb, RISCV_ISA_EXT_ZVKNHB), + __RISCV_ISA_EXT_BUNDLE(zvks, riscv_zvks_bundled_exts), + __RISCV_ISA_EXT_BUNDLE(zvksc, riscv_zvksc_bundled_exts), + __RISCV_ISA_EXT_DATA(zvksed, RISCV_ISA_EXT_ZVKSED), + __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH), + __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts), + __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), --=20 2.42.0 From nobody Thu Jan 1 23:52:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A225CDB482 for ; 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([2a01:e0a:999:a3a0:96:820c:ecf7:a817]) by smtp.gmail.com with ESMTPSA id fj7-20020a05600c0c8700b0040772138bb7sm9873393wmb.2.2023.10.17.06.15.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 06:15:31 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz Subject: [PATCH v2 06/19] riscv: hwprobe: export vector crypto ISA extensions Date: Tue, 17 Oct 2023 15:14:43 +0200 Message-ID: <20231017131456.2053396-7-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017131456.2053396-1-cleger@rivosinc.com> References: <20231017131456.2053396-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Export Zv* vector crypto ISA extensions that were added in "RISC-V Cryptography Extensions Volume II" specification[1] through hwprobe. This adds support for the following instructions: - Zvbb: Vector Basic Bit-manipulation - Zvbc: Vector Carryless Multiplication - Zvkb: Vector Cryptography Bit-manipulation - Zvkg: Vector GCM/GMAC. - Zvkned: NIST Suite: Vector AES Block Cipher - Zvknh[ab]: NIST Suite: Vector SHA-2 Secure Hash - Zvksed: ShangMi Suite: SM4 Block Cipher - Zvksh: ShangMi Suite: SM3 Secure Hash - Zvknc: NIST Algorithm Suite with carryless multiply - Zvkng: NIST Algorithm Suite with GCM. - Zvksc: ShangMi Algorithm Suite with carryless multiplication - Zvksg: ShangMi Algorithm Suite with GCM. - Zvkt: Vector Data-Independent Execution Latency. Zvkn and Zvks are ommited since they are a superset of other extensions. Link: https://drive.google.com/file/d/1gb9OLH-DhbCgWp7VwpPOVrrY6f3oSJLL/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Evan Green --- Documentation/riscv/hwprobe.rst | 30 +++++++++++++++++++++++++++ arch/riscv/include/uapi/asm/hwprobe.h | 10 +++++++++ arch/riscv/kernel/sys_riscv.c | 13 ++++++++++++ 3 files changed, 53 insertions(+) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.= rst index 968895562d42..8681fb601500 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -107,6 +107,36 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZKT` The Zkt extension is supported, as de= fined in version 1.0 of the Scalar Crypto ISA extensions. =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZVBB`: The Zvbb extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVBC`: The Zvbc extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKB`: The Zvkb extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKG`: The Zvkg extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKNED`: The Zvkned extension is supported= as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKNHA`: The Zvknha extension is supported= as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKNHB`: The Zvknhb extension is supported= as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKSED`: The Zvksed extension is supported= as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKSH`: The Zvksh extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvkt extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 89d0e37a01e9..2529cee323db 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -39,6 +39,16 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZKSED (1 << 13) #define RISCV_HWPROBE_EXT_ZKSH (1 << 14) #define RISCV_HWPROBE_EXT_ZKT (1 << 15) +#define RISCV_HWPROBE_EXT_ZVBB (1 << 16) +#define RISCV_HWPROBE_EXT_ZVBC (1 << 17) +#define RISCV_HWPROBE_EXT_ZVKB (1 << 18) +#define RISCV_HWPROBE_EXT_ZVKG (1 << 19) +#define RISCV_HWPROBE_EXT_ZVKNED (1 << 20) +#define RISCV_HWPROBE_EXT_ZVKNHA (1 << 21) +#define RISCV_HWPROBE_EXT_ZVKNHB (1 << 22) +#define RISCV_HWPROBE_EXT_ZVKSED (1 << 23) +#define RISCV_HWPROBE_EXT_ZVKSH (1 << 24) +#define RISCV_HWPROBE_EXT_ZVKT (1 << 25) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 2b50c661da90..25d35800809f 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -172,6 +172,19 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pai= r, CHECK_ISA_EXT(ZKSED); CHECK_ISA_EXT(ZKSH); CHECK_ISA_EXT(ZKT); + + if (has_vector()) { + CHECK_ISA_EXT(ZVBB); + CHECK_ISA_EXT(ZVBC); + CHECK_ISA_EXT(ZVKB); + CHECK_ISA_EXT(ZVKG); + CHECK_ISA_EXT(ZVKNED); + CHECK_ISA_EXT(ZVKNHA); + CHECK_ISA_EXT(ZVKNHB); + CHECK_ISA_EXT(ZVKSED); + CHECK_ISA_EXT(ZVKSH); + CHECK_ISA_EXT(ZVKT); + } #undef CHECK_ISA_EXT } =20 --=20 2.42.0 From nobody Thu Jan 1 23:52:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9505CCDB482 for ; Tue, 17 Oct 2023 13:16:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343898AbjJQNQD (ORCPT ); Tue, 17 Oct 2023 09:16:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55660 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343832AbjJQNPh (ORCPT ); Tue, 17 Oct 2023 09:15:37 -0400 Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B4FC7106 for ; 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([2a01:e0a:999:a3a0:96:820c:ecf7:a817]) by smtp.gmail.com with ESMTPSA id fj7-20020a05600c0c8700b0040772138bb7sm9873393wmb.2.2023.10.17.06.15.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 06:15:32 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Conor Dooley Subject: [PATCH v2 07/19] dt-bindings: riscv: add vector crypto ISA extensions description Date: Tue, 17 Oct 2023 15:14:44 +0200 Message-ID: <20231017131456.2053396-8-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017131456.2053396-1-cleger@rivosinc.com> References: <20231017131456.2053396-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add Zv* vector crypto extensions that were added in "RISC-V Cryptography Extensions Volume II" specificationi[1]: - Zvbb: Vector Basic Bit-manipulation - Zvbc: Vector Carryless Multiplication - Zvkb: Vector Cryptography Bit-manipulation - Zvkg: Vector GCM/GMAC. - Zvkned: NIST Suite: Vector AES Block Cipher - Zvknh[ab]: NIST Suite: Vector SHA-2 Secure Hash - Zvksed: ShangMi Suite: SM4 Block Cipher - Zvksh: ShangMi Suite: SM3 Secure Hash - Zvkn: NIST Algorithm Suite - Zvknc: NIST Algorithm Suite with carryless multiply - Zvkng: NIST Algorithm Suite with GCM. - Zvks: ShangMi Algorithm Suite - Zvksc: ShangMi Algorithm Suite with carryless multiplication - Zvksg: ShangMi Algorithm Suite with GCM. - Zvkt: Vector Data-Independent Execution Latency. Link: https://drive.google.com/file/d/1gb9OLH-DhbCgWp7VwpPOVrrY6f3oSJLL/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Acked-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 96ed3d22d3c4..93beb9872900 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -323,5 +323,101 @@ properties: in commit 2e5236 ("Ztso is now ratified.") of the riscv-isa-manual. =20 + - const: zvbb + description: + The standard Zvbb extension for vectored basic bit-manipulation + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvbc + description: + The standard Zvbc extension for vectored carryless multiplicat= ion + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvkb + description: + The standard Zvkb extension for vector cryptography bit-manipu= lation + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvkg + description: + The standard Zvkg extension for vector GCM/GMAC instructions, = as + ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.a= doc") + of riscv-crypto. + + - const: zvkn + description: + The standard Zvkn extension for NIST algorithm suite instructi= ons, as + ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.a= doc") + of riscv-crypto. + + - const: zvknc + description: + The standard Zvknc extension for NIST algorithm suite with car= ryless + multiply instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvkned + description: + The standard Zvkned extension for Vector AES block cipher + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvkng + description: + The standard Zvkng extension for NIST algorithm suite with GCM + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvknha + description: | + The standard Zvknha extension for NIST suite: vector SHA-2 sec= ure, + hash (SHA-256 only) instructions, as ratified in commit + 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-cryp= to. + + - const: zvknhb + description: | + The standard Zvknhb extension for NIST suite: vector SHA-2 sec= ure, + hash (SHA-256 and SHA-512) instructions, as ratified in commit + 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-cryp= to. + + - const: zvks + description: + The standard Zvks extension for ShangMi algorithm suite + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvksc + description: + The standard Zvksc extension for ShangMi algorithm suite with + carryless multiplication instructions, as ratified in commit 5= 6ed795 + ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvksed + description: | + The standard Zvksed extension for ShangMi suite: SM4 block cip= her + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvksh + description: | + The standard Zvksh extension for ShangMi suite: SM3 secure hash + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvksg + description: + The standard Zvksg extension for ShangMi algorithm suite with = GCM + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvkt + description: + The standard Zvkt extension for vector data-independent execut= ion + latency, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + additionalProperties: true ... --=20 2.42.0 From nobody Thu Jan 1 23:52:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0905CC46CA1 for ; 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([2a01:e0a:999:a3a0:96:820c:ecf7:a817]) by smtp.gmail.com with ESMTPSA id fj7-20020a05600c0c8700b0040772138bb7sm9873393wmb.2.2023.10.17.06.15.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 06:15:33 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz Subject: [PATCH v2 08/19] riscv: add ISA extension parsing for Zfh/Zfhmin Date: Tue, 17 Oct 2023 15:14:45 +0200 Message-ID: <20231017131456.2053396-9-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017131456.2053396-1-cleger@rivosinc.com> References: <20231017131456.2053396-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add parsing for Zvfh/Zfhmin ISA extensions[1]. Link: https://drive.google.com/file/d/1z3tQQLm5ALsAD77PM0l0CHnapxWCeVzP/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Evan Green --- arch/riscv/include/asm/hwcap.h | 4 +++- arch/riscv/kernel/cpufeature.c | 2 ++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index a2fac23b0cc0..bead05cb0df2 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -79,8 +79,10 @@ #define RISCV_ISA_EXT_ZVKSED 61 #define RISCV_ISA_EXT_ZVKSH 62 #define RISCV_ISA_EXT_ZVKT 63 +#define RISCV_ISA_EXT_ZFH 64 +#define RISCV_ISA_EXT_ZFHMIN 65 =20 -#define RISCV_ISA_EXT_MAX 64 +#define RISCV_ISA_EXT_MAX 128 =20 #ifdef CONFIG_RISCV_M_MODE #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 8cf0b8b442ae..68914b5e2df9 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -244,6 +244,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI), __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), + __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), + __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN), __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC), --=20 2.42.0 From nobody Thu Jan 1 23:52:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 109CACDB482 for ; Tue, 17 Oct 2023 13:16:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343847AbjJQNQK (ORCPT ); Tue, 17 Oct 2023 09:16:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55672 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343833AbjJQNPi (ORCPT ); Tue, 17 Oct 2023 09:15:38 -0400 Received: from mail-lj1-x232.google.com (mail-lj1-x232.google.com [IPv6:2a00:1450:4864:20::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 07173107 for ; Tue, 17 Oct 2023 06:15:37 -0700 (PDT) Received: by mail-lj1-x232.google.com with SMTP id 38308e7fff4ca-2c51774da07so6837751fa.1 for ; Tue, 17 Oct 2023 06:15:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697548535; x=1698153335; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3obtZPNOKP8LH+KjJEwDeimcpj3eT+9Cd34xi+FsYNw=; b=u5ZkaH2bN/ItQa1WQ4P8FXFoAITbBqWQIulaDtndjIOMQShIKOLFu0FcM5qBO4URTj g6Hgaft8g3okguJy/haY3vpj9LeNY9cUe5ROcpiHEMhIJ2f2p1B+v8nIhR/VPf/Rczsz v3hv9mTEPBnqcgI28wW7uPsKwRzocHA96gFk3/P3RuzUdigvu6Wela8JUb3RuXODoKL9 jxVuPaSXuUK9f3bOWw5dnn5zNpMgbTGtPRiWXf8dbKJ826OI6fjJ7fQODs3sq8x7k4TE dCjV9z97j7r5xI/W016egpc/UpHKYDQA864Cd03cGZ+Oa/4p45TX69HOOkdbYVKSet5t iD1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697548535; x=1698153335; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3obtZPNOKP8LH+KjJEwDeimcpj3eT+9Cd34xi+FsYNw=; b=qPLLFSYPCrMbiqLaONWMIJVY7/lZbk31TRmDK8Nsp9pbTGI3xb4W6LEwdWj37oyYSf YDDWz6A/NDMAZl79BL69OagVCaUHE4d8JlA/yvaxCLy0cCo29em0ecFOhNW6WKPrMF+w 3FWrbtawtwr7l0DQG0I11cIlpgV3P9MT2dpXazpUsvht3SXBAJFYA1lyiGNNTI4lJg9v TivUhcp3EjwYyajMrgO4CXRYfw2Mw4f8SeV9mEXoTNZkn/DSbbnPYp4ITxEL8ccz8t55 HCO0ktmCJ/J3UFxRCzsrvQYkGBjJgCr0QEQs+k9iSPy1nY8qSRcLRAJJ/qlr5Rtn2Mwl c/5Q== X-Gm-Message-State: AOJu0Yyzj28zTGaBFWrmbHYA7hjGmPEdrfxa6c11rAaeSidMtrVMO/7W 7KiJ4/TM/HDKmcO1y+544wlNxKae8PsnMSHUD97Kyw== X-Google-Smtp-Source: AGHT+IF341BXCev0oxtaNbakkAnO4ZAxajhUcsSm+LPtv73PBIJRAamKmYX/PlGez1RMG9nLGmAzPA== X-Received: by 2002:a05:651c:c8c:b0:2bf:b0d3:20f9 with SMTP id bz12-20020a05651c0c8c00b002bfb0d320f9mr1924875ljb.5.1697548535010; Tue, 17 Oct 2023 06:15:35 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:96:820c:ecf7:a817]) by smtp.gmail.com with ESMTPSA id fj7-20020a05600c0c8700b0040772138bb7sm9873393wmb.2.2023.10.17.06.15.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 06:15:34 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz Subject: [PATCH v2 09/19] riscv: hwprobe: export Zfh/Zfhmin ISA extensions Date: Tue, 17 Oct 2023 15:14:46 +0200 Message-ID: <20231017131456.2053396-10-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017131456.2053396-1-cleger@rivosinc.com> References: <20231017131456.2053396-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Export Zfh/Zfhmin ISA extensions[1] through hwprobe only if FPU support is available. Link: https://drive.google.com/file/d/1z3tQQLm5ALsAD77PM0l0CHnapxWCeVzP/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Evan Green --- Documentation/riscv/hwprobe.rst | 6 ++++++ arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ arch/riscv/kernel/sys_riscv.c | 5 +++++ 3 files changed, 13 insertions(+) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.= rst index 8681fb601500..35aedfff5049 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -137,6 +137,12 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvkt extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZFH`: The Zfh extension version 1.0 is sup= ported + as defined in the RISC-V ISA manual. + + * :c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 = is + supported as defined in the RISC-V ISA manual. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 2529cee323db..390805c49674 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -49,6 +49,8 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZVKSED (1 << 23) #define RISCV_HWPROBE_EXT_ZVKSH (1 << 24) #define RISCV_HWPROBE_EXT_ZVKT (1 << 25) +#define RISCV_HWPROBE_EXT_ZFH (1 << 26) +#define RISCV_HWPROBE_EXT_ZFHMIN (1 << 27) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 25d35800809f..4cca8b982a7a 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -185,6 +185,11 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pai= r, CHECK_ISA_EXT(ZVKSH); CHECK_ISA_EXT(ZVKT); } + + if (has_fpu()) { + CHECK_ISA_EXT(ZFH); + CHECK_ISA_EXT(ZFHMIN); + } #undef CHECK_ISA_EXT } =20 --=20 2.42.0 From nobody Thu Jan 1 23:52:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1791CDB474 for ; Tue, 17 Oct 2023 13:16:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343957AbjJQNQP (ORCPT ); Tue, 17 Oct 2023 09:16:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55710 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343838AbjJQNPk (ORCPT ); Tue, 17 Oct 2023 09:15:40 -0400 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F1C4610B for ; Tue, 17 Oct 2023 06:15:37 -0700 (PDT) Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-406aaccb41dso18299575e9.0 for ; Tue, 17 Oct 2023 06:15:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697548536; x=1698153336; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JWnPq2gaUY6Bw+QhkV+/+BvTRtvqF4BIiAlwEf1vKGM=; b=dOZ25igJytRqCFx+02/whVtQZ+4db7VtNy56yNr34omCyC19Q7ftnT4nBNG+8l+itS 8e/1GQY1tywkRBVigwGY5IePkvht4uLyon03ZukrXArgZs8kZr/WWdj8mKtwTC6jXkXd wuZIgliOrwijtHFozT5lFKMxO/NfMToDq9oltwCNE+jVPlFMhfotBcIikfEkKr9pNr+S P4XuHnqfRVUAuOXxC8IgFp3YAS9lApiqyoAFM0gDDtELf5p5q7Hvjpo24ODKXC9nIDDp DWfNV/qgoQ2IPgbszDgyBqEQuRgIA8tm46ALVuRycaqgeG3sY4r8lpzRiFgUzFMfAv2T dryg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697548536; x=1698153336; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JWnPq2gaUY6Bw+QhkV+/+BvTRtvqF4BIiAlwEf1vKGM=; b=Oyp4vew9wcrRvAqmEUcu0nCbAlGC5ea3vYUVaflSynTymVedqkAQ+JsPmhCZ3mx4CX u01KQoBUCxLV1vktCxrh6IcOZEKcY1QE+OqtryixCMgh6iEV2wNugp8Hu2coUKG/zspH mXKRUBnGSo+cL/nzo3u0Rsdr4Os0cANntL/j1MNzV0AYpKnvZx3DxkwELZYmb2pgDiR6 k6pfE5tznt1M6l7dakSr/ehj2ayeeSMkz188ImIrbK4KVA9wcY7r6b3Y1lwF1MLWjvdN HG8ZUnP0ctktBt21Z/4eUjv6NuWXihu03dnufRQWcojW+5IWZqoE8w7BrSs8Cw0htRoN EUZQ== X-Gm-Message-State: AOJu0YxTI3fJg6n8hu20IpOVX/ojn6+OUmYquqJLfEGLyHOlKGiFNkOe Al8bg+evGf91MN2AKRalqq58uQ== X-Google-Smtp-Source: AGHT+IEySb+/Q17ICv3l76yF8jJjBFEiH3hFuZYYjFi7wwKXT2ljs/AM5fR+ARSo4sgAbdGf5BuQog== X-Received: by 2002:a05:600c:1d9b:b0:408:3836:525f with SMTP id p27-20020a05600c1d9b00b004083836525fmr251193wms.1.1697548536185; Tue, 17 Oct 2023 06:15:36 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:96:820c:ecf7:a817]) by smtp.gmail.com with ESMTPSA id fj7-20020a05600c0c8700b0040772138bb7sm9873393wmb.2.2023.10.17.06.15.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 06:15:35 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Conor Dooley Subject: [PATCH v2 10/19] dt-bindings: riscv: add Zfh[min] ISA extensions description Date: Tue, 17 Oct 2023 15:14:47 +0200 Message-ID: <20231017131456.2053396-11-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017131456.2053396-1-cleger@rivosinc.com> References: <20231017131456.2053396-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add description of Zfh[min] ISA extensions[1] which can now be reported through hwprobe for userspace usage. Link: https://drive.google.com/file/d/1z3tQQLm5ALsAD77PM0l0CHnapxWCeVzP/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Acked-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 93beb9872900..b0a0d1bdf369 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -208,6 +208,19 @@ properties: instructions as ratified at commit 6d33919 ("Merge pull reques= t #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. =20 + - const: zfh + description: + The standard Zfh extension for 16-bit half-precision binary + floating-point instructions, as ratified in commit 64074bc ("U= pdate + version numbers for Zfh/Zfinx") of riscv-isa-manual. + + - const: zfhmin + description: + The standard Zfhmin extension which provides minimal support f= or + 16-bit half-precision binary floating-point instructions, as r= atified + in commit 64074bc ("Update version numbers for Zfh/Zfinx") of + riscv-isa-manual. + - const: zk description: The standard Zk Standard Scalar cryptography extension as rati= fied --=20 2.42.0 From nobody Thu Jan 1 23:52:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1FE5ACDB482 for ; Tue, 17 Oct 2023 13:16:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343962AbjJQNQR (ORCPT ); Tue, 17 Oct 2023 09:16:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55786 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343856AbjJQNPn (ORCPT ); Tue, 17 Oct 2023 09:15:43 -0400 Received: from mail-lj1-x230.google.com (mail-lj1-x230.google.com [IPv6:2a00:1450:4864:20::230]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F7E3F7 for ; Tue, 17 Oct 2023 06:15:39 -0700 (PDT) Received: by mail-lj1-x230.google.com with SMTP id 38308e7fff4ca-2c504a51a18so12430551fa.1 for ; Tue, 17 Oct 2023 06:15:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697548538; x=1698153338; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XveLx1BmE1GvU06WU0o1GpTCvis6fOoE2R2208YLJcc=; b=EviRm+5Q+1FbwvWL5F6/kvhGQNmfrI1A/MaocosEettqksG4vfmDk77kLysmPeX8f/ fLfIqg1mIpt09P1nZJfAgcz7g4SEAet/0YHZ8/niL/RAPhbrOLW87X88Hwd/o6Q5o2vT uEM/IfPe3yXvCPt/zXsSf+l0uIpAoXd1IMYvB5V3xpEVvXfvYJyIs3wuCyArriPnZi7M uj1N5SWEgPNeINCU/5efh6a7/LwI31f7nKClMR7Rnq61+jRHRJCDXkLniC+F5AFZUh+0 gZX/ZylPy1ouWUMKfK/rvuWWZS9WUt4HZgVD/wQFXjvb5ScBU0topvc5O8g2JUlyYGY7 RmLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697548538; x=1698153338; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XveLx1BmE1GvU06WU0o1GpTCvis6fOoE2R2208YLJcc=; b=NReyPxL9l7/6qLPTjwdBevf3P8pOJrYiCttnulzk1V2P3cxlb9SYQGsXPSERRCPyGM WuCj+tqQBxyP9XNvdHHyfYH/M3RXsqwAzOEl8lbPm0lZRZlCEVF4CSAXeaJl6oI0AwqJ +tf4r8EY9RJyN+4jQRDmLPf7w5r0YB5Y1HugRlJx0FzQtF+vJ/5pZFiomcCSwDjDt5gf JWeY4dVuSjPJD7/JbuuhG4/rMFOufG86CwN5B7OHfFOk0u7rObupzj2z6WRjsLusfBgs oq5iZM4kZ/G/CIAfAabPJLJr8n9px+UDXMJF6G4WK8KDAZ9tkP4MP3CUA2+ruoT8MZ0N IsKg== X-Gm-Message-State: AOJu0YygMVSWe3Gs12No4BcmUB6o1U4/JXi5688wC2l/GOWqfYcBvhKT VzXZKQ59TYT6xgpf+OLf8XhMKA== X-Google-Smtp-Source: AGHT+IF7LXN/FgZqOq/N2FVm/bEsUOoHif69CbGwt+OOKA9MLmQwAsroiCAxGTIPT5U1tiT7cTKbGw== X-Received: by 2002:a2e:9b49:0:b0:2c0:1959:fe59 with SMTP id o9-20020a2e9b49000000b002c01959fe59mr1644747ljj.3.1697548537405; Tue, 17 Oct 2023 06:15:37 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:96:820c:ecf7:a817]) by smtp.gmail.com with ESMTPSA id fj7-20020a05600c0c8700b0040772138bb7sm9873393wmb.2.2023.10.17.06.15.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 06:15:37 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz Subject: [PATCH v2 11/19] riscv: add ISA extension parsing for Zihintntl Date: Tue, 17 Oct 2023 15:14:48 +0200 Message-ID: <20231017131456.2053396-12-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017131456.2053396-1-cleger@rivosinc.com> References: <20231017131456.2053396-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add parsing for Zihintntl ISA extension[1] that was ratified in commit 0dc91f5 ("Zihintntl is ratified") of riscv-isa-manual[2]. Link: https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/vie= w [1] Link: https://github.com/riscv/riscv-isa-manual/commit/0dc91f505e6d [2] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Evan Green --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index bead05cb0df2..a9aea62b6c6f 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -81,6 +81,7 @@ #define RISCV_ISA_EXT_ZVKT 63 #define RISCV_ISA_EXT_ZFH 64 #define RISCV_ISA_EXT_ZFHMIN 65 +#define RISCV_ISA_EXT_ZIHINTNTL 66 =20 #define RISCV_ISA_EXT_MAX 128 =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 68914b5e2df9..0a74b2cdcacf 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -242,6 +242,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI), + __RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL), __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), --=20 2.42.0 From nobody Thu Jan 1 23:52:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85F44CDB474 for ; Tue, 17 Oct 2023 13:16:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343901AbjJQNQU (ORCPT ); Tue, 17 Oct 2023 09:16:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55732 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343861AbjJQNPn (ORCPT ); Tue, 17 Oct 2023 09:15:43 -0400 Received: from mail-lj1-x22c.google.com (mail-lj1-x22c.google.com [IPv6:2a00:1450:4864:20::22c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 46DFE112 for ; Tue, 17 Oct 2023 06:15:41 -0700 (PDT) Received: by mail-lj1-x22c.google.com with SMTP id 38308e7fff4ca-2c506d1798eso10177971fa.0 for ; Tue, 17 Oct 2023 06:15:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697548539; x=1698153339; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=T1rHWB6wPm7iXDYEGbhbD+aT0XqxKs0nvsJfpQIGqGo=; b=jkN1Ogm7S6sQdClJBzy0QES9thVqUxfXiF9F2SYGnmanBU5tfPG36FJg87aAKWukLe 5wypRc07Igqnye9M3t62M/ZsFIl5QU/PBpVHshXKdMoMwznzg3m6FkqCWlAwVGyJYOgV m9z0vwpYu1U94jVUN8FcJRvHPqe9TOpTGDFFb4eLcw41eOw3WHbl6Y0WK+/7e3n139Zk 7Zr54o1ds4x11TzFOy4OeFn50kKQsmZZzSCscD6/ra9L9H2+x80Huqzcx6gIS2l4PS0v dY79f0SevdFzRBrpvdznCEyLORMkf+DQWnag4MT1fb/MTOYjuj1yt63O+7UzHMEHl4Ls PnkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697548539; x=1698153339; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T1rHWB6wPm7iXDYEGbhbD+aT0XqxKs0nvsJfpQIGqGo=; b=GChwovtWFh5o+dY0VxkaJJuBOf1xbvWzN+75z9oDRTHHX3vEAiykfwa2oabw5FwVzk byUz9EtnMOSWeKTIbCd3t5uqJygp46KdLzuNq3OZhScoFI5RCR3jo81gpcaa6FwA2REU kNMxBBQrCGxcaJA+ApY+cJ62m/mQM+Qr3dGxvT2D71vC8O4ognmkCajkalykY0+1nbqM GKxqvlhyC1GJKKtm25QoVxaf/L7K2+1/tRNS/Udzs85t/ucKWmoWbhcUd7DhqWlAG9oj ybyj4Bh51qms8EsuheWTG5qfT4A4T97oPRJwBUdzNbhh5485XMHqSTJBo8L7gDpnE3SM H9tA== X-Gm-Message-State: AOJu0YwOgbTE1gdg84XxN4mzUHP4Ozil8eMXK6uptGLbXHps3BJGr5Id fKoM/ykFsmCVaNfUkVZ6vXW8+A== X-Google-Smtp-Source: AGHT+IE8o+inTRSVUnhN0nXkjkUhZnyVP1Kvn8PbG9YD2TzCATvewF2se7oUMFMIdsxNUL5t0bXQaA== X-Received: by 2002:a2e:9b4b:0:b0:2b9:e10b:a511 with SMTP id o11-20020a2e9b4b000000b002b9e10ba511mr1660431ljj.0.1697548538766; Tue, 17 Oct 2023 06:15:38 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:96:820c:ecf7:a817]) by smtp.gmail.com with ESMTPSA id fj7-20020a05600c0c8700b0040772138bb7sm9873393wmb.2.2023.10.17.06.15.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 06:15:37 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz Subject: [PATCH v2 12/19] riscv: hwprobe: export Zhintntl ISA extension Date: Tue, 17 Oct 2023 15:14:49 +0200 Message-ID: <20231017131456.2053396-13-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017131456.2053396-1-cleger@rivosinc.com> References: <20231017131456.2053396-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Export Zihintntl extension[1] through hwprobe. Link: https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Evan Green --- Documentation/riscv/hwprobe.rst | 3 +++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_riscv.c | 1 + 3 files changed, 5 insertions(+) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.= rst index 35aedfff5049..9c909e0d5316 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -143,6 +143,9 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 = is supported as defined in the RISC-V ISA manual. =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension versio= n 1.0 + is supported as defined in the RISC-V ISA manual. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 390805c49674..dc4eaa978ad1 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -51,6 +51,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZVKT (1 << 25) #define RISCV_HWPROBE_EXT_ZFH (1 << 26) #define RISCV_HWPROBE_EXT_ZFHMIN (1 << 27) +#define RISCV_HWPROBE_EXT_ZIHINTNTL (1 << 28) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 4cca8b982a7a..84daaf6ed4a1 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -172,6 +172,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, CHECK_ISA_EXT(ZKSED); CHECK_ISA_EXT(ZKSH); CHECK_ISA_EXT(ZKT); + CHECK_ISA_EXT(ZIHINTNTL); =20 if (has_vector()) { CHECK_ISA_EXT(ZVBB); --=20 2.42.0 From nobody Thu Jan 1 23:52:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54901CDB474 for ; Tue, 17 Oct 2023 13:16:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343875AbjJQNQ0 (ORCPT ); Tue, 17 Oct 2023 09:16:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55818 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343863AbjJQNPo (ORCPT ); Tue, 17 Oct 2023 09:15:44 -0400 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 72F84102 for ; Tue, 17 Oct 2023 06:15:41 -0700 (PDT) Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-406532c49dcso17776645e9.0 for ; Tue, 17 Oct 2023 06:15:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697548540; x=1698153340; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BcwMvdrQT7dDiQfvq5mk8auJjq+yKDjdUlNI6K4rk90=; b=xa8kyVmxIMdgaf2ZwDbPGSzStRaubmGVqg+N2Ez+3aBJMLX9F1s7NeyquRbLn1WvHa JVOkzFUCAbAHJwaMRdSWl3HM7wN5vHYLAaw+hX6yKoGleqbEDt13vFcV23C1Y4sMBYuY BbfhmHkLSFl6y+Yy9KA+kP1IYca6qY4EP/labyUaUQ5nfPFUv4e+YCcGM02O+eNAFQ22 aY5PSQn/2OxN14Tpp/8Z9EdVFAah7ebH7FpPTq04QmpWHZ1Sr3DT2K0xmeOTBT531OjL iTIDz/4HMQgceSwbTvNYwOhLZxRdk1fphcMrNkabml6cak/CJAcR8be9oovZSkg/JqG8 vnCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697548540; x=1698153340; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BcwMvdrQT7dDiQfvq5mk8auJjq+yKDjdUlNI6K4rk90=; b=J7RkGDe8B1E3MxAJgIOffJVU+ByG/RngsM+Vo91k18rBtYbN/S1xDE849sdxZg0ByD ds8iWOzHsdcxx8wUGwhcA01fqoiaeEznl6AJgCAOxA7Hhye3hBZBwfR+/7cW0yCtKtU9 e00AZGfPTr6ugNVL598IqwhRq/QwqJT4uvmanVyidcHPbEBnZf/a8udlbGYgjrlvHiJe EKsYJ0wzzV33ZW32IKWF5XXzSoK8kU2PYDQzkXG8AEQyKdQwPXn3PqnLeusCUCe22KG0 VADVLWEzKrmC65o8x06yvrWk/DRmFtnE90pFbADpwY6U/tUhedfsGC2JwbUpwM/VHVZl 9Jxg== X-Gm-Message-State: AOJu0YxEn3dZoC11Y3jRFjiI5Kfa7uJU+SUEpa6ni4kk6VzM1qkpsOgY a7u73iXaIxzKQmMNvqGDrlEfcA== X-Google-Smtp-Source: AGHT+IHVBUlyPGQBU14EXa9PZ6UFLb59Nwth5umwYgIAc2moUAd+hl54lbf8HW53OTtnTpusU2Ppyg== X-Received: by 2002:a05:600c:150c:b0:405:38d1:621 with SMTP id b12-20020a05600c150c00b0040538d10621mr1641826wmg.3.1697548539594; Tue, 17 Oct 2023 06:15:39 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:96:820c:ecf7:a817]) by smtp.gmail.com with ESMTPSA id fj7-20020a05600c0c8700b0040772138bb7sm9873393wmb.2.2023.10.17.06.15.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 06:15:39 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Conor Dooley Subject: [PATCH v2 13/19] dt-bindings: riscv: add Zihintntl ISA extension description Date: Tue, 17 Oct 2023 15:14:50 +0200 Message-ID: <20231017131456.2053396-14-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017131456.2053396-1-cleger@rivosinc.com> References: <20231017131456.2053396-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add description for Zihintntl ISA extension[1] which can now be reported through hwprobe for userspace usage. Link: https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Acked-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index b0a0d1bdf369..eb4c77b319fb 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -324,6 +324,12 @@ properties: The standard Zihintpause extension for pause hints, as ratifie= d in commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-ma= nual. =20 + - const: zihintntl + description: + The standard Zihintntl extension for non-temporal locality hin= ts, as + ratified in commit 0dc91f5 ("Zihintntl is ratified") of the + riscv-isa-manual. + - const: zihpm description: The standard Zihpm extension for hardware performance counters= , as --=20 2.42.0 From nobody Thu Jan 1 23:52:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98573CDB474 for ; Tue, 17 Oct 2023 13:16:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343972AbjJQNQY (ORCPT ); Tue, 17 Oct 2023 09:16:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343864AbjJQNPo (ORCPT ); Tue, 17 Oct 2023 09:15:44 -0400 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6798211B for ; Tue, 17 Oct 2023 06:15:42 -0700 (PDT) Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-4053e6e8ca7so18306305e9.1 for ; Tue, 17 Oct 2023 06:15:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697548541; x=1698153341; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1HAW94BWBN5i9ceq6FqY8wdNnvu4aG0cSFSkPmGNLOw=; b=L1oyLJWZhrk/cE3FkrHFuJhb2oHjFDDui8MA9/Vulh75w3b1tR2iGxG4jwsnS2LfK9 V6qqbnQ+l+H3i6nDZDtzcVtH7AYmF1zTQkg4kCJR2+gSGVpDHG4x/74Ju7AmoaiTaFfd Yw6sNfvxbKpV2yz4olFOLyAfvRwqHE4LAaRDICvSCh+UkOXKz1obUPdmVsT+GROeuVPt eI7WIRJf35X574I1JnFPbj9dInfJWHIuevO43OQohKU5jBKT+u0uGgiArSjPDTW1heDq C53njOksvltnuR22SRVTqoyA10YOqL1suFrQRCf7GgFUBgI+H3Cyk00DCLnjyinK8VyY l7PQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697548541; x=1698153341; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1HAW94BWBN5i9ceq6FqY8wdNnvu4aG0cSFSkPmGNLOw=; b=ol4k6Ft0DUTbHiPoy1zIzUeGoutSnf8Wr4nGaTebQWGyO2MGWqGCA0IodkdrV3+lEu GpJc2jv1H7s4Z2Df1FeGsc105Tvy7XU4XaLePXJyFX7W8bLJ+P5ABRA3UY91WBGMzL2z YqaLyH7ETgkdBSW5n01NcdQ8WXKKtHty0VHZgb5kZ0x2fKSAAlqVU/agBuKBX4k+2Ftw BOeU2FmXuZOdp8wq42JfwxUe4wN0erydkUzxCapj4tj+vFuPAn1JkrkT4p9hFOyTISar Q9Rb2+vDSdSY5VRqAN3RrxfAnl/nq7yWNUaWPD5qw4oJl7ht8XS73lGI0bj6Qs35cAO/ K7Jw== X-Gm-Message-State: AOJu0Yw961tiWXAbWWd8mN9Hh7ZrberVwI2ItOBOa+JMJxqeayTZxSHH tUhNsNicPrQ7UXjYf/FSjijHGA== X-Google-Smtp-Source: AGHT+IGbBB2bpP6DKx5jv6ntXm18AdT9vWp/ruxSD4Q9u2qImyTRJFK6ZXveoHMW47E7zhir096qKw== X-Received: by 2002:a05:600c:2145:b0:406:513d:738f with SMTP id v5-20020a05600c214500b00406513d738fmr1640603wml.2.1697548540446; Tue, 17 Oct 2023 06:15:40 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:96:820c:ecf7:a817]) by smtp.gmail.com with ESMTPSA id fj7-20020a05600c0c8700b0040772138bb7sm9873393wmb.2.2023.10.17.06.15.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 06:15:40 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz Subject: [PATCH v2 14/19] riscv: add ISA extension parsing for Zvfh[min] Date: Tue, 17 Oct 2023 15:14:51 +0200 Message-ID: <20231017131456.2053396-15-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017131456.2053396-1-cleger@rivosinc.com> References: <20231017131456.2053396-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add parsing for Zvfh[min] ISA extension[1] which were ratified in june 2023 around commit e2ccd0548d6c ("Remove draft warnings from Zvfh[min]") in riscv-v-spec[2]. Link: https://drive.google.com/file/d/1_Yt60HGAf1r1hx7JnsIptw0sqkBd9BQ8/vie= w [1] Link: https://github.com/riscv/riscv-v-spec/commits/e2ccd0548d6c [2] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Evan Green --- arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/kernel/cpufeature.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index a9aea62b6c6f..d9fb782f198d 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -82,6 +82,8 @@ #define RISCV_ISA_EXT_ZFH 64 #define RISCV_ISA_EXT_ZFHMIN 65 #define RISCV_ISA_EXT_ZIHINTNTL 66 +#define RISCV_ISA_EXT_ZVFH 67 +#define RISCV_ISA_EXT_ZVFHMIN 68 =20 #define RISCV_ISA_EXT_MAX 128 =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 0a74b2cdcacf..c70885f5014b 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -266,6 +266,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH), __RISCV_ISA_EXT_DATA(zvbb, RISCV_ISA_EXT_ZVBB), __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC), + __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH), + __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN), __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB), __RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG), __RISCV_ISA_EXT_BUNDLE(zvkn, riscv_zvkn_bundled_exts), --=20 2.42.0 From nobody Thu Jan 1 23:52:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A8ABCDB474 for ; Tue, 17 Oct 2023 13:16:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343925AbjJQNQd (ORCPT ); Tue, 17 Oct 2023 09:16:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55802 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234968AbjJQNPw (ORCPT ); Tue, 17 Oct 2023 09:15:52 -0400 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DC726ED for ; Tue, 17 Oct 2023 06:15:44 -0700 (PDT) Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-407acb21f27so736095e9.0 for ; Tue, 17 Oct 2023 06:15:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697548542; x=1698153342; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=U2m+45j3rbdaE2NY5Ol9kX9V97sFwlFvtbz4uSqqCuM=; b=ComVT4RglsIdNqywtVJS5Xicunw98kWgC3QgQOl67r8wz5l50QaQQNivyIux9OSGPJ ptUs/R6spZLljlX3hZHi9ySrk2d1FQR210DUIfEtPjJwaUbvZ/hwDJxsEWns6F/eP9t4 0R/XkGHdTjj4n363g45uerHPqTYxYQJlOpVSQyTkiaqBAUEl2wAl+k9JpCj3Km+OpJxN 0fzRRYwxhv0PITyl0MzHm1ijLr1PGVx+G8B43Xg0Kk/BMw3glkC9OIT+11tC34SoSQfb K2KXkJmOc6wdX0df4EL8VCT3XyNF6caMIExbzQr3ullS2KN5Ge/CqHJsVFRHvnhodwFZ OTew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697548542; x=1698153342; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=U2m+45j3rbdaE2NY5Ol9kX9V97sFwlFvtbz4uSqqCuM=; b=RMjChhsZ4Qpv2r7tclC5HDjklFVQrCQThNM1g7f/6Fii4vG6TFbNttC/+OqmQuZcMf g+ONRp/mJWNWdmXG8BJYcUqUaG99NupM6in2YjA7ooE6v8hu9O8gqZINgxv0YTmZ9Csx Ngv/W/dSBQRijs30m/kfTbfQnpK4P7Y7vo6n67EuN/9ywjtVFk0+vCUHonGq9mCyqQE4 6qS17G9UbzY7Q2fRrJ+y7MXKP2pT70uJXcLhrMgAFWglkbQze4uu5IMzz6GhQL/GlQAq zRFL9UPYIw1evYT0L5sjNaqC/jC4MMpDdjP7w0jfxTSTVy0CkDKYk0Ui/Rdc8Mz2ACfX +hxA== X-Gm-Message-State: AOJu0YwFIZp3fBv1RX2vfV4Q00LCzVcFKP6gKS9+n7J+CiLwaihm1hud Vtrx9Aqv34PhKqFuIo7Vf+A8fQ== X-Google-Smtp-Source: AGHT+IGl5sTERYXS8gZHY5M+sSNt7WnBezruA/vUWy9wkpbAVX1cnbpzCqcAtWiC4jzRoXD25NnTVg== X-Received: by 2002:a05:600c:929:b0:405:39bb:38a8 with SMTP id m41-20020a05600c092900b0040539bb38a8mr1653730wmp.2.1697548541300; Tue, 17 Oct 2023 06:15:41 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:96:820c:ecf7:a817]) by smtp.gmail.com with ESMTPSA id fj7-20020a05600c0c8700b0040772138bb7sm9873393wmb.2.2023.10.17.06.15.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 06:15:40 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz Subject: [PATCH v2 15/19] riscv: hwprobe: export Zvfh[min] ISA extensions Date: Tue, 17 Oct 2023 15:14:52 +0200 Message-ID: <20231017131456.2053396-16-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017131456.2053396-1-cleger@rivosinc.com> References: <20231017131456.2053396-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Export Zvfh[min] ISA extension[1] through hwprobe. Link: https://drive.google.com/file/d/1_Yt60HGAf1r1hx7JnsIptw0sqkBd9BQ8/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Evan Green --- Documentation/riscv/hwprobe.rst | 8 ++++++++ arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ arch/riscv/kernel/sys_riscv.c | 2 ++ 3 files changed, 12 insertions(+) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.= rst index 9c909e0d5316..782ac26cb92a 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -146,6 +146,14 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension versio= n 1.0 is supported as defined in the RISC-V ISA manual. =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZVFH`: The Zvfh extension is supported as + defined in the RISC-V Vector manual starting from commit e2ccd0548d= 6c + ("Remove draft warnings from Zvfh[min]"). + + * :c:macro:`RISCV_HWPROBE_EXT_ZVFHMIN`: The Zvfhmin extension is support= ed as + defined in the RISC-V Vector manual starting from commit e2ccd0548d= 6c + ("Remove draft warnings from Zvfh[min]"). + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index dc4eaa978ad1..79407010952a 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -52,6 +52,8 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZFH (1 << 26) #define RISCV_HWPROBE_EXT_ZFHMIN (1 << 27) #define RISCV_HWPROBE_EXT_ZIHINTNTL (1 << 28) +#define RISCV_HWPROBE_EXT_ZVFH (1 << 29) +#define RISCV_HWPROBE_EXT_ZVFHMIN (1 << 30) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 84daaf6ed4a1..8d6edd721627 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -185,6 +185,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, CHECK_ISA_EXT(ZVKSED); CHECK_ISA_EXT(ZVKSH); CHECK_ISA_EXT(ZVKT); + CHECK_ISA_EXT(ZVFH); + CHECK_ISA_EXT(ZVFHMIN); } =20 if (has_fpu()) { --=20 2.42.0 From nobody Thu Jan 1 23:52:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72E3ECDB474 for ; Tue, 17 Oct 2023 13:16:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343536AbjJQNQa (ORCPT ); Tue, 17 Oct 2023 09:16:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58130 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343874AbjJQNPw (ORCPT ); Tue, 17 Oct 2023 09:15:52 -0400 Received: from mail-lj1-x22b.google.com (mail-lj1-x22b.google.com [IPv6:2a00:1450:4864:20::22b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D0756EA for ; Tue, 17 Oct 2023 06:15:44 -0700 (PDT) Received: by mail-lj1-x22b.google.com with SMTP id 38308e7fff4ca-2c52289e900so3532211fa.0 for ; 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([2a01:e0a:999:a3a0:96:820c:ecf7:a817]) by smtp.gmail.com with ESMTPSA id fj7-20020a05600c0c8700b0040772138bb7sm9873393wmb.2.2023.10.17.06.15.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 06:15:41 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Conor Dooley Subject: [PATCH v2 16/19] dt-bindings: riscv: add Zvfh[min] ISA extension description Date: Tue, 17 Oct 2023 15:14:53 +0200 Message-ID: <20231017131456.2053396-17-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017131456.2053396-1-cleger@rivosinc.com> References: <20231017131456.2053396-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add description for Zvfh[min] ISA extension[1] which can now be reported through hwprobe for userspace usage. Link: https://drive.google.com/file/d/1_Yt60HGAf1r1hx7JnsIptw0sqkBd9BQ8/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Acked-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index eb4c77b319fb..07678564f11d 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -354,6 +354,18 @@ properties: instructions, as ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. =20 + - const: zvfh + description: + The standard Zvfh extension for vectored half-precision + floating-point instructions, as ratified in commit e2ccd05 + ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. + + - const: zvfhmin + description: + The standard Zvfhmin extension for vectored minimal half-preci= sion + floating-point instructions, as ratified in commit e2ccd05 + ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. + - const: zvkb description: The standard Zvkb extension for vector cryptography bit-manipu= lation --=20 2.42.0 From nobody Thu Jan 1 23:52:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC01DCDB474 for ; Tue, 17 Oct 2023 13:16:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343837AbjJQNQh (ORCPT ); Tue, 17 Oct 2023 09:16:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343862AbjJQNPz (ORCPT ); Tue, 17 Oct 2023 09:15:55 -0400 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 132C5128 for ; Tue, 17 Oct 2023 06:15:45 -0700 (PDT) Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-40837396b1eso511565e9.1 for ; Tue, 17 Oct 2023 06:15:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697548544; x=1698153344; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/AFw9z9dpP/ckJjbN9Tmyf7889lk/XiWzjzseb60llw=; b=jHVmk0FHiIh5Oh37fKBkZvvMfEpdaVj6/WkMAW9BqKeFICa1KyRaXQgSTrJLDNgN4s yxMSMgkTskVFuI+OZZRDUiJR/QeB180RHnVi+k0NuaIeGnXza6i04PrXay+ZRo6c3wSO u/8/ZFcn3hWaVjSkvj5EjcOg7g5j/plBKLsz71rYhDEB2qIwoPi5PwZUmKJ4dowpYpCp UokGFXUl9F/iyYhSOQAzyIPcd70uMg8mq4GJ/ctR93/7NvCLaJ/+T437PntroQ71u167 8i0pBIUjTswX6qGUcsRym0zCvL4zUxqDBa/g8uHen87cULnV5U9kUH2wFtt72Q3GVW+d X5eQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697548544; x=1698153344; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/AFw9z9dpP/ckJjbN9Tmyf7889lk/XiWzjzseb60llw=; b=wJ2QJHs+hJ0jWV9KequAMuBrV+EVynIB1xdYwleZgHRM1MmLZbpIglJSUSN20/R5Oz 2KoAXwcDRiPiVAccu+rgAVY9y4ZojnYdM0lxPS1b7EiqTUclHrf8pSzhtCHjcx6jkewP odwoim0zzs2Fml8shY16FoLD0/t5ZSV2wJqj6XZiK4qWM6G10TQU2T7iXom5Iyoyfps4 tFl4/a1XIiItDzYD9ES4XIqwqL7JyMLc47Wgig7kI/LDiZWfRPFg+N/seC/WRn4InWNQ 799iI+GF1ucuAfzRdPVi/LzC0OdnZO2/UsIinHrTSXSmeP5NzmU0XVAefY8VVNYBx1MR UhVA== X-Gm-Message-State: AOJu0Yw5OdEnmtQY5QyeuPsZnSe8U6+c63vCQaOzJ+D0TxhIthf0u7fN nPjGCSH5/IjYljEQkaBhOM4WwA== X-Google-Smtp-Source: AGHT+IGD6k8FykqQQcX67hgxOWRNET24ch03mfUZpvzescEdSJ0tjByWo4qNt8mvukTxxj/gJ+XeOw== X-Received: by 2002:a05:600c:150c:b0:405:38d1:621 with SMTP id b12-20020a05600c150c00b0040538d10621mr1641979wmg.3.1697548543538; Tue, 17 Oct 2023 06:15:43 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:96:820c:ecf7:a817]) by smtp.gmail.com with ESMTPSA id fj7-20020a05600c0c8700b0040772138bb7sm9873393wmb.2.2023.10.17.06.15.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 06:15:42 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz Subject: [PATCH v2 17/19] riscv: add ISA extension parsing for Zfa Date: Tue, 17 Oct 2023 15:14:54 +0200 Message-ID: <20231017131456.2053396-18-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017131456.2053396-1-cleger@rivosinc.com> References: <20231017131456.2053396-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add parsing for Zfa ISA extension [1] which were ratified in commit 056b6ff467c7 ("Zfa is ratified") of riscv-isa-manual[2]. Link: https://drive.google.com/file/d/1VT6QIggpb59-8QRV266dEE4T8FZTxGq4/vie= w [1] Link: https://github.com/riscv/riscv-isa-manual/commits/056b6ff467c7 [2] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Evan Green --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index d9fb782f198d..8f324c646a73 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -84,6 +84,7 @@ #define RISCV_ISA_EXT_ZIHINTNTL 66 #define RISCV_ISA_EXT_ZVFH 67 #define RISCV_ISA_EXT_ZVFHMIN 68 +#define RISCV_ISA_EXT_ZFA 69 =20 #define RISCV_ISA_EXT_MAX 128 =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index c70885f5014b..296cc0025734 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -245,6 +245,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL), __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), + __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN), __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), --=20 2.42.0 From nobody Thu Jan 1 23:52:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1EA5CDB474 for ; Tue, 17 Oct 2023 13:16:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343846AbjJQNQl (ORCPT ); Tue, 17 Oct 2023 09:16:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55684 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343881AbjJQNP4 (ORCPT ); Tue, 17 Oct 2023 09:15:56 -0400 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE61211C for ; Tue, 17 Oct 2023 06:15:46 -0700 (PDT) Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-406532c49dcso17776885e9.0 for ; Tue, 17 Oct 2023 06:15:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697548545; x=1698153345; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=C4LU7gzy3Hbb258ih1CCCOKNMQ4iLpkNhcu+Kc5tvws=; b=Sqf8DRC0dIDb8iAXzK5SNL9AgKcXGH/ERKGG7WA2G1+MkJx7YQVm/JwrT9/z8QdKN6 v9aAN3djgk0HNGrw7/pt28XEDHpUC9FqhQgWuLFfpiTaYw4mJ1uubrKAC9H31fKO/QBi rc9IxKjOKp9MCrOi6LBsJDcgl8MJYQwShPBmkAUvuznKr41rcT7G1KQoEZLAPgpuZgiy 7JtlRznLH1l88ih8dOWFzaDQg5DE1gkfLyrUpPZivT2fZoug0sJ1v31vP19wAX4g15hp 3h2AaIqn2E6huzasjvfyQ151IEVw/vFViQyJJRQqx37FDigaIyHgduIa9amWoTgzUAPR SAKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697548545; x=1698153345; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=C4LU7gzy3Hbb258ih1CCCOKNMQ4iLpkNhcu+Kc5tvws=; b=jnZQ0wDrLR1E6PnjlEmp2ASMuRsuBG1uApxBnPp2xcYWtKY0mClJckek0KLstIoEiH fki9rhCmgMzDEAp5ZzJRDhukxF/a47j4wCf0VV8PjzVIa2nQ78y+ZRMslBDhwhqmM47f +z6BoZSPoGNd4PFNka2gpPQuovAXoJeXMYK6o61RfdXqYhKFP6Mi8s/nKWPMkLzjlE/2 n1Rqn06Fksbkevrb5/Pawl7z2IpY9J5tfeJCMwGQatm/vE/J/DLgQvZTfDRQ0YRSGg/P 0HzdiRRnoL74KV4cL2IVaXLfTIZm40KXg3UNFQc5CpLhCJXByG9g4vcoH1dQ9XB6OK7q IB+Q== X-Gm-Message-State: AOJu0YzW4jEE4BrllZNmtMVF0+VQJUCwzFoztO34f4qsaTp8GTxGTnNE gDAD4JVpffSwypUxyx+aVpBbeg== X-Google-Smtp-Source: AGHT+IHnpuaE2cK/zZiBwTN9WlDKtqZo7vhcXCnW27rCQU+XEM9WRrUe1J4q6WIg4FdM21J+kwJUfg== X-Received: by 2002:a05:600c:891:b0:405:4280:341d with SMTP id l17-20020a05600c089100b004054280341dmr1640946wmp.4.1697548544833; Tue, 17 Oct 2023 06:15:44 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:96:820c:ecf7:a817]) by smtp.gmail.com with ESMTPSA id fj7-20020a05600c0c8700b0040772138bb7sm9873393wmb.2.2023.10.17.06.15.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 06:15:44 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz Subject: [PATCH v2 18/19] riscv: hwprobe: export Zfa ISA extension Date: Tue, 17 Oct 2023 15:14:55 +0200 Message-ID: <20231017131456.2053396-19-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017131456.2053396-1-cleger@rivosinc.com> References: <20231017131456.2053396-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Export Zfa ISA extension[1] through hwprobe. Link: https://drive.google.com/file/d/1VT6QIggpb59-8QRV266dEE4T8FZTxGq4/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Evan Green --- Documentation/riscv/hwprobe.rst | 4 ++++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_riscv.c | 1 + 3 files changed, 6 insertions(+) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.= rst index 782ac26cb92a..f81e3c93ac1e 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -154,6 +154,10 @@ The following keys are defined: defined in the RISC-V Vector manual starting from commit e2ccd0548d= 6c ("Remove draft warnings from Zvfh[min]"). =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZFA`: The Zfa extension is supported as + defined in the RISC-V ISA manual starting from commit 056b6ff467c7 + ("Zfa is ratified"). + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 79407010952a..4014492c3960 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -54,6 +54,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZIHINTNTL (1 << 28) #define RISCV_HWPROBE_EXT_ZVFH (1 << 29) #define RISCV_HWPROBE_EXT_ZVFHMIN (1 << 30) +#define RISCV_HWPROBE_EXT_ZFA (1 << 31) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 8d6edd721627..a6a063f1dcf5 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -192,6 +192,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, if (has_fpu()) { CHECK_ISA_EXT(ZFH); CHECK_ISA_EXT(ZFHMIN); + CHECK_ISA_EXT(ZFA); } #undef CHECK_ISA_EXT } --=20 2.42.0 From nobody Thu Jan 1 23:52:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 541FFCDB474 for ; Tue, 17 Oct 2023 13:16:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235024AbjJQNQp (ORCPT ); Tue, 17 Oct 2023 09:16:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52320 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343850AbjJQNP5 (ORCPT ); Tue, 17 Oct 2023 09:15:57 -0400 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 76555184 for ; Tue, 17 Oct 2023 06:15:48 -0700 (PDT) Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-4064e3c7c07so11476445e9.1 for ; Tue, 17 Oct 2023 06:15:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697548546; x=1698153346; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VR7lcVmAz+UhHjZIcV3xEUmifohwbRxKjtUEu/6fWYw=; b=N6VSQM6+LN05iMnXVzLwoywZD8IMN96hW9EZUE0Wwx8wMtQMP2A2loQ8djiaZzvmSc 8eKhDmtdi08J/gV3FXfS0YMFvSj++Ki4nBjRg9i+Uh0X3yMWzaoEDMR9LQRO303Uv3rg S05Ut2C/0vkpf6P80kRbNiMTdOK6tRRVqegFjX1awkBr4KNYh/h1abOS3bcj9HAzTbxk 9kVB8JgLwqRMh2mkslG/VH4FmGfhDEtDWaVIBmTu8dSyIn3oQJoeqW6QNPBjrHKw8OQB 8GAzxvcPAH9CKzngs7SoSwDgyRhIXwXAgToRboGS8k80ox1wgRE5B/XBxCVXuapY1Kq9 HhBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697548546; x=1698153346; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VR7lcVmAz+UhHjZIcV3xEUmifohwbRxKjtUEu/6fWYw=; b=ofVJVrpXcjh1yqZ1TU1Gf708U8V20I7vidDHhmLKSs1jgKOMln7yUWnCs91oCskVEl kQKp2+lgF3908SO9AqsiulAxpj5Y/9u7T1Mn1M2hG/SZkq6UIEYc5cZbRagHX5ziHVDq sc0mCCYxse/NSqt6INS8B7BRjoWXS7EudfxPISrAzdmkr/A9n8p8aKQe5RjWFTiDb1hR BUDqERgL2p0zA9+uS8W4irYNFd/CdnND3bHZucouX+T6PSWn3nHdnfQZmTOocSx4b8j0 6zkdJeayTZtO5g6LeB3mUHmjok73M1XzMLlaOVcDS4VxMqLOY9C1nHuDte4LGIf72+fa +mEg== X-Gm-Message-State: AOJu0Yx6wy0tZAPizPZrBKj9IbBz2ZfZBLRCAY9JXrFPC/pjbk13da26 0kq8c9GQBVIKG7PPXKH1NkDqNw== X-Google-Smtp-Source: AGHT+IHIQDkhluCQslFyJdgDxKAY9q+c4pJ4JyE/Vo42cW4xdwk6uSfnB9uiUpQR0s0lka7NJ6WUWQ== X-Received: by 2002:a05:600c:5026:b0:404:75cc:62e6 with SMTP id n38-20020a05600c502600b0040475cc62e6mr1650073wmr.3.1697548545908; Tue, 17 Oct 2023 06:15:45 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:96:820c:ecf7:a817]) by smtp.gmail.com with ESMTPSA id fj7-20020a05600c0c8700b0040772138bb7sm9873393wmb.2.2023.10.17.06.15.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 06:15:45 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz Subject: [PATCH v2 19/19] dt-bindings: riscv: add Zfa ISA extension description Date: Tue, 17 Oct 2023 15:14:56 +0200 Message-ID: <20231017131456.2053396-20-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017131456.2053396-1-cleger@rivosinc.com> References: <20231017131456.2053396-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add description for the Zfa ISA extension[1] which can now be reported through hwprobe for userspace usage. Link: https://drive.google.com/file/d/1VT6QIggpb59-8QRV266dEE4T8FZTxGq4/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 07678564f11d..3033afcea033 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -208,6 +208,12 @@ properties: instructions as ratified at commit 6d33919 ("Merge pull reques= t #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. =20 + - const: zfa + description: + The standard Zfa extension for additional floating point + instructions, as ratified in commit 056b6ff ("Zfa is ratified"= ) of + riscv-isa-manual. + - const: zfh description: The standard Zfh extension for 16-bit half-precision binary --=20 2.42.0