From nobody Fri Sep 20 11:38:19 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCBF0CDB482 for ; Tue, 17 Oct 2023 06:48:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234579AbjJQGsG (ORCPT ); Tue, 17 Oct 2023 02:48:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234605AbjJQGrn (ORCPT ); Tue, 17 Oct 2023 02:47:43 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E7E75F0; Mon, 16 Oct 2023 23:47:37 -0700 (PDT) X-UUID: 04d371b46cb911ee8051498923ad61e6-20231017 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=TmWMoMNwy1Vj/2pYXEudaUwW19Ln7StYihfj7Lm+CSM=; b=Au+Xr0ud2xwe02kESKJ9mcrBySYJfNw8qay6N07PyzRtz6kugvMhGsaCbXAVNM38j9CXRtqDrCPe4nXIrdaOiNq8Xq6toXFWewveH0LpXPYtQSWGGR1TyaJS9cVmrWcKMpqbFxH+gPBhCzt3I5/kOgQNG9LS1UAi7M/DTE/IgoU=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:4abe5145-5f9c-4dd4-9763-b51afc6f585b,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:5f78ec9,CLOUDID:1725e2f0-9a6e-4c39-b73e-f2bc08ca3dc5,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 04d371b46cb911ee8051498923ad61e6-20231017 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1242859224; Tue, 17 Oct 2023 14:47:20 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 17 Oct 2023 14:47:19 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 17 Oct 2023 14:47:19 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , Krzysztof Kozlowski , Matthias Brugger CC: Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , "Chen-Yu Tsai" , Sean Paul , , , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Hsiao Chien Sung Subject: [PATCH v3 06/11] drm/mediatek: Support alpha blending in display driver Date: Tue, 17 Oct 2023 14:47:12 +0800 Message-ID: <20231017064717.21616-7-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231017064717.21616-1-shawn.sung@mediatek.com> References: <20231017064717.21616-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--13.241300-8.000000 X-TMASE-MatchedRID: sHBNP13/Fsz2fv0LTPfvM6MVgdN9w+TCG9Itfzsy8/Xvnm3ZesFzgrxX z8rVhwNp09NQNrxIpFaXO2uBwefMOJOD/r6k201R4pdq9sdj8LW4vBuE2X0HlfNhzIgXtFJVqcT eK67rgVPgN525AmZSDlrpZ2UgV/eS1x+eOID2gFVIOSHptb5tx5qCl1R34jDPtxF8SAx8/RmOx7 X7h9Du63wAGFxWrqclKSiRRLHTYarlRxm3A2wKuhRFJJyf5BJe3QfwsVk0UbtuRXh7bFKB7j4Mm vPrGH5K+6DJezH7jeu8YBKVTOFKeAwhFEZZKPcO66XHIc5w+gc= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--13.241300-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 00459956C72CDF8663DBAED2D777653D33981E0D0B403A95CF843A006A2041D42000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support alpha blending by adding correct blend mode and alpha property in plane initialization. Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 10 ++++++++++ drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 ++ drivers/gpu/drm/mediatek/mtk_drm_plane.c | 11 +++++++++++ 3 files changed, 23 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index a4b740420ebb..0467e80444d3 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -14,6 +14,7 @@ =20 #include #include +#include #include #include #include @@ -305,6 +306,9 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys= 0_driver_data =3D { .conn_routes_num =3D ARRAY_SIZE(mt8188_mtk_ddp_main_routes), .mmsys_dev_num =3D 2, .max_pitch =3D GENMASK(15, 0), + .blend_mode =3D BIT(DRM_MODE_BLEND_PIXEL_NONE) | + BIT(DRM_MODE_BLEND_PREMULTI) | + BIT(DRM_MODE_BLEND_COVERAGE), }; =20 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data =3D { @@ -320,6 +324,9 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys= 0_driver_data =3D { .main_len =3D ARRAY_SIZE(mt8195_mtk_ddp_main), .mmsys_dev_num =3D 2, .max_pitch =3D GENMASK(15, 0), + .blend_mode =3D BIT(DRM_MODE_BLEND_PIXEL_NONE) | + BIT(DRM_MODE_BLEND_PREMULTI) | + BIT(DRM_MODE_BLEND_COVERAGE), }; =20 static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data =3D { @@ -328,6 +335,9 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys= 1_driver_data =3D { .mmsys_id =3D 1, .mmsys_dev_num =3D 2, .max_pitch =3D GENMASK(15, 0), + .blend_mode =3D BIT(DRM_MODE_BLEND_PIXEL_NONE) | + BIT(DRM_MODE_BLEND_PREMULTI) | + BIT(DRM_MODE_BLEND_COVERAGE), }; =20 static const struct of_device_id mtk_drm_of_ids[] =3D { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/media= tek/mtk_drm_drv.h index 833ecee855bb..27865f8f1160 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -42,6 +42,7 @@ struct mtk_drm_route { * @mmsys_id: multi-media system ID * @mmsys_dev_num: number of devices for in the mmsys as a whole * @max_pitch: maximum pitch in bytes that the mmsys supports + * @blend_mode: alpha blend modes that the mmsys supports */ struct mtk_mmsys_driver_data { const unsigned int *main_path; @@ -58,6 +59,7 @@ struct mtk_mmsys_driver_data { unsigned int mmsys_dev_num; =20 u32 max_pitch; + u32 blend_mode; }; =20 struct mtk_drm_private { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c b/drivers/gpu/drm/med= iatek/mtk_drm_plane.c index 9208f03b3f8c..a6cf1ab94e42 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c @@ -327,6 +327,7 @@ int mtk_plane_init(struct drm_device *dev, struct drm_p= lane *plane, size_t num_formats) { int err; + struct mtk_drm_private *priv =3D dev->dev_private; =20 if (!formats || !num_formats) { DRM_ERROR("no formats for plane\n"); @@ -349,6 +350,16 @@ int mtk_plane_init(struct drm_device *dev, struct drm_= plane *plane, DRM_INFO("Create rotation property failed\n"); } =20 + err =3D drm_plane_create_alpha_property(plane); + if (err) + DRM_ERROR("failed to create property: alpha\n"); + + if (priv->data->blend_mode) { + err =3D drm_plane_create_blend_mode_property(plane, priv->data->blend_mo= de); + if (err) + DRM_ERROR("failed to create property: blend_mode\n"); + } + drm_plane_helper_add(plane, &mtk_plane_helper_funcs); =20 return 0; --=20 2.18.0