From nobody Fri Sep 20 12:40:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2297CDB474 for ; Tue, 17 Oct 2023 06:47:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234577AbjJQGri (ORCPT ); Tue, 17 Oct 2023 02:47:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52260 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229666AbjJQGrd (ORCPT ); Tue, 17 Oct 2023 02:47:33 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F8E1B6; Mon, 16 Oct 2023 23:47:27 -0700 (PDT) X-UUID: 04aca98a6cb911eea33bb35ae8d461a2-20231017 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=pbIhtZN7tbeEZN7b/e6iHZByMWn+L/d3BOIBFhKze9A=; b=GGmLyJqkEJL7Mj6kDDaw1csVJQJF3wLlDXTmDbNxV7auhmIlfrQOIj0cuy8tnX2FCZ1HlAvvt/CL1rBVdhKevtYkdFGxgG2dMYikt5ne54iYjgy41iouwGd2k3wUx+qXTL5CY3SAC0KvF4RKmabQcEeCqoFIm7P8A5HAFLBAlRw=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:e44afa21-2643-4d6a-97c7-15d8ff72fccf,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:5f78ec9,CLOUDID:7ceb36c4-1e57-4345-9d31-31ad9818b39f,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 04aca98a6cb911eea33bb35ae8d461a2-20231017 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 857944696; Tue, 17 Oct 2023 14:47:19 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 17 Oct 2023 14:47:18 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 17 Oct 2023 14:47:18 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , Krzysztof Kozlowski , Matthias Brugger CC: Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , "Chen-Yu Tsai" , Sean Paul , , , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Hsiao Chien Sung Subject: [PATCH v3 01/11] soc: mediatek: Add register definitions for GCE Date: Tue, 17 Oct 2023 14:47:07 +0800 Message-ID: <20231017064717.21616-2-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231017064717.21616-1-shawn.sung@mediatek.com> References: <20231017064717.21616-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--0.744200-8.000000 X-TMASE-MatchedRID: +aiIZkdJNeWLwgJA7qJvFMnUT+eskUQPUAjrAJWsTe//evmlVf9xZkN+ V6ZFLcNdK+GE57usLIi8xfjW6NxdqFfnsPC4h9MjSEQN/D/3cG4IYICTzfK2gccfB5qY+d3io8W MkQWv6iXBcIE78YqRWo6HM5rqDwqtZHKDEaeJy4byKRh4CNRN852PVxVMV2ioN9hxljcgqvC+po L87PUishRY09hgyy5B79Evy1WLpYHKWZR2fV44oViLpGR6nqyUwZBgUyJVEbl6Fw8/PpTMRaVvm iAyeA2kc5MSfkiJFI5p3LlElBHTlw== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--0.744200-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: AA0BAC5DCBAFE761AFDBC181DEC6779C639F59B2CD1D8D60EC3353CAEA8FA3C52000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add register definitions for GCE so users can use them as a buffer to store data. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- include/linux/soc/mediatek/mtk-cmdq.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/medi= atek/mtk-cmdq.h index 649955d2cf5c..a253c001c861 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -14,6 +14,16 @@ #define CMDQ_ADDR_HIGH(addr) ((u32)(((addr) >> 16) & GENMASK(31, 0))) #define CMDQ_ADDR_LOW(addr) ((u16)(addr) | BIT(1)) =20 +/* + * Every cmdq thread has its own SPRs (Specific Purpose Registers), + * so there are 4 * 24 (threads) =3D 96 SPRs in GCE that shares the + * same indexes below + */ +#define CMDQ_THR_SPR_IDX0 (0) +#define CMDQ_THR_SPR_IDX1 (1) +#define CMDQ_THR_SPR_IDX2 (2) +#define CMDQ_THR_SPR_IDX3 (3) + struct cmdq_pkt; =20 struct cmdq_client_reg { --=20 2.18.0