From nobody Wed Dec 17 10:05:36 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8314BCDB474 for ; Tue, 17 Oct 2023 05:26:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234501AbjJQF0E (ORCPT ); Tue, 17 Oct 2023 01:26:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34530 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234656AbjJQFZh (ORCPT ); Tue, 17 Oct 2023 01:25:37 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8171D1B5; Mon, 16 Oct 2023 22:25:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1697520323; x=1729056323; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=Ui1Hqm41JSxotFlyE4G0v69tZLA9xc0/FYrcSUnN77Y=; b=Nbm82neaf8pjai/Dy54azXizfXgtaURLoYmzxufKk6uy9d3WxcIzQOTT L+hlwlb7fnxLpcxqUavMUwmTi5g8z/HHGIaQro14o2U6/XEaPAkwR/f4L DNmlby21/WU0ohkl7jd4LMBEs8zIMAet8ohI+wkFYaCfSyO8+I51EZ8YF 3rIULRvrdQhEBSJEvdoixFkrefb8CRXkWWFTMtdyi3ZkzT/wOXVI24ITi rEVJnZ7BmQgxHVKI52SpQ+2j67FgTb6aeFut32VlE74vIp6W0csMesqXF PGxaM3ONt3Yh8jPjxu1vfEJk/hn312MjYemNmq7CyZ6gaYe/5FUdQAH9H w==; X-IronPort-AV: E=McAfee;i="6600,9927,10865"; a="388561779" X-IronPort-AV: E=Sophos;i="6.03,231,1694761200"; d="scan'208";a="388561779" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2023 22:25:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10865"; a="1087358019" X-IronPort-AV: E=Sophos;i="6.03,231,1694761200"; d="scan'208";a="1087358019" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by fmsmga005.fm.intel.com with ESMTP; 16 Oct 2023 22:25:18 -0700 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, jstultz@google.com, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org Cc: x86@kernel.org, linux-doc@vger.kernel.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, pandith.n@intel.com, mallikarjunappa.sangannavar@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [PATCH v1 5/6] Documentation: driver-api: pps: Add Intel Timed I/O PPS generator Date: Tue, 17 Oct 2023 10:54:56 +0530 Message-Id: <20231017052457.25287-6-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231017052457.25287-1-lakshmi.sowjanya.d@intel.com> References: <20231017052457.25287-1-lakshmi.sowjanya.d@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Lakshmi Sowjanya D Add Intel Timed I/O PPS usage instructions. Co-developed-by: Pandith N Signed-off-by: Pandith N Signed-off-by: Lakshmi Sowjanya D Reviewed-by: Andy Shevchenko --- Documentation/driver-api/pps.rst | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/driver-api/pps.rst b/Documentation/driver-api/pp= s.rst index 2d6b99766ee8..35bba2bf98a8 100644 --- a/Documentation/driver-api/pps.rst +++ b/Documentation/driver-api/pps.rst @@ -240,3 +240,25 @@ delay between assert and clear edge as small as possib= le to reduce system latencies. But if it is too small slave won't be able to capture clear edge transition. The default of 30us should be good enough in most situations. The delay can be selected using 'delay' pps_gen_parport module parameter. + + +Intel Timed I/O PPS signal generator +------------------------------------ + +Intel Timed I/O is a high precision device, present on 2019 and newer Intel +CPUs, that can generate PPS signal. + +Timed I/O and system time are both driven by same hardware clock, The sign= al +generated with a precision of ~20 nanoseconds. The generated PPS signal +is used to synchronize an external device with system clock. For example, +Share your clock with a device that receives PPS signal, generated by +Timed I/O device. There are dedicated Timed I/O pins to deliver PPS signal +to an external device. + +Usage of Intel Timed I/O as PPS generator: + +Start generating PPS signal:: + $echo 1 > /sys/devices/platform/INTCxxxx\:00/enable + +Stop generating PPS signal:: + $echo 0 > /sys/devices/platform/INTCxxxx\:00/enable --=20 2.17.1