From nobody Wed Dec 17 09:44:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A6F0CDB474 for ; Tue, 17 Oct 2023 05:23:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234397AbjJQFXs (ORCPT ); Tue, 17 Oct 2023 01:23:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55708 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234396AbjJQFXh (ORCPT ); Tue, 17 Oct 2023 01:23:37 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 0C0AEA4 for ; Mon, 16 Oct 2023 22:23:36 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3C2961007; Mon, 16 Oct 2023 22:24:16 -0700 (PDT) Received: from u200865.usa.arm.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 724BB3F5A1; Mon, 16 Oct 2023 22:23:35 -0700 (PDT) From: Jeremy Linton To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, maz@kernel.org, anshuman.khandual@arm.com, krisman@suse.de, broonie@kernel.org, james.morse@arm.com, ionela.voinescu@arm.com, linux-kernel@vger.kernel.org, Jeremy Linton Subject: [PATCH v2 3/3] arm64: cpufeature: Change 32-bit EL0 to display enabled cores Date: Tue, 17 Oct 2023 00:23:22 -0500 Message-ID: <20231017052322.1211099-4-jeremy.linton@arm.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231017052322.1211099-1-jeremy.linton@arm.com> References: <20231017052322.1211099-1-jeremy.linton@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Now that we have the ability to display the list of cores with a feature when it is selectivly enabled, lets display the cores enabled for 32-bit use at EL0. Signed-off-by: Jeremy Linton --- arch/arm64/kernel/cpufeature.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index b7b67bac0e60..512cbe446b41 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1533,8 +1533,17 @@ static bool has_32bit_el0(const struct arm64_cpu_cap= abilities *entry, int scope) if (!has_cpuid_feature(entry, scope)) return allow_mismatched_32bit_el0; =20 - if (scope =3D=3D SCOPE_SYSTEM) - pr_info("detected: 32-bit EL0 Support\n"); + if (scope =3D=3D SCOPE_SYSTEM) { + struct arm64_cpu_capabilities *has_32bit; + + has_32bit =3D (struct arm64_cpu_capabilities *)entry; + + has_32bit->cpus =3D system_32bit_el0_cpumask(); + if (has_32bit->cpus =3D=3D cpu_possible_mask) + has_32bit->cpus =3D cpu_online_mask; + if (has_32bit->cpus =3D=3D cpu_none_mask) + has_32bit->cpus =3D NULL; + } =20 return true; } @@ -2307,9 +2316,11 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, IMP) }, { + .desc =3D "32-bit EL0 Support", .capability =3D ARM64_HAS_32BIT_EL0_DO_NOT_USE, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_32bit_el0, + .cpus =3D cpu_none_mask, ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32) }, #ifdef CONFIG_KVM --=20 2.41.0