From nobody Wed Dec 17 08:08:55 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74EB6CDB474 for ; Tue, 17 Oct 2023 05:23:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234412AbjJQFXi (ORCPT ); Tue, 17 Oct 2023 01:23:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45444 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234284AbjJQFXf (ORCPT ); Tue, 17 Oct 2023 01:23:35 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 9D6FCA4 for ; Mon, 16 Oct 2023 22:23:33 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BD9D72F4; Mon, 16 Oct 2023 22:24:13 -0700 (PDT) Received: from u200865.usa.arm.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0347E3F5A1; Mon, 16 Oct 2023 22:23:32 -0700 (PDT) From: Jeremy Linton To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, maz@kernel.org, anshuman.khandual@arm.com, krisman@suse.de, broonie@kernel.org, james.morse@arm.com, ionela.voinescu@arm.com, linux-kernel@vger.kernel.org, Jeremy Linton Subject: [PATCH v2 1/3] arm64: cpufeature: Display the set of cores with a feature Date: Tue, 17 Oct 2023 00:23:20 -0500 Message-ID: <20231017052322.1211099-2-jeremy.linton@arm.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231017052322.1211099-1-jeremy.linton@arm.com> References: <20231017052322.1211099-1-jeremy.linton@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The AMU feature can be enabled on a subset of the cores in a system. Because of that, it prints a message for each core as it is detected. This becomes tedious when there are hundreds of cores. Instead, for CPU features which can be enabled on a subset of the present cores, lets wait until update_cpu_capabilities() and print the subset of cores the feature was enabled on. Signed-off-by: Jeremy Linton Reviewed-by: Ionela Voinescu Tested-by: Ionela Voinescu Reviewed-by: Punit Agrawal Tested-by: Punit Agrawal --- arch/arm64/include/asm/cpufeature.h | 2 ++ arch/arm64/kernel/cpufeature.c | 22 +++++++++++++--------- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/c= pufeature.h index 5bba39376055..19b4d001d845 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -23,6 +23,7 @@ #include #include #include +#include =20 /* * CPU feature register tracking @@ -380,6 +381,7 @@ struct arm64_cpu_capabilities { * method is robust against being called multiple times. */ const struct arm64_cpu_capabilities *match_list; + const struct cpumask *cpus; }; =20 static inline int cpucap_default_scope(const struct arm64_cpu_capabilities= *cap) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 444a73c2e638..2dd695fc3472 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1944,8 +1944,6 @@ int get_cpu_with_amu_feat(void) static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) { if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { - pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n", - smp_processor_id()); cpumask_set_cpu(smp_processor_id(), &amu_cpus); =20 /* 0 reference values signal broken/disabled counters */ @@ -2405,16 +2403,12 @@ static const struct arm64_cpu_capabilities arm64_fe= atures[] =3D { #endif /* CONFIG_ARM64_RAS_EXTN */ #ifdef CONFIG_ARM64_AMU_EXTN { - /* - * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=3Dy. - * Therefore, don't provide .desc as we don't want the detection - * message to be shown until at least one CPU is detected to - * support the feature. - */ + .desc =3D "Activity Monitors Unit (AMU)", .capability =3D ARM64_HAS_AMU_EXTN, .type =3D ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, .matches =3D has_amu, .cpu_enable =3D cpu_amu_enable, + .cpus =3D &amu_cpus, ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP) }, #endif /* CONFIG_ARM64_AMU_EXTN */ @@ -2981,7 +2975,7 @@ static void update_cpu_capabilities(u16 scope_mask) !caps->matches(caps, cpucap_default_scope(caps))) continue; =20 - if (caps->desc) + if (caps->desc && !caps->cpus) pr_info("detected: %s\n", caps->desc); =20 __set_bit(caps->capability, system_cpucaps); @@ -3330,6 +3324,7 @@ unsigned long cpu_get_elf_hwcap2(void) =20 static void __init setup_system_capabilities(void) { + int i; /* * We have finalised the system-wide safe feature * registers, finalise the capabilities that depend @@ -3338,6 +3333,15 @@ static void __init setup_system_capabilities(void) */ update_cpu_capabilities(SCOPE_SYSTEM); enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); + + for (i =3D 0; i < ARM64_NCAPS; i++) { + const struct arm64_cpu_capabilities *caps =3D cpucap_ptrs[i]; + + if (caps && caps->cpus && caps->desc && + cpumask_any(caps->cpus) < nr_cpu_ids) + pr_info("detected: %s on CPU%*pbl\n", + caps->desc, cpumask_pr_args(caps->cpus)); + } } =20 void __init setup_cpu_features(void) --=20 2.41.0 From nobody Wed Dec 17 08:08:55 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A345CDB474 for ; Tue, 17 Oct 2023 05:23:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234428AbjJQFXo (ORCPT ); Tue, 17 Oct 2023 01:23:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55700 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234391AbjJQFXg (ORCPT ); Tue, 17 Oct 2023 01:23:36 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id E1B70B6 for ; Mon, 16 Oct 2023 22:23:34 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1A283FEC; Mon, 16 Oct 2023 22:24:15 -0700 (PDT) Received: from u200865.usa.arm.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 507A03F5A1; Mon, 16 Oct 2023 22:23:34 -0700 (PDT) From: Jeremy Linton To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, maz@kernel.org, anshuman.khandual@arm.com, krisman@suse.de, broonie@kernel.org, james.morse@arm.com, ionela.voinescu@arm.com, linux-kernel@vger.kernel.org, Jeremy Linton Subject: [PATCH v2 2/3] arm64: cpufeature: Change DBM to display enabled cores Date: Tue, 17 Oct 2023 00:23:21 -0500 Message-ID: <20231017052322.1211099-3-jeremy.linton@arm.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231017052322.1211099-1-jeremy.linton@arm.com> References: <20231017052322.1211099-1-jeremy.linton@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Now that we have the ability to display the list of cores with a feature when its selectivly enabled, lets convert DBM to use that as well. Signed-off-by: Jeremy Linton --- arch/arm64/kernel/cpufeature.c | 33 ++++++++------------------------- 1 file changed, 8 insertions(+), 25 deletions(-) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 2dd695fc3472..b7b67bac0e60 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1848,6 +1848,8 @@ static int __init parse_kpti(char *str) early_param("kpti", parse_kpti); =20 #ifdef CONFIG_ARM64_HW_AFDBM +static struct cpumask dbm_cpus __read_mostly; + static inline void __cpu_enable_hw_dbm(void) { u64 tcr =3D read_sysreg(tcr_el1) | TCR_HD; @@ -1883,35 +1885,22 @@ static bool cpu_can_use_dbm(const struct arm64_cpu_= capabilities *cap) =20 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) { - if (cpu_can_use_dbm(cap)) + if (cpu_can_use_dbm(cap)) { __cpu_enable_hw_dbm(); + cpumask_set_cpu(smp_processor_id(), &dbm_cpus); + } } =20 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, int __unused) { - static bool detected =3D false; /* * DBM is a non-conflicting feature. i.e, the kernel can safely * run a mix of CPUs with and without the feature. So, we * unconditionally enable the capability to allow any late CPU * to use the feature. We only enable the control bits on the - * CPU, if it actually supports. - * - * We have to make sure we print the "feature" detection only - * when at least one CPU actually uses it. So check if this CPU - * can actually use it and print the message exactly once. - * - * This is safe as all CPUs (including secondary CPUs - due to the - * LOCAL_CPU scope - and the hotplugged CPUs - via verification) - * goes through the "matches" check exactly once. Also if a CPU - * matches the criteria, it is guaranteed that the CPU will turn - * the DBM on, as the capability is unconditionally enabled. + * CPU, if it is supported. */ - if (!detected && cpu_can_use_dbm(cap)) { - detected =3D true; - pr_info("detected: Hardware dirty bit management\n"); - } =20 return true; } @@ -2448,18 +2437,12 @@ static const struct arm64_cpu_capabilities arm64_fe= atures[] =3D { }, #ifdef CONFIG_ARM64_HW_AFDBM { - /* - * Since we turn this on always, we don't want the user to - * think that the feature is available when it may not be. - * So hide the description. - * - * .desc =3D "Hardware pagetable Dirty Bit Management", - * - */ + .desc =3D "Hardware dirty bit management", .type =3D ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, .capability =3D ARM64_HW_DBM, .matches =3D has_hw_dbm, .cpu_enable =3D cpu_enable_hw_dbm, + .cpus =3D &dbm_cpus, ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM) }, #endif --=20 2.41.0 From nobody Wed Dec 17 08:08:55 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A6F0CDB474 for ; Tue, 17 Oct 2023 05:23:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234397AbjJQFXs (ORCPT ); Tue, 17 Oct 2023 01:23:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55708 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234396AbjJQFXh (ORCPT ); Tue, 17 Oct 2023 01:23:37 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 0C0AEA4 for ; Mon, 16 Oct 2023 22:23:36 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3C2961007; Mon, 16 Oct 2023 22:24:16 -0700 (PDT) Received: from u200865.usa.arm.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 724BB3F5A1; Mon, 16 Oct 2023 22:23:35 -0700 (PDT) From: Jeremy Linton To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, maz@kernel.org, anshuman.khandual@arm.com, krisman@suse.de, broonie@kernel.org, james.morse@arm.com, ionela.voinescu@arm.com, linux-kernel@vger.kernel.org, Jeremy Linton Subject: [PATCH v2 3/3] arm64: cpufeature: Change 32-bit EL0 to display enabled cores Date: Tue, 17 Oct 2023 00:23:22 -0500 Message-ID: <20231017052322.1211099-4-jeremy.linton@arm.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231017052322.1211099-1-jeremy.linton@arm.com> References: <20231017052322.1211099-1-jeremy.linton@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Now that we have the ability to display the list of cores with a feature when it is selectivly enabled, lets display the cores enabled for 32-bit use at EL0. Signed-off-by: Jeremy Linton --- arch/arm64/kernel/cpufeature.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index b7b67bac0e60..512cbe446b41 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1533,8 +1533,17 @@ static bool has_32bit_el0(const struct arm64_cpu_cap= abilities *entry, int scope) if (!has_cpuid_feature(entry, scope)) return allow_mismatched_32bit_el0; =20 - if (scope =3D=3D SCOPE_SYSTEM) - pr_info("detected: 32-bit EL0 Support\n"); + if (scope =3D=3D SCOPE_SYSTEM) { + struct arm64_cpu_capabilities *has_32bit; + + has_32bit =3D (struct arm64_cpu_capabilities *)entry; + + has_32bit->cpus =3D system_32bit_el0_cpumask(); + if (has_32bit->cpus =3D=3D cpu_possible_mask) + has_32bit->cpus =3D cpu_online_mask; + if (has_32bit->cpus =3D=3D cpu_none_mask) + has_32bit->cpus =3D NULL; + } =20 return true; } @@ -2307,9 +2316,11 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, IMP) }, { + .desc =3D "32-bit EL0 Support", .capability =3D ARM64_HAS_32BIT_EL0_DO_NOT_USE, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_32bit_el0, + .cpus =3D cpu_none_mask, ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32) }, #ifdef CONFIG_KVM --=20 2.41.0