From nobody Wed Dec 17 09:50:04 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F993CDB465 for ; Tue, 17 Oct 2023 00:48:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234257AbjJQAsq (ORCPT ); Mon, 16 Oct 2023 20:48:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46734 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234332AbjJQAsk (ORCPT ); Mon, 16 Oct 2023 20:48:40 -0400 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D26CF2 for ; Mon, 16 Oct 2023 17:48:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1697503718; x=1729039718; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=a9SqKUtQWxi9wsxrdsiDkqkB6ZJKJ0NNGX75QDvdcLg=; b=GrOGJKtcT5Tmusbt8yPeRHn62gVtoGNK/yH2dNqDvnu1PoagLqtvQzwV X+xP1I/MHGK2lRNrozShzZlSZ2UJu9A3PSdOhLt6puszuiGNW6oDt6Xwj jXl6jddBvyyeaNUUMwlPvhqsfwCN+gbM+DJ56PBjq76kfwvHp5jk8uDmr wJRrU90chZFfsLR3SQYjbphDNfle2/Ga0jmk65jm2b7J1OifJA4uf6OQo pJOnzOMrasw2AfIXLvpfCBw+y5HSxWbzhF2eXq8uOP8UJfMZW4bphW6DJ 0r6DKjfL+71KVVohTjSRUHJaNL2D78TU6kQeI/MjXHUAzFdk+BbxwAyay A==; X-IronPort-AV: E=McAfee;i="6600,9927,10865"; a="382893293" X-IronPort-AV: E=Sophos;i="6.03,230,1694761200"; d="scan'208";a="382893293" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2023 17:48:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10865"; a="705793729" X-IronPort-AV: E=Sophos;i="6.03,230,1694761200"; d="scan'208";a="705793729" Received: from sqa-gate.sh.intel.com (HELO spr-2s5.tsp.org) ([10.239.48.212]) by orsmga003.jf.intel.com with ESMTP; 16 Oct 2023 17:48:33 -0700 From: Tina Zhang To: iommu@lists.linux.dev, linux-kernel@vger.kernel.org Cc: David Woodhouse , Lu Baolu , Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe , Kevin Tian , Nicolin Chen , Michael Shavit , Vasant Hegde , Tina Zhang , Jason Gunthorpe Subject: [PATCH v8 2/5] iommu: Add mm_get_enqcmd_pasid() helper function Date: Tue, 17 Oct 2023 08:47:59 +0800 Message-Id: <20231017004802.109618-3-tina.zhang@intel.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20231017004802.109618-1-tina.zhang@intel.com> References: <20231017004802.109618-1-tina.zhang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" mm_get_enqcmd_pasid() should be used by architecture code and closely related to learn the PASID value that the x86 ENQCMD operation should use for the mm. For the moment SMMUv3 uses this without any connection to ENQCMD, it will be cleaned up similar to how the prior patch made VT-d use the PASID argument of set_dev_pasid(). The motivation is to replace mm->pasid with an iommu private data structure that is introduced in a later patch. Reviewed-by: Lu Baolu Reviewed-by: Jason Gunthorpe Tested-by: Nicolin Chen Signed-off-by: Tina Zhang --- Change in v7: - Update the commit message. Changes in v6: - Let SMMUv3 call mm_get_enqcmd_pasid(). - Let iommu_sva_get_pasid() call mm_get_enqcmd_pasid(). Change in v2: - Change mm_get_pasid() to mm_get_enqcmd_pasid() arch/x86/kernel/traps.c | 2 +- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 12 ++++++------ drivers/iommu/iommu-sva.c | 2 +- include/linux/iommu.h | 12 ++++++++++++ 4 files changed, 20 insertions(+), 8 deletions(-) diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index c876f1d36a81..832f4413d96a 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -591,7 +591,7 @@ static bool try_fixup_enqcmd_gp(void) if (!mm_valid_pasid(current->mm)) return false; =20 - pasid =3D current->mm->pasid; + pasid =3D mm_get_enqcmd_pasid(current->mm); =20 /* * Did this thread already have its PASID activated? diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iomm= u/arm/arm-smmu-v3/arm-smmu-v3-sva.c index 8a16cd3ef487..49aaa7262ea1 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -229,7 +229,7 @@ static void arm_smmu_mm_arch_invalidate_secondary_tlbs(= struct mmu_notifier *mn, smmu_domain); } =20 - arm_smmu_atc_inv_domain(smmu_domain, mm->pasid, start, size); + arm_smmu_atc_inv_domain(smmu_domain, mm_get_enqcmd_pasid(mm), start, size= ); } =20 static void arm_smmu_mm_release(struct mmu_notifier *mn, struct mm_struct = *mm) @@ -247,10 +247,10 @@ static void arm_smmu_mm_release(struct mmu_notifier *= mn, struct mm_struct *mm) * DMA may still be running. Keep the cd valid to avoid C_BAD_CD events, * but disable translation. */ - arm_smmu_write_ctx_desc(smmu_domain, mm->pasid, &quiet_cd); + arm_smmu_write_ctx_desc(smmu_domain, mm_get_enqcmd_pasid(mm), &quiet_cd); =20 arm_smmu_tlb_inv_asid(smmu_domain->smmu, smmu_mn->cd->asid); - arm_smmu_atc_inv_domain(smmu_domain, mm->pasid, 0, 0); + arm_smmu_atc_inv_domain(smmu_domain, mm_get_enqcmd_pasid(mm), 0, 0); =20 smmu_mn->cleared =3D true; mutex_unlock(&sva_lock); @@ -304,7 +304,7 @@ arm_smmu_mmu_notifier_get(struct arm_smmu_domain *smmu_= domain, goto err_free_cd; } =20 - ret =3D arm_smmu_write_ctx_desc(smmu_domain, mm->pasid, cd); + ret =3D arm_smmu_write_ctx_desc(smmu_domain, mm_get_enqcmd_pasid(mm), cd); if (ret) goto err_put_notifier; =20 @@ -329,7 +329,7 @@ static void arm_smmu_mmu_notifier_put(struct arm_smmu_m= mu_notifier *smmu_mn) return; =20 list_del(&smmu_mn->list); - arm_smmu_write_ctx_desc(smmu_domain, mm->pasid, NULL); + arm_smmu_write_ctx_desc(smmu_domain, mm_get_enqcmd_pasid(mm), NULL); =20 /* * If we went through clear(), we've already invalidated, and no @@ -337,7 +337,7 @@ static void arm_smmu_mmu_notifier_put(struct arm_smmu_m= mu_notifier *smmu_mn) */ if (!smmu_mn->cleared) { arm_smmu_tlb_inv_asid(smmu_domain->smmu, cd->asid); - arm_smmu_atc_inv_domain(smmu_domain, mm->pasid, 0, 0); + arm_smmu_atc_inv_domain(smmu_domain, mm_get_enqcmd_pasid(mm), 0, 0); } =20 /* Frees smmu_mn */ diff --git a/drivers/iommu/iommu-sva.c b/drivers/iommu/iommu-sva.c index b78671a8a914..4a2f5699747f 100644 --- a/drivers/iommu/iommu-sva.c +++ b/drivers/iommu/iommu-sva.c @@ -141,7 +141,7 @@ u32 iommu_sva_get_pasid(struct iommu_sva *handle) { struct iommu_domain *domain =3D handle->domain; =20 - return domain->mm->pasid; + return mm_get_enqcmd_pasid(domain->mm); } EXPORT_SYMBOL_GPL(iommu_sva_get_pasid); =20 diff --git a/include/linux/iommu.h b/include/linux/iommu.h index c50a769d569a..074b98f9e5dc 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -1189,6 +1189,12 @@ static inline bool mm_valid_pasid(struct mm_struct *= mm) { return mm->pasid !=3D IOMMU_PASID_INVALID; } + +static inline u32 mm_get_enqcmd_pasid(struct mm_struct *mm) +{ + return mm->pasid; +} + void mm_pasid_drop(struct mm_struct *mm); struct iommu_sva *iommu_sva_bind_device(struct device *dev, struct mm_struct *mm); @@ -1211,6 +1217,12 @@ static inline u32 iommu_sva_get_pasid(struct iommu_s= va *handle) } static inline void mm_pasid_init(struct mm_struct *mm) {} static inline bool mm_valid_pasid(struct mm_struct *mm) { return false; } + +static inline u32 mm_get_enqcmd_pasid(struct mm_struct *mm) +{ + return IOMMU_PASID_INVALID; +} + static inline void mm_pasid_drop(struct mm_struct *mm) {} #endif /* CONFIG_IOMMU_SVA */ =20 --=20 2.39.3