From nobody Fri Jan 2 00:10:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14962CDB483 for ; Tue, 17 Oct 2023 20:45:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344283AbjJQUp2 (ORCPT ); Tue, 17 Oct 2023 16:45:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56230 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235093AbjJQUpW (ORCPT ); Tue, 17 Oct 2023 16:45:22 -0400 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7E71BFF for ; Tue, 17 Oct 2023 13:45:20 -0700 (PDT) Received: by mail-pj1-x1030.google.com with SMTP id 98e67ed59e1d1-27cefb5ae1fso3582511a91.3 for ; Tue, 17 Oct 2023 13:45:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1697575520; x=1698180320; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=GEp58o5jHhf4WpbbQN22nWQx0p8/zKOYMNnof7eHdFk=; b=XyUH0exzrO3kCOpB6aFZBQRuV8LtEBstVdbWewp2MZTCHgkZ3KJpDnVWzwUt2xuWm/ yMOYekAZLAofK9S9AP5V0n0IUUFjFfzp2zGCaCkjYQhU4vP9581z6bEBEy5kIbcV9tWA yZthFyBkEpuSv2eCzXmxBMPWnFG0ZnN+ijify2YXn/k9gi4nm3YkZU16CNSIVh2Et9wm fOgYHEPECBS8QmD6M3yaSMmpfTU96H8RN5lg9cPRNOkjnaj8hAWbTEBBevicu2awPOLX EibzkbA64gGJRZJ2DCuDpvHolRX8ON0K6TXgxxjRSVeLEf+aYHtWN5gWfYYMJSWP35w9 OXaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697575520; x=1698180320; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GEp58o5jHhf4WpbbQN22nWQx0p8/zKOYMNnof7eHdFk=; b=m0IHsrOq+G00z+7XTMHo2ZYOUOJfKScq6WpTw2AadMoib334G/mXe+84ya6eCrDr5V gS95g3UFwuhueW8+R1vxDnt3zB5aW55fLf+4hyT8ryauX2qaL1TV/OMMUwNQb7Kj56IG JlHMhQFoaRfKyaCng8eLNfEyp8AHsctVEgqiWatn1n8P6S3oeLuemeivKbmRshRao6m3 Zd7D6wfihpArPRFJLw2/V2rxRJs0rnu8icMNZVicKfU2n2YFj5/OAzRRhcrNBf0hutgV MxaaaIPBqvZm/rcZ4tq/dtSOYshPx/rL4Uj7LINqE765OK+TI+3DaT+PZwvSoVCAPUUV N1cw== X-Gm-Message-State: AOJu0YyHIqYBwwhZkFBo4xhXK9VZIPEM27zdcrXBQSWOCRnPp/8IHt4q 3Y0o+EpL53AOn4tH7hjVR1cdjA== X-Google-Smtp-Source: AGHT+IFp9pFfIQEXNfCKkC3vHINl59IS1m8/a0WaUgexa1L64KCFZa0B5E8Uxe+pqG+nf7JdZ+AKhg== X-Received: by 2002:a17:90a:800c:b0:27d:5ef6:2862 with SMTP id b12-20020a17090a800c00b0027d5ef62862mr3354510pjn.13.1697575519879; Tue, 17 Oct 2023 13:45:19 -0700 (PDT) Received: from [127.0.1.1] ([2601:1c2:1800:f680:51d6:dcd6:63ef:52e9]) by smtp.gmail.com with ESMTPSA id w3-20020a17090a6b8300b0027b168cb011sm1906553pjj.56.2023.10.17.13.45.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 13:45:19 -0700 (PDT) From: Drew Fustini Date: Tue, 17 Oct 2023 13:43:47 -0700 Subject: [PATCH v2 1/7] dt-bindings: mmc: sdhci-of-dwcmhsc: Add T-Head TH1520 support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231017-th1520-mmc-v2-1-4678c8cc4048@baylibre.com> References: <20231017-th1520-mmc-v2-0-4678c8cc4048@baylibre.com> In-Reply-To: <20231017-th1520-mmc-v2-0-4678c8cc4048@baylibre.com> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jisheng Zhang , Adrian Hunter , Guo Ren , Fu Wei , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley Cc: Robert Nelson , Jason Kridner , Xi Ruoyao , Han Gao , Icenowy Zheng , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Drew Fustini X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1697575515; l=752; i=dfustini@baylibre.com; s=20230430; h=from:subject:message-id; bh=N4XyeVof9hR52mLfjwIJ/Ek5oPrydhGBm0Gy7EtJsFw=; b=+Ob+gpIgFt2gGa83X788FD8dq4mXWEM1rO3tlCBf2HwM5l8WNPiB40d3qp2Xd4waLgjW94rAb nu/B5dApi0JB/KK0nc1z5V5Bw3NqrLUU4ThP/xnLvrDfw+Z49RjOadw X-Developer-Key: i=dfustini@baylibre.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add compatible value for the T-Head TH1520 dwcmshc controller. Signed-off-by: Drew Fustini Acked-by: Guo Ren Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml = b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml index a43eb837f8da..42804d955293 100644 --- a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml @@ -19,6 +19,7 @@ properties: - rockchip,rk3568-dwcmshc - rockchip,rk3588-dwcmshc - snps,dwcmshc-sdhci + - thead,th1520-dwcmshc =20 reg: maxItems: 1 --=20 2.34.1 From nobody Fri Jan 2 00:10:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27CBECDB482 for ; Tue, 17 Oct 2023 20:45:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344426AbjJQUpc (ORCPT ); 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Tue, 17 Oct 2023 13:45:21 -0700 (PDT) From: Drew Fustini Date: Tue, 17 Oct 2023 13:43:48 -0700 Subject: [PATCH v2 2/7] mmc: sdhci: add __sdhci_execute_tuning() to header MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231017-th1520-mmc-v2-2-4678c8cc4048@baylibre.com> References: <20231017-th1520-mmc-v2-0-4678c8cc4048@baylibre.com> In-Reply-To: <20231017-th1520-mmc-v2-0-4678c8cc4048@baylibre.com> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jisheng Zhang , Adrian Hunter , Guo Ren , Fu Wei , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley Cc: Robert Nelson , Jason Kridner , Xi Ruoyao , Han Gao , Icenowy Zheng , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Drew Fustini X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1697575515; l=2057; i=dfustini@baylibre.com; s=20230430; h=from:subject:message-id; bh=O0pl7kPWnknxTc+1ciCix3vi2PmSyK8UTzQqhv8rZP0=; b=c6MNN19+LVa+YXw8BVIwdqx0H9tnKqK0U5fbdhUSgz7AcvpDWhHyDwOlUig3M0ucf+4RwI6E4 UqlGbcLac7HAbSsrCd3MB60tM6ZE9sf10n3goXEu6+eNFsYQiMZJghN X-Developer-Key: i=dfustini@baylibre.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Expose __sdhci_execute_tuning() so that it can be called from the mmc host controller drivers. In the sdhci-of-dwcmshc driver, sdhci_dwcmshc_th1520_ops sets platform_execute_tuning to th1520_execute_tuning(). That function has to manipulate phy registers before tuning can be performed. To avoid copying the code verbatim from __sdhci_execute_tuning() into th1520_execute_tuning(), make it possible for __sdhci_execute_tuning() to be called from sdhci-of-dwcmshc. Signed-off-by: Drew Fustini --- drivers/mmc/host/sdhci.c | 3 ++- drivers/mmc/host/sdhci.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index ff41aa56564e..c79f73459915 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -2841,7 +2841,7 @@ void sdhci_send_tuning(struct sdhci_host *host, u32 o= pcode) } EXPORT_SYMBOL_GPL(sdhci_send_tuning); =20 -static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) +int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) { int i; =20 @@ -2879,6 +2879,7 @@ static int __sdhci_execute_tuning(struct sdhci_host *= host, u32 opcode) sdhci_reset_tuning(host); return -EAGAIN; } +EXPORT_SYMBOL_GPL(__sdhci_execute_tuning); =20 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) { diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index f219bdea8f28..a20864fc0641 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -793,6 +793,7 @@ void sdhci_set_bus_width(struct sdhci_host *host, int w= idth); void sdhci_reset(struct sdhci_host *host, u8 mask); void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); +int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode); void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios); --=20 2.34.1 From nobody Fri Jan 2 00:10:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 230FFCDB485 for ; Tue, 17 Oct 2023 20:45:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344494AbjJQUpp (ORCPT ); Tue, 17 Oct 2023 16:45:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33048 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344448AbjJQUph (ORCPT ); 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Tue, 17 Oct 2023 13:45:24 -0700 (PDT) From: Drew Fustini Date: Tue, 17 Oct 2023 13:43:49 -0700 Subject: [PATCH v2 3/7] mmc: sdhci-of-dwcmshc: Add support for T-Head TH1520 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231017-th1520-mmc-v2-3-4678c8cc4048@baylibre.com> References: <20231017-th1520-mmc-v2-0-4678c8cc4048@baylibre.com> In-Reply-To: <20231017-th1520-mmc-v2-0-4678c8cc4048@baylibre.com> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jisheng Zhang , Adrian Hunter , Guo Ren , Fu Wei , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley Cc: Robert Nelson , Jason Kridner , Xi Ruoyao , Han Gao , Icenowy Zheng , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Drew Fustini X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1697575515; l=17079; i=dfustini@baylibre.com; s=20230430; h=from:subject:message-id; bh=vv/AIEuNFqLsZz9JcRtq2XC0MaJKKMJSyowi1Hzu1SE=; b=RLo9jDcqXN1sLkkUnNvydK2xg/jjS4hi2QxeKq8WT0X/E/x4ytK1M2GbDGZGyHe+cOvdm6a6+ I2KbkIN3EMLDvKrvf3Fv8cd9ElZ8YwL2KO9svP/A3XwQiJSXcupk+El X-Developer-Key: i=dfustini@baylibre.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for the mmc controller in the T-Head TH1520 with the new compatible "thead,th1520-dwcmshc". Implement custom sdhci_ops for set_uhs_signaling, reset, voltage_switch, and platform_execute_tuning. Signed-off-by: Drew Fustini --- drivers/mmc/host/sdhci-of-dwcmshc.c | 358 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 358 insertions(+) diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-o= f-dwcmshc.c index 3a3bae6948a8..88ed0937c4e9 100644 --- a/drivers/mmc/host/sdhci-of-dwcmshc.c +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c @@ -8,6 +8,7 @@ */ =20 #include +#include #include #include #include @@ -35,6 +36,21 @@ #define DWCMSHC_CARD_IS_EMMC BIT(0) #define DWCMSHC_ENHANCED_STROBE BIT(8) #define DWCMSHC_EMMC_ATCTRL 0x40 +/* Tuning and auto-tuning fields in AT_CTRL_R control register */ +#define AT_CTRL_AT_EN BIT(0) /* autotuning is enabled */ +#define AT_CTRL_CI_SEL BIT(1) /* interval to drive center phase select */ +#define AT_CTRL_SWIN_TH_EN BIT(2) /* sampling window threshold enable */ +#define AT_CTRL_RPT_TUNE_ERR BIT(3) /* enable reporting framing errors */ +#define AT_CTRL_SW_TUNE_EN BIT(4) /* enable software managed tuning */ +#define AT_CTRL_WIN_EDGE_SEL_MASK GENMASK(11, 8) /* bits [11:8] */ +#define AT_CTRL_WIN_EDGE_SEL 0xf /* sampling window edge select */ +#define AT_CTRL_TUNE_CLK_STOP_EN BIT(16) /* clocks stopped during phase co= de change */ +#define AT_CTRL_PRE_CHANGE_DLY_MASK GENMASK(18, 17) /* bits [18:17] */ +#define AT_CTRL_PRE_CHANGE_DLY 0x1 /* 2-cycle latency */ +#define AT_CTRL_POST_CHANGE_DLY_MASK GENMASK(20, 19) /* bits [20:19] */ +#define AT_CTRL_POST_CHANGE_DLY 0x3 /* 4-cycle latency */ +#define AT_CTRL_SWIN_TH_VAL_MASK GENMASK(31, 24) /* bits [31:24] */ +#define AT_CTRL_SWIN_TH_VAL 0x9 /* sampling window threshold */ =20 /* Rockchip specific Registers */ #define DWCMSHC_EMMC_DLL_CTRL 0x800 @@ -72,6 +88,82 @@ (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) =3D=3D 0)) #define RK35xx_MAX_CLKS 3 =20 +/* PHY register area pointer */ +#define DWC_MSHC_PTR_PHY_R 0x300 + +/* PHY general configuration */ +#define PHY_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x00) +#define PHY_CNFG_RSTN_DEASSERT 0x1 /* Deassert PHY reset */ +#define PHY_CNFG_PAD_SP_MASK GENMASK(19, 16) /* bits [19:16] */ +#define PHY_CNFG_PAD_SP 0x0c /* PMOS TX drive strength */ +#define PHY_CNFG_PAD_SN_MASK GENMASK(23, 20) /* bits [23:20] */ +#define PHY_CNFG_PAD_SN 0x0c /* NMOS TX drive strength */ + +/* PHY command/response pad settings */ +#define PHY_CMDPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x04) + +/* PHY data pad settings */ +#define PHY_DATAPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x06) + +/* PHY clock pad settings */ +#define PHY_CLKPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x08) + +/* PHY strobe pad settings */ +#define PHY_STBPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0a) + +/* PHY reset pad settings */ +#define PHY_RSTNPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0c) + +/* Bitfields are common for all pad settings */ +#define PHY_PAD_RXSEL_1V8 0x1 /* Receiver type select for 1.8V */ +#define PHY_PAD_RXSEL_3V3 0x2 /* Receiver type select for 3.3V */ + +#define PHY_PAD_WEAKPULL_MASK GENMASK(4, 3) /* bits [4:3] */ +#define PHY_PAD_WEAKPULL_PULLUP 0x1 /* Weak pull down enabled */ +#define PHY_PAD_WEAKPULL_PULLDOWN 0x2 /* Weak pull down enabled */ + +#define PHY_PAD_TXSLEW_CTRL_P_MASK GENMASK(8, 5) /* bits [8:5] */ +#define PHY_PAD_TXSLEW_CTRL_P 0x3 /* Slew control for P-Type pad TX */ +#define PHY_PAD_TXSLEW_CTRL_N_MASK GENMASK(12, 9) /* bits [12:9] */ +#define PHY_PAD_TXSLEW_CTRL_N 0x3 /* Slew control for N-Type pad TX */ + +/* PHY CLK delay line settings */ +#define PHY_SDCLKDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x1d) +#define PHY_SDCLKDL_CNFG_UPDATE BIT(4) /* set before writing to SDCLKDL_DC= */ + +/* PHY CLK delay line delay code */ +#define PHY_SDCLKDL_DC_R (DWC_MSHC_PTR_PHY_R + 0x1e) +#define PHY_SDCLKDL_DC_INITIAL 0x40 /* initial delay code */ +#define PHY_SDCLKDL_DC_DEFAULT 0x32 /* default delay code */ +#define PHY_SDCLKDL_DC_HS400 0x18 /* delay code for HS400 mode */ + +/* PHY drift_cclk_rx delay line configuration setting */ +#define PHY_ATDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x21) +#define PHY_ATDL_CNFG_INPSEL_MASK GENMASK(3, 2) /* bits [3:2] */ +#define PHY_ATDL_CNFG_INPSEL 0x3 /* delay line input source */ + +/* PHY DLL control settings */ +#define PHY_DLL_CTRL_R (DWC_MSHC_PTR_PHY_R + 0x24) +#define PHY_DLL_CTRL_DISABLE 0x0 /* PHY DLL is enabled */ +#define PHY_DLL_CTRL_ENABLE 0x1 /* PHY DLL is disabled */ + +/* PHY DLL configuration register 1 */ +#define PHY_DLL_CNFG1_R (DWC_MSHC_PTR_PHY_R + 0x25) +#define PHY_DLL_CNFG1_SLVDLY_MASK GENMASK(5, 4) /* bits [5:4] */ +#define PHY_DLL_CNFG1_SLVDLY 0x2 /* DLL slave update delay input */ +#define PHY_DLL_CNFG1_WAITCYCLE 0x5 /* DLL wait cycle input */ + +/* PHY DLL configuration register 2 */ +#define PHY_DLL_CNFG2_R (DWC_MSHC_PTR_PHY_R + 0x26) +#define PHY_DLL_CNFG2_JUMPSTEP 0xa /* DLL jump step input */ + +/* PHY DLL master and slave delay line configuration settings */ +#define PHY_DLLDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x28) +#define PHY_DLLDL_CNFG_SLV_INPSEL_MASK GENMASK(6, 5) /* bits [6:5] */ +#define PHY_DLLDL_CNFG_SLV_INPSEL 0x3 /* clock source select for slave DL = */ + +#define FLAG_IO_FIXED_1V8 BIT(0) + #define BOUNDARY_OK(addr, len) \ ((addr | (SZ_128M - 1)) =3D=3D ((addr + len - 1) | (SZ_128M - 1))) =20 @@ -92,6 +184,8 @@ struct dwcmshc_priv { struct clk *bus_clk; int vendor_specific_area1; /* P_VENDOR_SPECIFIC_AREA reg */ void *priv; /* pointer to SoC private stuff */ + u16 delay_line; + u16 flags; }; =20 /* @@ -157,6 +251,129 @@ static void dwcmshc_request(struct mmc_host *mmc, str= uct mmc_request *mrq) sdhci_request(mmc, mrq); } =20 +static void th1520_phy_1_8v_init(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct dwcmshc_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + u32 val; + + if (!priv) + return; + + /* deassert phy reset & set tx drive strength */ + val =3D PHY_CNFG_RSTN_DEASSERT; + val |=3D FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP); + val |=3D FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN); + sdhci_writel(host, val, PHY_CNFG_R); + + /* disable delay line */ + sdhci_writeb(host, PHY_SDCLKDL_CNFG_UPDATE, PHY_SDCLKDL_CNFG_R); + + /* set delay line */ + sdhci_writeb(host, priv->delay_line, PHY_SDCLKDL_DC_R); + sdhci_writeb(host, PHY_DLL_CNFG2_JUMPSTEP, PHY_DLL_CNFG2_R); + + /* enable delay lane */ + val =3D sdhci_readb(host, PHY_SDCLKDL_CNFG_R); + val &=3D ~(PHY_SDCLKDL_CNFG_UPDATE); + sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R); + + /* configure phy pads */ + val =3D PHY_PAD_RXSEL_1V8; + val |=3D FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP); + val |=3D FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); + val |=3D FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); + sdhci_writew(host, val, PHY_CMDPAD_CNFG_R); + sdhci_writew(host, val, PHY_DATAPAD_CNFG_R); + sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R); + + val =3D FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); + val |=3D FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); + sdhci_writew(host, val, PHY_CLKPAD_CNFG_R); + + val =3D PHY_PAD_RXSEL_1V8; + val |=3D FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN); + val |=3D FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); + val |=3D FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); + sdhci_writew(host, val, PHY_STBPAD_CNFG_R); + + /* enable data strobe mode */ + sdhci_writeb(host, FIELD_PREP(PHY_DLLDL_CNFG_SLV_INPSEL_MASK, PHY_DLLDL_C= NFG_SLV_INPSEL), + PHY_DLLDL_CNFG_R); + + /* enable phy dll */ + sdhci_writeb(host, PHY_DLL_CTRL_ENABLE, PHY_DLL_CTRL_R); +} + +static void th1520_phy_3_3v_init(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct dwcmshc_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + u32 val; + + /* deassert phy reset & set tx drive strength */ + val =3D PHY_CNFG_RSTN_DEASSERT; + val |=3D FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP); + val |=3D FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN); + sdhci_writel(host, val, PHY_CNFG_R); + + /* disable delay line */ + sdhci_writeb(host, PHY_SDCLKDL_CNFG_UPDATE, PHY_SDCLKDL_CNFG_R); + + /* set delay line */ + sdhci_writeb(host, priv->delay_line, PHY_SDCLKDL_DC_R); + sdhci_writeb(host, PHY_DLL_CNFG2_JUMPSTEP, PHY_DLL_CNFG2_R); + + /* enable delay lane */ + val =3D sdhci_readb(host, PHY_SDCLKDL_CNFG_R); + val &=3D ~(PHY_SDCLKDL_CNFG_UPDATE); + sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R); + + /* configure phy pads */ + val =3D PHY_PAD_RXSEL_3V3; + val |=3D FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP); + val |=3D FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); + val |=3D FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); + sdhci_writew(host, val, PHY_CMDPAD_CNFG_R); + sdhci_writew(host, val, PHY_DATAPAD_CNFG_R); + sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R); + + val =3D FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); + val |=3D FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); + sdhci_writew(host, val, PHY_CLKPAD_CNFG_R); + + val =3D PHY_PAD_RXSEL_3V3; + val |=3D FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN); + val |=3D FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); + val |=3D FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); + sdhci_writew(host, val, PHY_STBPAD_CNFG_R); + + /* enable phy dll */ + sdhci_writeb(host, PHY_DLL_CTRL_ENABLE, PHY_DLL_CTRL_R); +} + +static void th1520_sdhci_set_phy(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct dwcmshc_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + u16 emmc_ctrl; + + /* Before power on, set PHY configs */ + if (priv->flags & FLAG_IO_FIXED_1V8) + th1520_phy_1_8v_init(host); + else + th1520_phy_3_3v_init(host); + + if (host->mmc->caps & MMC_CAP_NONREMOVABLE) { + emmc_ctrl =3D sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EM= MC_CONTROL); + emmc_ctrl |=3D DWCMSHC_CARD_IS_EMMC; + sdhci_writew(host, emmc_ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC= _CONTROL); + } + + sdhci_writeb(host, FIELD_PREP(PHY_DLL_CNFG1_SLVDLY_MASK, PHY_DLL_CNFG1_SL= VDLY) | + PHY_DLL_CNFG1_WAITCYCLE, PHY_DLL_CNFG1_R); +} + static void dwcmshc_set_uhs_signaling(struct sdhci_host *host, unsigned int timing) { @@ -189,9 +406,26 @@ static void dwcmshc_set_uhs_signaling(struct sdhci_hos= t *host, ctrl_2 |=3D DWCMSHC_CTRL_HS400; } =20 + if (priv->flags & FLAG_IO_FIXED_1V8) + ctrl_2 |=3D SDHCI_CTRL_VDD_180; sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); } =20 +static void th1520_set_uhs_signaling(struct sdhci_host *host, + unsigned int timing) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct dwcmshc_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + + dwcmshc_set_uhs_signaling(host, timing); + if (timing =3D=3D MMC_TIMING_MMC_HS400) { + priv->delay_line =3D PHY_SDCLKDL_DC_HS400; + th1520_sdhci_set_phy(host); + } else { + sdhci_writeb(host, 0, PHY_DLLDL_CNFG_R); + } +} + static void dwcmshc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios) { @@ -338,6 +572,85 @@ static void rk35xx_sdhci_reset(struct sdhci_host *host= , u8 mask) sdhci_reset(host, mask); } =20 +static int th1520_execute_tuning(struct sdhci_host *host, u32 opcode) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct dwcmshc_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + u32 val =3D 0; + + if (host->flags & SDHCI_HS400_TUNING) + return 0; + + sdhci_writeb(host, FIELD_PREP(PHY_ATDL_CNFG_INPSEL_MASK, PHY_ATDL_CNFG_IN= PSEL), + PHY_ATDL_CNFG_R); + val =3D sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCT= RL); + + /* + * configure tuning settings: + * - center phase select code driven in block gap interval + * - disable reporting of framing errors + * - disable software managed tuning + * - disable user selection of sampling window edges, + * instead tuning calculated edges are used + */ + val &=3D ~(AT_CTRL_CI_SEL | AT_CTRL_RPT_TUNE_ERR | AT_CTRL_SW_TUNE_EN | + FIELD_PREP(AT_CTRL_WIN_EDGE_SEL_MASK, AT_CTRL_WIN_EDGE_SEL)); + + /* + * configure tuning settings: + * - enable auto-tuning + * - enable sampling window threshold + * - stop clocks during phase code change + * - set max latency in cycles between tx and rx clocks + * - set max latency in cycles to switch output phase + * - set max sampling window threshold value + */ + val |=3D AT_CTRL_AT_EN | AT_CTRL_SWIN_TH_EN | AT_CTRL_TUNE_CLK_STOP_EN; + val |=3D FIELD_PREP(AT_CTRL_PRE_CHANGE_DLY_MASK, AT_CTRL_PRE_CHANGE_DLY); + val |=3D FIELD_PREP(AT_CTRL_POST_CHANGE_DLY_MASK, AT_CTRL_POST_CHANGE_DLY= ); + val |=3D FIELD_PREP(AT_CTRL_SWIN_TH_VAL_MASK, AT_CTRL_SWIN_TH_VAL); + + sdhci_writel(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL= ); + val =3D sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCT= RL); + + /* check if is possible to enable auto-tuning */ + if (!(val & AT_CTRL_AT_EN)) { + dev_err(mmc_dev(host->mmc), "failed to enable auto tuning\n"); + return -EIO; + } + + /* perform tuning */ + sdhci_start_tuning(host); + host->tuning_err =3D __sdhci_execute_tuning(host, opcode); + if (host->tuning_err) { + /* disable auto-tuning upon tuning error */ + val &=3D ~AT_CTRL_AT_EN; + sdhci_writel(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTR= L); + dev_err(mmc_dev(host->mmc), "tuning failed: %d\n", host->tuning_err); + return -EIO; + } + sdhci_end_tuning(host); + + return 0; +} + +static void th1520_sdhci_reset(struct sdhci_host *host, u8 mask) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct dwcmshc_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + u16 ctrl_2; + + sdhci_reset(host, mask); + + if (priv->flags & FLAG_IO_FIXED_1V8) { + ctrl_2 =3D sdhci_readw(host, SDHCI_HOST_CONTROL2); + if (!(ctrl_2 & SDHCI_CTRL_VDD_180)) { + ctrl_2 |=3D SDHCI_CTRL_VDD_180; + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); + } + } +} + static const struct sdhci_ops sdhci_dwcmshc_ops =3D { .set_clock =3D sdhci_set_clock, .set_bus_width =3D sdhci_set_bus_width, @@ -356,6 +669,17 @@ static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops= =3D { .adma_write_desc =3D dwcmshc_adma_write_desc, }; =20 +static const struct sdhci_ops sdhci_dwcmshc_th1520_ops =3D { + .set_clock =3D sdhci_set_clock, + .set_bus_width =3D sdhci_set_bus_width, + .set_uhs_signaling =3D th1520_set_uhs_signaling, + .get_max_clock =3D dwcmshc_get_max_clock, + .reset =3D th1520_sdhci_reset, + .adma_write_desc =3D dwcmshc_adma_write_desc, + .voltage_switch =3D th1520_phy_1_8v_init, + .platform_execute_tuning =3D &th1520_execute_tuning, +}; + static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata =3D { .ops =3D &sdhci_dwcmshc_ops, .quirks =3D SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, @@ -379,6 +703,12 @@ static const struct sdhci_pltfm_data sdhci_dwcmshc_rk3= 5xx_pdata =3D { SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, }; =20 +static const struct sdhci_pltfm_data sdhci_dwcmshc_th1520_pdata =3D { + .ops =3D &sdhci_dwcmshc_th1520_ops, + .quirks =3D SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, + .quirks2 =3D SDHCI_QUIRK2_PRESET_VALUE_BROKEN, +}; + static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_pri= v *dwc_priv) { int err; @@ -447,6 +777,10 @@ static const struct of_device_id sdhci_dwcmshc_dt_ids[= ] =3D { .compatible =3D "snps,dwcmshc-sdhci", .data =3D &sdhci_dwcmshc_pdata, }, + { + .compatible =3D "thead,th1520-dwcmshc", + .data =3D &sdhci_dwcmshc_th1520_pdata, + }, {}, }; MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids); @@ -542,6 +876,30 @@ static int dwcmshc_probe(struct platform_device *pdev) goto err_clk; } =20 + if (pltfm_data =3D=3D &sdhci_dwcmshc_th1520_pdata) { + priv->delay_line =3D PHY_SDCLKDL_DC_DEFAULT; + + if ((device_property_read_bool(dev, "mmc-ddr-1_8v")) | + (device_property_read_bool(dev, "mmc-hs200-1_8v")) | + (device_property_read_bool(dev, "mmc-hs400-1_8v"))) + priv->flags |=3D FLAG_IO_FIXED_1V8; + else + priv->flags &=3D ~FLAG_IO_FIXED_1V8; + + /* + * start_signal_voltage_switch() will try 3.3V first + * then 1.8V. Use SDHCI_SIGNALING_180 ranther than + * SDHCI_SIGNALING_330 to avoid setting voltage to 3.3V + * in sdhci_start_signal_voltage_switch(). + */ + if (priv->flags & FLAG_IO_FIXED_1V8) { + host->flags &=3D ~SDHCI_SIGNALING_330; + host->flags |=3D SDHCI_SIGNALING_180; + } + + sdhci_enable_v4_mode(host); + } + #ifdef CONFIG_ACPI if (pltfm_data =3D=3D &sdhci_dwcmshc_bf3_pdata) sdhci_enable_v4_mode(host); --=20 2.34.1 From nobody Fri Jan 2 00:10:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F1EDCDB482 for ; Tue, 17 Oct 2023 20:45:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344506AbjJQUpm (ORCPT ); Tue, 17 Oct 2023 16:45:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33038 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344447AbjJQUph (ORCPT ); Tue, 17 Oct 2023 16:45:37 -0400 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D06B101 for ; Tue, 17 Oct 2023 13:45:27 -0700 (PDT) Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-1c888b3a25aso39596985ad.0 for ; Tue, 17 Oct 2023 13:45:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1697575526; x=1698180326; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=2BmxulcCPkSniZYdQWfk9xRMqLpea0NZ1oqzxL0OgN4=; b=KGeC/cFx0Q/6/SnPUIHq9+SIEAtEu9QtHJKWj5UWX8LXd0Nh3G0KoZevUYMm5qw32p nLDClYH4stj1c97CHl3bLTLtYX0hh/HNo4C/iL4/AINH96jts5CDbeGDX4MGqxfv2d1S 1dNMgcoM1McKaz7LqzjYQCGSOOMp6ghx9Ib9xfGmh1TQXu+QnL2LuttgxdXujF7/7DUI n8EMUYoQWStjXAHLASctILAmVf25d/W5MEn1Da2cqRfh5vQeDElrD1O0q+2DbuXdeRdW pENXat6mDIklDzqifBsfcQRv/APIBbE5nKczxf0q9Gbe75KCBRuEB+4HR1/b8jZfS3Vv Eacg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697575526; x=1698180326; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2BmxulcCPkSniZYdQWfk9xRMqLpea0NZ1oqzxL0OgN4=; b=Xll3hnT6eGWKURLo+CBqKIoAfVNG5+mMshO3P2/xXd7EfZ+nQT3L7yh7TQ0/pJneRP 1Lr78W2dAIhnB0UTAJD6EUIxo5Ou6UyZIU0GIJ9VT5HM1z+m3QVtoDfSjO9awQYhbVlU Z3dRSYcnk86IBFWGTIY6t7dPCi5N4CFbLHXKTt+UyrBgahk0yDwT53BAI90S+cHx0tKh i2mwo28n3rg6HJaGPK/83jf4YP4yYgoGbzlEyy4hTbUnBOTwg0dDiTMWdXlAjtOdZfZX TkWJAgj24/fOXc1zEXbG6zTRZoR4si+3vq5teVZVdkf93HypjH9JzJ4J8lBOai7YI1Zf MfTQ== X-Gm-Message-State: AOJu0YxwO+dj3tpbJM8jHLAnZYyfjmmSt87r7x7PUsD348LUOVPhW0cE pazf5OJqcT7fSLxfn+o+aG5O6w== X-Google-Smtp-Source: AGHT+IEzzNmgIZ8zis35YXLxguwj5DngT1258LdDb627amXgp9c4UUvS9r5IPBtrYpPwBsm5Y/h7PQ== X-Received: by 2002:a17:90b:2501:b0:27d:7666:9596 with SMTP id ns1-20020a17090b250100b0027d76669596mr3072562pjb.11.1697575526448; Tue, 17 Oct 2023 13:45:26 -0700 (PDT) Received: from [127.0.1.1] ([2601:1c2:1800:f680:51d6:dcd6:63ef:52e9]) by smtp.gmail.com with ESMTPSA id w3-20020a17090a6b8300b0027b168cb011sm1906553pjj.56.2023.10.17.13.45.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 13:45:26 -0700 (PDT) From: Drew Fustini Date: Tue, 17 Oct 2023 13:43:50 -0700 Subject: [PATCH v2 4/7] riscv: defconfig: Enable mmc and dma drivers for T-Head TH1520 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231017-th1520-mmc-v2-4-4678c8cc4048@baylibre.com> References: <20231017-th1520-mmc-v2-0-4678c8cc4048@baylibre.com> In-Reply-To: <20231017-th1520-mmc-v2-0-4678c8cc4048@baylibre.com> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jisheng Zhang , Adrian Hunter , Guo Ren , Fu Wei , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley Cc: Robert Nelson , Jason Kridner , Xi Ruoyao , Han Gao , Icenowy Zheng , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Drew Fustini X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1697575515; l=873; i=dfustini@baylibre.com; s=20230430; h=from:subject:message-id; bh=1b6E7IcYPcGUX3CsWI9slySNkcpgVBWsbFODn/9h1s4=; b=35sRMPw4jZ4wGRrdg+DGS4oNB75lU2OE/PvljPF/GCaThFBcZGUoTrJbIi4kNmE714EcWRq9I FUKF7Fv4YiNB82HJ4GGaDCbqEs6wY44RXyc+Euh+2yVdj6gHQDyUizS X-Developer-Key: i=dfustini@baylibre.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Enable the mmc controller driver and dma controller driver needed for T-Head TH1520 based boards, like the LicheePi 4A and BeagleV-Ahead, to boot from eMMC storage. Signed-off-by: Drew Fustini Reviewed-by: Guo Ren --- arch/riscv/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index ab86ec3b9eab..c5a8583236d0 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -168,12 +168,14 @@ CONFIG_MMC=3Dy CONFIG_MMC_SDHCI=3Dy CONFIG_MMC_SDHCI_PLTFM=3Dy CONFIG_MMC_SDHCI_CADENCE=3Dy +CONFIG_MMC_SDHCI_OF_DWCMSHC=3Dy CONFIG_MMC_SPI=3Dy CONFIG_MMC_SUNXI=3Dy CONFIG_RTC_CLASS=3Dy CONFIG_RTC_DRV_SUN6I=3Dy CONFIG_DMADEVICES=3Dy CONFIG_DMA_SUN6I=3Dm +CONFIG_DW_AXI_DMAC=3Dy CONFIG_VIRTIO_PCI=3Dy CONFIG_VIRTIO_BALLOON=3Dy CONFIG_VIRTIO_INPUT=3Dy --=20 2.34.1 From nobody Fri Jan 2 00:10:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9276CDB482 for ; Tue, 17 Oct 2023 20:45:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232228AbjJQUpw (ORCPT ); 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Tue, 17 Oct 2023 13:45:28 -0700 (PDT) From: Drew Fustini Date: Tue, 17 Oct 2023 13:43:51 -0700 Subject: [PATCH v2 5/7] riscv: dts: thead: Add TH1520 mmc controller and sdhci clock MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231017-th1520-mmc-v2-5-4678c8cc4048@baylibre.com> References: <20231017-th1520-mmc-v2-0-4678c8cc4048@baylibre.com> In-Reply-To: <20231017-th1520-mmc-v2-0-4678c8cc4048@baylibre.com> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jisheng Zhang , Adrian Hunter , Guo Ren , Fu Wei , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley Cc: Robert Nelson , Jason Kridner , Xi Ruoyao , Han Gao , Icenowy Zheng , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Drew Fustini X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1697575515; l=1256; i=dfustini@baylibre.com; s=20230430; h=from:subject:message-id; bh=BOuTsoiS4wD+cP61c2nYQjChDl2neNVnlaTjhPPnjNo=; b=dcjpH9D4/iuzxXetEkXlXo86ynK58hWjYsp59cgxdD/sG0SgXrxZ439+HwU+bql+QBAfc0iv0 l9K6iCBFRIzATnT9moU6vrLC7rmog09qtMRbIBbp7o96+Fr82mQl/EW X-Developer-Key: i=dfustini@baylibre.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add nodes for the SDHCI fixed clock and the first mmc controller which is typically connected to the eMMC device. Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index ff364709a6df..ee0711352790 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -134,6 +134,13 @@ uart_sclk: uart-sclk-clock { #clock-cells =3D <0>; }; =20 + sdhci_clk: sdhci-clock { + compatible =3D "fixed-clock"; + clock-frequency =3D <198000000>; + clock-output-names =3D "sdhci_clk"; + #clock-cells =3D <0>; + }; + soc { compatible =3D "simple-bus"; interrupt-parent =3D <&plic>; @@ -292,6 +299,14 @@ dmac0: dma-controller@ffefc00000 { status =3D "disabled"; }; =20 + mmc0: mmc@ffe7080000 { + compatible =3D "thead,th1520-dwcmshc"; + reg =3D <0xff 0xe7080000 0x0 0x10000>; + interrupts =3D <62 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&sdhci_clk>; + clock-names =3D "core"; + }; + timer0: timer@ffefc32000 { compatible =3D "snps,dw-apb-timer"; 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Tue, 17 Oct 2023 13:45:30 -0700 (PDT) From: Drew Fustini Date: Tue, 17 Oct 2023 13:43:52 -0700 Subject: [PATCH v2 6/7] riscv: dts: thead: Enable BeagleV Ahead eMMC controller MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231017-th1520-mmc-v2-6-4678c8cc4048@baylibre.com> References: <20231017-th1520-mmc-v2-0-4678c8cc4048@baylibre.com> In-Reply-To: <20231017-th1520-mmc-v2-0-4678c8cc4048@baylibre.com> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jisheng Zhang , Adrian Hunter , Guo Ren , Fu Wei , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley Cc: Robert Nelson , Jason Kridner , Xi Ruoyao , Han Gao , Icenowy Zheng , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Drew Fustini X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1697575515; l=933; i=dfustini@baylibre.com; s=20230430; h=from:subject:message-id; bh=vNFZt2gizhpsjzH9MAKHp09E78+qWWf2znY/lpZAKnk=; b=j5MwipA9159XueCAdESnb2EitXe9gLx6ENZSvmnLtlql41q832inr6iR4u+oaVwFG7pwLGGN0 Vi3eKERq18FDVLSmbURSHVWxMLqysL2SMc3AwBaEAzRyYd2aeL6EEmC X-Developer-Key: i=dfustini@baylibre.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add properties to the emmc node and enable it and set the frequency for the sdhci clock. Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/risc= v/boot/dts/thead/th1520-beaglev-ahead.dts index 70e8042c8304..bf55319ba950 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -52,6 +52,10 @@ &uart_sclk { clock-frequency =3D <100000000>; }; =20 +&sdhci_clk { + clock-frequency =3D <198000000>; +}; + &dmac0 { status =3D "okay"; }; @@ -59,3 +63,13 @@ &dmac0 { &uart0 { status =3D "okay"; }; + +&mmc0 { + bus-width =3D <8>; + max-frequency =3D <198000000>; + mmc-hs400-1_8v; + non-removable; + no-sdio; + no-sd; + status =3D "okay"; +}; --=20 2.34.1 From nobody Fri Jan 2 00:10:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B63ECDB482 for ; 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Tue, 17 Oct 2023 13:45:33 -0700 (PDT) Received: from [127.0.1.1] ([2601:1c2:1800:f680:51d6:dcd6:63ef:52e9]) by smtp.gmail.com with ESMTPSA id w3-20020a17090a6b8300b0027b168cb011sm1906553pjj.56.2023.10.17.13.45.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 13:45:33 -0700 (PDT) From: Drew Fustini Date: Tue, 17 Oct 2023 13:43:53 -0700 Subject: [PATCH v2 7/7] riscv: dts: thead: Enable LicheePi 4A eMMC controller MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231017-th1520-mmc-v2-7-4678c8cc4048@baylibre.com> References: <20231017-th1520-mmc-v2-0-4678c8cc4048@baylibre.com> In-Reply-To: <20231017-th1520-mmc-v2-0-4678c8cc4048@baylibre.com> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jisheng Zhang , Adrian Hunter , Guo Ren , Fu Wei , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley Cc: Robert Nelson , Jason Kridner , Xi Ruoyao , Han Gao , Icenowy Zheng , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Drew Fustini X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1697575515; l=972; i=dfustini@baylibre.com; s=20230430; h=from:subject:message-id; bh=fP0X7H2ev/K5EsIr1ajuR3Wl40rAHHxMMZR5DlF6EQU=; b=zzNGRi480ZBM5jq5QFMXYG/fMcO+yA74L+HUirBBNxAziVp61WiOPvolxmJJ3FfkTdUEllXn1 T0Hl+mS034yATbcHCEq3lYgVdwBJXjkOiBymPsItzNlzSLVMYbyYY/L X-Developer-Key: i=dfustini@baylibre.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add properties to the emmc node and enable it and set the frequency for the sdhci clock. Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/= riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index a802ab110429..bc8f111571bc 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -29,6 +29,10 @@ &apb_clk { clock-frequency =3D <62500000>; }; =20 +&sdhci_clk { + clock-frequency =3D <198000000>; +}; + &uart_sclk { clock-frequency =3D <100000000>; }; @@ -36,3 +40,13 @@ &uart_sclk { &dmac0 { status =3D "okay"; }; + +&mmc0 { + bus-width =3D <8>; + max-frequency =3D <198000000>; + mmc-hs400-1_8v; + non-removable; + no-sdio; + no-sd; + status =3D "okay"; +}; --=20 2.34.1