From nobody Tue Dec 16 20:02:19 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF0F4CDB483 for ; Fri, 13 Oct 2023 14:59:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232246AbjJMO7r (ORCPT ); Fri, 13 Oct 2023 10:59:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232222AbjJMO7n (ORCPT ); Fri, 13 Oct 2023 10:59:43 -0400 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CAB75C9 for ; Fri, 13 Oct 2023 07:59:41 -0700 (PDT) Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-405524e6769so14282525e9.1 for ; Fri, 13 Oct 2023 07:59:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697209180; x=1697813980; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6XixNF8rcGeT14/86b+PK/uBZUvKiNOeydeAMM5h+qM=; b=Lsi3e3LGJnfI/w5D3y8+oG85IYXqdA7QV5Yc662qKbFs6tbGpGMj51Ai+JNrvxYoLy Ur/bqy/Wlw2/B+8XkCOBACG51kwuOd25UfBThoJBjlupbgRFI2cmHdO/EJBbU0IFk3T0 OY+T3zRP5IBFVYgBJVsXjxESVuLiNPoDn6EgC83950Ys5PiVAaO041DlaixhKYxlhq2Q LscH0K+3x4YeEU3uTZiTBYgSxCy09aREGkIGdqdGerxjpqK4l2ZZG82eyC3dMFFi0F5H a77MEftT56uQzn+fePmggD6ojY9B9bZPrhCofp9YSMus4mLgYr5I3ZQdt1zSHpbWu7kz TPig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697209180; x=1697813980; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6XixNF8rcGeT14/86b+PK/uBZUvKiNOeydeAMM5h+qM=; b=Ib0NA+fCk0FfcOH/Hh7c4vpfFv8RwKskG3288bHIYKuKwFxHKgtMuy51LPa2YsSLnh 2rO3Igbse3SenLAOk+tEP6a5EEl4oUpgIDXyIbaZf9y6bypZ+EOP0JqhxHYp90kTETJS IxhCcBHarJ7mK5H9vdEyE7R1AtlEddidQmQfy+8NREp9d51sWPOGmhaVOft1FilWUtJx +l+PbGu65Rw5yPnlOO8K95GsoovQfTjoPUakmantZDvz2q/RsEc21W8JIOw4+3rTowzp kN4FEVKVpwhFQXCrNnW9RvDbZIDEKsC0lXi4yM+RofKMqyXbBp5jxawvhI53rtEdNdsV 5G1g== X-Gm-Message-State: AOJu0YxSbW4Q/E2GjneEDmWoYJ2k35xnz4Z2Mu7JXGI5X0i+4bQ1TUNU 2ZTkPkU7QagoYsiza7Yg7waAjI+hma5ziMKiHj4= X-Google-Smtp-Source: AGHT+IEPQNQrI0nwaQkzVKmF+/qzLrm2eHCyV21p+KfzM81DrT5slU2YLvJSulhh31z+gRCVN4Fj7Q== X-Received: by 2002:a05:600c:3c83:b0:403:aced:f7f4 with SMTP id bg3-20020a05600c3c8300b00403acedf7f4mr308030wmb.12.1697209180272; Fri, 13 Oct 2023 07:59:40 -0700 (PDT) Received: from krzk-bin.. ([178.197.219.100]) by smtp.gmail.com with ESMTPSA id dh13-20020a0560000a8d00b00327cd5e5ac1sm6428267wrb.1.2023.10.13.07.59.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 07:59:39 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v2 1/2] pinctrl: qcom: lpass-lpi: split slew rate set to separate function Date: Fri, 13 Oct 2023 16:59:34 +0200 Message-Id: <20231013145935.220945-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013145935.220945-1-krzysztof.kozlowski@linaro.org> References: <20231013145935.220945-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Setting slew rate for each pin will grow with upcoming Qualcomm SoCs, so split the code responsible for this into separate function for easier readability and maintenance. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- Changes in v2: 1. None --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 53 +++++++++++++++--------- 1 file changed, 33 insertions(+), 20 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qco= m/pinctrl-lpass-lpi.c index 9651aed048cf..4fb808545f7f 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -186,6 +186,35 @@ static int lpi_config_get(struct pinctrl_dev *pctldev, return 0; } =20 +static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl, + const struct lpi_pingroup *g, + unsigned int group, unsigned int slew) +{ + unsigned long sval; + int slew_offset; + + if (slew > LPI_SLEW_RATE_MAX) { + dev_err(pctrl->dev, "invalid slew rate %u for pin: %d\n", + slew, group); + return -EINVAL; + } + + slew_offset =3D g->slew_offset; + if (slew_offset =3D=3D LPI_NO_SLEW) + return 0; + + mutex_lock(&pctrl->lock); + + sval =3D ioread32(pctrl->slew_base + LPI_SLEW_RATE_CTL_REG); + sval &=3D ~(LPI_SLEW_RATE_MASK << slew_offset); + sval |=3D slew << slew_offset; + iowrite32(sval, pctrl->slew_base + LPI_SLEW_RATE_CTL_REG); + + mutex_unlock(&pctrl->lock); + + return 0; +} + static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group, unsigned long *configs, unsigned int nconfs) { @@ -193,8 +222,7 @@ static int lpi_config_set(struct pinctrl_dev *pctldev, = unsigned int group, unsigned int param, arg, pullup =3D LPI_GPIO_BIAS_DISABLE, strength =3D 2; bool value, output_enabled =3D false; const struct lpi_pingroup *g; - unsigned long sval; - int i, slew_offset; + int i, ret; u32 val; =20 g =3D &pctrl->data->groups[group]; @@ -226,24 +254,9 @@ static int lpi_config_set(struct pinctrl_dev *pctldev,= unsigned int group, strength =3D arg; break; case PIN_CONFIG_SLEW_RATE: - if (arg > LPI_SLEW_RATE_MAX) { - dev_err(pctldev->dev, "invalid slew rate %u for pin: %d\n", - arg, group); - return -EINVAL; - } - - slew_offset =3D g->slew_offset; - if (slew_offset =3D=3D LPI_NO_SLEW) - break; - - mutex_lock(&pctrl->lock); - - sval =3D ioread32(pctrl->slew_base + LPI_SLEW_RATE_CTL_REG); - sval &=3D ~(LPI_SLEW_RATE_MASK << slew_offset); - sval |=3D arg << slew_offset; - iowrite32(sval, pctrl->slew_base + LPI_SLEW_RATE_CTL_REG); - - mutex_unlock(&pctrl->lock); + ret =3D lpi_config_set_slew_rate(pctrl, g, group, arg); + if (ret) + return ret; break; default: return -EINVAL; --=20 2.34.1 From nobody Tue Dec 16 20:02:19 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2DB6CDB47E for ; Fri, 13 Oct 2023 14:59:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232265AbjJMO7u (ORCPT ); Fri, 13 Oct 2023 10:59:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230373AbjJMO7o (ORCPT ); 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([178.197.219.100]) by smtp.gmail.com with ESMTPSA id dh13-20020a0560000a8d00b00327cd5e5ac1sm6428267wrb.1.2023.10.13.07.59.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 07:59:41 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v2 2/2] pinctrl: qcom: lpass-lpi: allow slew rate bit in main pin config register Date: Fri, 13 Oct 2023 16:59:35 +0200 Message-Id: <20231013145935.220945-3-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013145935.220945-1-krzysztof.kozlowski@linaro.org> References: <20231013145935.220945-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Existing Qualcomm SoCs have the LPASS pin controller slew rate control in separate register, however this will change with upcoming Qualcomm SoCs. The slew rate will be part of the main register for pin configuration, thus second device IO address space is not needed. Prepare for supporting new SoCs by adding flag customizing the driver behavior for slew rate. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- Changes in v2: 1. Reversed xmas tree v1: https://lore.kernel.org/all/20230901090224.27770-1-krzysztof.kozlowski@= linaro.org/ --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 20 ++++++++++++++------ drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 7 +++++++ 2 files changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qco= m/pinctrl-lpass-lpi.c index 4fb808545f7f..9e410a281bfa 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -191,6 +191,7 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl = *pctrl, unsigned int group, unsigned int slew) { unsigned long sval; + void __iomem *reg; int slew_offset; =20 if (slew > LPI_SLEW_RATE_MAX) { @@ -203,12 +204,17 @@ static int lpi_config_set_slew_rate(struct lpi_pinctr= l *pctrl, if (slew_offset =3D=3D LPI_NO_SLEW) return 0; =20 + if (pctrl->data->flags & LPI_FLAG_SLEW_RATE_SAME_REG) + reg =3D pctrl->tlmm_base + LPI_TLMM_REG_OFFSET * group + LPI_GPIO_CFG_RE= G; + else + reg =3D pctrl->slew_base + LPI_SLEW_RATE_CTL_REG; + mutex_lock(&pctrl->lock); =20 - sval =3D ioread32(pctrl->slew_base + LPI_SLEW_RATE_CTL_REG); + sval =3D ioread32(reg); sval &=3D ~(LPI_SLEW_RATE_MASK << slew_offset); sval |=3D slew << slew_offset; - iowrite32(sval, pctrl->slew_base + LPI_SLEW_RATE_CTL_REG); + iowrite32(sval, reg); =20 mutex_unlock(&pctrl->lock); =20 @@ -452,10 +458,12 @@ int lpi_pinctrl_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base), "TLMM resource not provided\n"); =20 - pctrl->slew_base =3D devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(pctrl->slew_base)) - return dev_err_probe(dev, PTR_ERR(pctrl->slew_base), - "Slew resource not provided\n"); + if (!(data->flags & LPI_FLAG_SLEW_RATE_SAME_REG)) { + pctrl->slew_base =3D devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(pctrl->slew_base)) + return dev_err_probe(dev, PTR_ERR(pctrl->slew_base), + "Slew resource not provided\n"); + } =20 ret =3D devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks); if (ret) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qco= m/pinctrl-lpass-lpi.h index 387d83ee95b5..206b2c0ca828 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h @@ -60,6 +60,12 @@ struct pinctrl_pin_desc; .nfuncs =3D 5, \ } =20 +/* + * Slew rate control is done in the same register as rest of the + * pin configuration. + */ +#define LPI_FLAG_SLEW_RATE_SAME_REG BIT(0) + struct lpi_pingroup { struct group_desc group; unsigned int pin; @@ -82,6 +88,7 @@ struct lpi_pinctrl_variant_data { int ngroups; const struct lpi_function *functions; int nfunctions; + unsigned int flags; }; =20 int lpi_pinctrl_probe(struct platform_device *pdev); --=20 2.34.1