From nobody Tue Dec 16 11:48:18 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6AA64CDB46E for ; Thu, 12 Oct 2023 14:27:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344069AbjJLO1Z (ORCPT ); Thu, 12 Oct 2023 10:27:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58288 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233710AbjJLO1W (ORCPT ); Thu, 12 Oct 2023 10:27:22 -0400 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4200CC0 for ; Thu, 12 Oct 2023 07:27:20 -0700 (PDT) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 73F15C433C8; Thu, 12 Oct 2023 14:27:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1697120839; bh=CR2OauK8hHh42JQRioqOEoUfQnShsiqypCYHqpnkFvE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Z9OE6M7O3//fIKzGaHkxRO26P6HRIr0yQhbVo1q1vUtCwYtLySCna4p0QjoUO3LWu GuGMt0Dg+31D9Gz3sSIkxi+PZaqn6PXRErCbpSLjiV4bP04y8TeXGcB4HOZwtp4KJk 7H0yKEV8Zfdw9NZxjlxmLCGQPhjfDcFREZAbHA8Ylax3p+WxgfD9xSpeSr1aZfkPyT G1LJU0o0LkFmh4deuBKUYZp9SLinTrf73kl4myFhVwDb/e6f2YG4f6j5vBfJtrjoO+ JaDLCQs2m8PMnKytRUIHvmo9KbjvGVstxe6l9s8liY70UsQrt4AbSUR9HI3tuwlUv3 m/DFGfkGV0YMA== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Guo Ren , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Emil Renner Berthing Subject: [PATCH v3 1/2] riscv: errata: thead: use riscv_nonstd_cache_ops for CMO Date: Thu, 12 Oct 2023 22:14:55 +0800 Message-Id: <20231012141456.4078-2-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20231012141456.4078-1-jszhang@kernel.org> References: <20231012141456.4078-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Previously, we use alternative mechanism to dynamically patch the CMO operations for THEAD C906/C910 during boot for performance reason. But as pointed out by Arnd, "there is already a significant cost in accessing the invalidated cache lines afterwards, which is likely going to be much higher than the cost of an indirect branch". And indeed, there's no performance difference with GMAC and EMMC per my test on Sipeed Lichee Pi 4A board. Use riscv_nonstd_cache_ops for THEAD C906/C910 CMO to simplify the alternative code, and to acchieve Arnd's goal -- "I think moving the THEAD ops at the same level as all nonstandard operations makes sense, but I'd still leave CMO as an explicit fast path that avoids the indirect branch. This seems like the right thing to do both for readability and for platforms on which the indirect branch has a noticeable overhead." Signed-off-by: Jisheng Zhang Tested-by: Emil Renner Berthing Reviewed-by: Conor Dooley --- arch/riscv/Kconfig.errata | 1 + arch/riscv/errata/thead/errata.c | 75 +++++++++++++++++++++++++++- arch/riscv/include/asm/errata_list.h | 50 +++---------------- 3 files changed, 80 insertions(+), 46 deletions(-) diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index 566bcefeab50..d7972914f9de 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -78,6 +78,7 @@ config ERRATA_THEAD_CMO bool "Apply T-Head cache management errata" depends on ERRATA_THEAD && MMU select RISCV_DMA_NONCOHERENT + select RISCV_NONSTANDARD_CACHE_OPS default y help This will apply the cache management errata to handle the diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/err= ata.c index 0554ed4bf087..3fefeb1b456e 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -12,8 +12,10 @@ #include #include #include +#include #include #include +#include #include #include =20 @@ -33,6 +35,75 @@ static bool errata_probe_pbmt(unsigned int stage, return false; } =20 +/* + * dcache.ipa rs1 (invalidate, physical address) + * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | + * 0000001 01010 rs1 000 00000 0001011 + * dcache.iva rs1 (invalidate, virtual address) + * 0000001 00110 rs1 000 00000 0001011 + * + * dcache.cpa rs1 (clean, physical address) + * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | + * 0000001 01001 rs1 000 00000 0001011 + * dcache.cva rs1 (clean, virtual address) + * 0000001 00101 rs1 000 00000 0001011 + * + * dcache.cipa rs1 (clean then invalidate, physical address) + * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | + * 0000001 01011 rs1 000 00000 0001011 + * dcache.civa rs1 (clean then invalidate, virtual address) + * 0000001 00111 rs1 000 00000 0001011 + * + * sync.s (make sure all cache operations finished) + * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | + * 0000000 11001 00000 000 00000 0001011 + */ +#define THEAD_inval_A0 ".long 0x0265000b" +#define THEAD_clean_A0 ".long 0x0255000b" +#define THEAD_flush_A0 ".long 0x0275000b" +#define THEAD_SYNC_S ".long 0x0190000b" + +#define THEAD_CMO_OP(_op, _start, _size, _cachesize) \ +asm volatile("mv a0, %1\n\t" \ + "j 2f\n\t" \ + "3:\n\t" \ + THEAD_##_op##_A0 "\n\t" \ + "add a0, a0, %0\n\t" \ + "2:\n\t" \ + "bltu a0, %2, 3b\n\t" \ + THEAD_SYNC_S \ + : : "r"(_cachesize), \ + "r"((unsigned long)(_start) & ~((_cachesize) - 1UL)), \ + "r"((unsigned long)(_start) + (_size)) \ + : "a0") + +static void thead_errata_cache_inv(phys_addr_t paddr, size_t size) +{ + void *vaddr =3D phys_to_virt(paddr); + + THEAD_CMO_OP(inval, vaddr, size, riscv_cbom_block_size); +} + +static void thead_errata_cache_wback(phys_addr_t paddr, size_t size) +{ + void *vaddr =3D phys_to_virt(paddr); + + THEAD_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); +} + +static void thead_errata_cache_wback_inv(phys_addr_t paddr, size_t size) +{ + void *vaddr =3D phys_to_virt(paddr); + + THEAD_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); +} + +static const struct riscv_nonstd_cache_ops thead_errata_cmo_ops =3D { + .wback =3D &thead_errata_cache_wback, + .inv =3D &thead_errata_cache_inv, + .wback_inv =3D &thead_errata_cache_wback_inv, +}; + static bool errata_probe_cmo(unsigned int stage, unsigned long arch_id, unsigned long impid) { @@ -48,6 +119,7 @@ static bool errata_probe_cmo(unsigned int stage, if (stage =3D=3D RISCV_ALTERNATIVES_BOOT) { riscv_cbom_block_size =3D L1_CACHE_BYTES; riscv_noncoherent_supported(); + riscv_noncoherent_register_cache_ops(&thead_errata_cmo_ops); } =20 return true; @@ -77,8 +149,7 @@ static u32 thead_errata_probe(unsigned int stage, if (errata_probe_pbmt(stage, archid, impid)) cpu_req_errata |=3D BIT(ERRATA_THEAD_PBMT); =20 - if (errata_probe_cmo(stage, archid, impid)) - cpu_req_errata |=3D BIT(ERRATA_THEAD_CMO); + errata_probe_cmo(stage, archid, impid); =20 if (errata_probe_pmu(stage, archid, impid)) cpu_req_errata |=3D BIT(ERRATA_THEAD_PMU); diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/= errata_list.h index b55b434f0059..ea33288f8a25 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -24,9 +24,8 @@ =20 #ifdef CONFIG_ERRATA_THEAD #define ERRATA_THEAD_PBMT 0 -#define ERRATA_THEAD_CMO 1 -#define ERRATA_THEAD_PMU 2 -#define ERRATA_THEAD_NUMBER 3 +#define ERRATA_THEAD_PMU 1 +#define ERRATA_THEAD_NUMBER 2 #endif =20 #ifdef __ASSEMBLY__ @@ -94,54 +93,17 @@ asm volatile(ALTERNATIVE( \ #define ALT_THEAD_PMA(_val) #endif =20 -/* - * dcache.ipa rs1 (invalidate, physical address) - * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | - * 0000001 01010 rs1 000 00000 0001011 - * dache.iva rs1 (invalida, virtual address) - * 0000001 00110 rs1 000 00000 0001011 - * - * dcache.cpa rs1 (clean, physical address) - * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | - * 0000001 01001 rs1 000 00000 0001011 - * dcache.cva rs1 (clean, virtual address) - * 0000001 00101 rs1 000 00000 0001011 - * - * dcache.cipa rs1 (clean then invalidate, physical address) - * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | - * 0000001 01011 rs1 000 00000 0001011 - * dcache.civa rs1 (... virtual address) - * 0000001 00111 rs1 000 00000 0001011 - * - * sync.s (make sure all cache operations finished) - * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | - * 0000000 11001 00000 000 00000 0001011 - */ -#define THEAD_inval_A0 ".long 0x0265000b" -#define THEAD_clean_A0 ".long 0x0255000b" -#define THEAD_flush_A0 ".long 0x0275000b" -#define THEAD_SYNC_S ".long 0x0190000b" - #define ALT_CMO_OP(_op, _start, _size, _cachesize) \ -asm volatile(ALTERNATIVE_2( \ - __nops(6), \ +asm volatile(ALTERNATIVE( \ + __nops(5), \ "mv a0, %1\n\t" \ "j 2f\n\t" \ "3:\n\t" \ CBO_##_op(a0) \ "add a0, a0, %0\n\t" \ "2:\n\t" \ - "bltu a0, %2, 3b\n\t" \ - "nop", 0, RISCV_ISA_EXT_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \ - "mv a0, %1\n\t" \ - "j 2f\n\t" \ - "3:\n\t" \ - THEAD_##_op##_A0 "\n\t" \ - "add a0, a0, %0\n\t" \ - "2:\n\t" \ - "bltu a0, %2, 3b\n\t" \ - THEAD_SYNC_S, THEAD_VENDOR_ID, \ - ERRATA_THEAD_CMO, CONFIG_ERRATA_THEAD_CMO) \ + "bltu a0, %2, 3b\n\t", \ + 0, RISCV_ISA_EXT_ZICBOM, CONFIG_RISCV_ISA_ZICBOM) \ : : "r"(_cachesize), \ "r"((unsigned long)(_start) & ~((_cachesize) - 1UL)), \ "r"((unsigned long)(_start) + (_size)) \ --=20 2.40.1 From nobody Tue Dec 16 11:48:18 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0C16CDB47E for ; Thu, 12 Oct 2023 14:27:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347262AbjJLO12 (ORCPT ); Thu, 12 Oct 2023 10:27:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58306 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344035AbjJLO1Y (ORCPT ); Thu, 12 Oct 2023 10:27:24 -0400 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB697BE for ; Thu, 12 Oct 2023 07:27:22 -0700 (PDT) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9A04DC433C9; Thu, 12 Oct 2023 14:27:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1697120842; bh=qzR32gMwqLa17IpLtlTXacrXoBXks+o3rMWn8BtgPT4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KxEzD4Hb45irhwRrR6hmVCp9cRJNfnq1J8JUzLAk6c0ZrW5q+mVClsOlJX3lIlK9Y d/ZwrOqNaJn8hH7/jCQ1lzfXy42fMEYNWxcU1f1BEF9lSEqEICRP87lWmjP1CXS4Ys LisBPismY1a2v66e+o79sXzTudUIMUUHdp0Z4SZ2kPZlngpuER0y9SWZC4UDLhtwIA w/ikdXlLY3iKZEhZO1RKv7eIxs1XKQ666mlm8jJEcqPuPRGNvJ9vtq1nw3Ii1bbRVm S89Hh34WiBgf1M5OZ6NSJT3JNotxrWOfhmSJrL3MgLQyhP+dT5JjIrn9tmdb8BkfT0 0M5i2RnPY0zPQ== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Guo Ren , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/2] riscv: errata: thead: use pa based instructions for CMO Date: Thu, 12 Oct 2023 22:14:56 +0800 Message-Id: <20231012141456.4078-3-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20231012141456.4078-1-jszhang@kernel.org> References: <20231012141456.4078-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" T-HEAD CPUs such as C906/C910/C920 support phy address based CMO, use them so that we don't need to convert to virt address. Signed-off-by: Jisheng Zhang --- arch/riscv/errata/thead/errata.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/err= ata.c index 3fefeb1b456e..632557f36b19 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -58,9 +58,9 @@ static bool errata_probe_pbmt(unsigned int stage, * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | * 0000000 11001 00000 000 00000 0001011 */ -#define THEAD_inval_A0 ".long 0x0265000b" -#define THEAD_clean_A0 ".long 0x0255000b" -#define THEAD_flush_A0 ".long 0x0275000b" +#define THEAD_inval_A0 ".long 0x02a5000b" +#define THEAD_clean_A0 ".long 0x0295000b" +#define THEAD_flush_A0 ".long 0x02b5000b" #define THEAD_SYNC_S ".long 0x0190000b" =20 #define THEAD_CMO_OP(_op, _start, _size, _cachesize) \ @@ -79,23 +79,17 @@ asm volatile("mv a0, %1\n\t" \ =20 static void thead_errata_cache_inv(phys_addr_t paddr, size_t size) { - void *vaddr =3D phys_to_virt(paddr); - - THEAD_CMO_OP(inval, vaddr, size, riscv_cbom_block_size); + THEAD_CMO_OP(inval, paddr, size, riscv_cbom_block_size); } =20 static void thead_errata_cache_wback(phys_addr_t paddr, size_t size) { - void *vaddr =3D phys_to_virt(paddr); - - THEAD_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); + THEAD_CMO_OP(clean, paddr, size, riscv_cbom_block_size); } =20 static void thead_errata_cache_wback_inv(phys_addr_t paddr, size_t size) { - void *vaddr =3D phys_to_virt(paddr); - - THEAD_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); + THEAD_CMO_OP(flush, paddr, size, riscv_cbom_block_size); } =20 static const struct riscv_nonstd_cache_ops thead_errata_cmo_ops =3D { --=20 2.40.1