From nobody Tue Dec 16 21:25:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3756CDB47E for ; Thu, 12 Oct 2023 11:31:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378229AbjJLLbZ (ORCPT ); Thu, 12 Oct 2023 07:31:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41034 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378322AbjJLLbO (ORCPT ); Thu, 12 Oct 2023 07:31:14 -0400 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E8195CA for ; Thu, 12 Oct 2023 04:31:11 -0700 (PDT) Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-405361bb94eso10479125e9.0 for ; Thu, 12 Oct 2023 04:31:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697110270; x=1697715070; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nweWobJWJBf+E3jMJor/bM09luKRlFeXTfeRgH/BAFs=; b=YKROy4YyH5/giI2LWCn8oBylTKO5U3/9qGJsm0NxlHJU1KoAzNGxh+eQil9oQtmRkJ HsKt2yfL/I5CQUr8ZaTJPpHwofwV1/06MMqMbfrE1qZdeV35F8cmjnKV1pbh/CjV0gHt AueTl9t1vVqqTO5OrzeF5CqR8dVzd6xn8S770VjTlqUoaUATZZWCtN+t8z62n5yn6wJZ 82d1AooxqoOjb0izGBKnBEQY9ubtOtA0BV6nWWaTlf26+UGwvnlTUWfGWz+C9Pl6V5YO lON8Bg1PjLwSEQutFK96ffwLki/QYXLcCp+Wuhe+Xv0H7L2BhxYJGsOtmAMv/EhHJjrd 5ZRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697110270; x=1697715070; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nweWobJWJBf+E3jMJor/bM09luKRlFeXTfeRgH/BAFs=; b=FyIt9Slk+vcTGL0bQhfCqLCOweDR5lzqX/XlsclgbBD/JAu65DAl5WP0XvQH52aVED cM/T4yqAltV3Us+FPuM8WTPUULxgjuMLMZRTV+kAmSTyYolaHDZwwra8G1799cFlXiUc fuf1KVV1/mzRrSS+WdtyEiY/Nf9dYLkZWPXgvXGZLapPEScCGKT7IVafJb9uYcr8tfEV thu/xnjGbEGVGiH5Jtc3Vu7eN4h7zdZZJqbVIaHRjDfEKS6qqU3jUDsSO5Ot/ffH2lcE Etoz24DJkIGPnXVU4NLgDTt9R3T/OraumzBR2AHbz57JAMxIWJ06KqHHZo7L5JS1QdJe kFfw== X-Gm-Message-State: AOJu0Yyi5zpVKwJEugf4TqpBPZymWG4CkUmWn7N4EU2jeiqW6K6gj3Ha 8koVgsBKz1HhNoGZjoknEcIpwg== X-Google-Smtp-Source: AGHT+IGzL/VBHml/MgfXpJ7hDrVWBYtjSuBeGZBQky2hOQpUuhcT8MU0XUFGEJs11cUsOAdJE2lEJQ== X-Received: by 2002:adf:fdc7:0:b0:320:c9c8:5f14 with SMTP id i7-20020adffdc7000000b00320c9c85f14mr21604562wrs.29.1697110270324; Thu, 12 Oct 2023 04:31:10 -0700 (PDT) Received: from x13s-linux.nxsw.local ([37.228.218.3]) by smtp.gmail.com with ESMTPSA id l14-20020a5d480e000000b0031c5e9c2ed7sm18244891wrq.92.2023.10.12.04.31.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Oct 2023 04:31:09 -0700 (PDT) From: Bryan O'Donoghue To: andersson@kernel.org, agross@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, dmitry.baryshkov@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, jonathan@marek.ca, quic_tdas@quicinc.com, vladimir.zapolskiy@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bryan.odonoghue@linaro.org Subject: [PATCH v4 4/4] arm64: dts: qcom: sc8280xp: camss: Add CAMSS block definition Date: Thu, 12 Oct 2023 12:31:00 +0100 Message-Id: <20231012113100.3656480-5-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231012113100.3656480-1-bryan.odonoghue@linaro.org> References: <20231012113100.3656480-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add CAMSS block definition for sc8280xp. This drop contains definitions for the following components on sc8280xp: VFE * 4 VFE Lite * 4 CSID * 4 CSIPHY * 4 This dtsi definition has been developed and validated on a Lenovo X13s laptop. Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 285 +++++++++++++++++++++++++ 1 file changed, 285 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 22e9671af0e9..c1fac3e872f4 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -3615,6 +3615,291 @@ cci3_i2c1: i2c-bus@1 { }; }; =20 + camss: camss@ac5a000 { + compatible =3D "qcom,sc8280xp-camss"; + + reg =3D <0 0x0ac5a000 0 0x2000>, + <0 0x0ac5c000 0 0x2000>, + <0 0x0ac65000 0 0x2000>, + <0 0x0ac67000 0 0x2000>, + <0 0x0acaf000 0 0x4000>, + <0 0x0acb3000 0 0x1000>, + <0 0x0acb6000 0 0x4000>, + <0 0x0acba000 0 0x1000>, + <0 0x0acbd000 0 0x4000>, + <0 0x0acc1000 0 0x1000>, + <0 0x0acc4000 0 0x4000>, + <0 0x0acc8000 0 0x1000>, + <0 0x0accb000 0 0x4000>, + <0 0x0accf000 0 0x1000>, + <0 0x0acd2000 0 0x4000>, + <0 0x0acd6000 0 0x1000>, + <0 0x0acd9000 0 0x4000>, + <0 0x0acdd000 0 0x1000>, + <0 0x0ace0000 0 0x4000>, + <0 0x0ace4000 0 0x1000>; + + reg-names =3D "csiphy2", + "csiphy3", + "csiphy0", + "csiphy1", + "vfe0", + "csid0", + "vfe1", + "csid1", + "vfe2", + "csid2", + "vfe_lite0", + "csid0_lite", + "vfe_lite1", + "csid1_lite", + "vfe_lite2", + "csid2_lite", + "vfe_lite3", + "csid3_lite", + "vfe3", + "csid3"; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + interrupt-names =3D "csid1_lite", + "vfe_lite1", + "csiphy3", + "csid0", + "vfe0", + "csid1", + "vfe1", + "csid0_lite", + "vfe_lite0", + "csiphy0", + "csiphy1", + "csiphy2", + "csid2", + "vfe2", + "csid3_lite", + "csid2_lite", + "vfe_lite3", + "vfe_lite2", + "csid3", + "vfe3"; + + power-domains =3D <&camcc IFE_0_GDSC>, + <&camcc IFE_1_GDSC>, + <&camcc IFE_2_GDSC>, + <&camcc IFE_3_GDSC>, + <&camcc TITAN_TOP_GDSC>; + + power-domain-names =3D "ife0", + "ife1", + "ife2", + "ife3", + "top"; + + clocks =3D <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_CAMNOC_AXI_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CPHY_RX_CLK_SRC>, + <&camcc CAMCC_CSIPHY0_CLK>, + <&camcc CAMCC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAMCC_CSI0PHYTIMER_CLK>, + <&camcc CAMCC_CSIPHY1_CLK>, + <&camcc CAMCC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAMCC_CSI1PHYTIMER_CLK>, + <&camcc CAMCC_CSIPHY2_CLK>, + <&camcc CAMCC_CSI2PHYTIMER_CLK_SRC>, + <&camcc CAMCC_CSI2PHYTIMER_CLK>, + <&camcc CAMCC_CSIPHY3_CLK>, + <&camcc CAMCC_CSI3PHYTIMER_CLK_SRC>, + <&camcc CAMCC_CSI3PHYTIMER_CLK>, + <&camcc CAMCC_IFE_0_AXI_CLK>, + <&camcc CAMCC_IFE_0_CLK_SRC>, + <&camcc CAMCC_IFE_0_CLK>, + <&camcc CAMCC_IFE_0_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_0_CSID_CLK_SRC>, + <&camcc CAMCC_IFE_0_CSID_CLK>, + <&camcc CAMCC_IFE_1_AXI_CLK>, + <&camcc CAMCC_IFE_1_CLK_SRC>, + <&camcc CAMCC_IFE_1_CLK>, + <&camcc CAMCC_IFE_1_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_1_CSID_CLK_SRC>, + <&camcc CAMCC_IFE_1_CSID_CLK>, + <&camcc CAMCC_IFE_2_AXI_CLK>, + <&camcc CAMCC_IFE_2_CLK_SRC>, + <&camcc CAMCC_IFE_2_CLK>, + <&camcc CAMCC_IFE_2_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_2_CSID_CLK_SRC>, + <&camcc CAMCC_IFE_2_CSID_CLK>, + <&camcc CAMCC_IFE_3_AXI_CLK>, + <&camcc CAMCC_IFE_3_CLK_SRC>, + <&camcc CAMCC_IFE_3_CLK>, + <&camcc CAMCC_IFE_3_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_3_CSID_CLK_SRC>, + <&camcc CAMCC_IFE_3_CSID_CLK>, + <&camcc CAMCC_IFE_LITE_0_CLK_SRC>, + <&camcc CAMCC_IFE_LITE_0_CLK>, + <&camcc CAMCC_IFE_LITE_0_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_LITE_0_CSID_CLK_SRC>, + <&camcc CAMCC_IFE_LITE_0_CSID_CLK>, + <&camcc CAMCC_IFE_LITE_1_CLK_SRC>, + <&camcc CAMCC_IFE_LITE_1_CLK>, + <&camcc CAMCC_IFE_LITE_1_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_LITE_1_CSID_CLK_SRC>, + <&camcc CAMCC_IFE_LITE_1_CSID_CLK>, + <&camcc CAMCC_IFE_LITE_2_CLK_SRC>, + <&camcc CAMCC_IFE_LITE_2_CLK>, + <&camcc CAMCC_IFE_LITE_2_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_LITE_2_CSID_CLK_SRC>, + <&camcc CAMCC_IFE_LITE_2_CSID_CLK>, + <&camcc CAMCC_IFE_LITE_3_CLK_SRC>, + <&camcc CAMCC_IFE_LITE_3_CLK>, + <&camcc CAMCC_IFE_LITE_3_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_LITE_3_CSID_CLK_SRC>, + <&camcc CAMCC_IFE_LITE_3_CSID_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>; + + clock-names =3D "camnoc_axi", + "camnoc_axi_src", + "cpas_ahb", + "cphy_rx_src", + "csiphy0", + "csiphy0_timer_src", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer_src", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer_src", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer_src", + "csiphy3_timer", + "vfe0_axi", + "vfe0_src", + "vfe0", + "vfe0_cphy_rx", + "vfe0_csid_src", + "vfe0_csid", + "vfe1_axi", + "vfe1_src", + "vfe1", + "vfe1_cphy_rx", + "vfe1_csid_src", + "vfe1_csid", + "vfe2_axi", + "vfe2_src", + "vfe2", + "vfe2_cphy_rx", + "vfe2_csid_src", + "vfe2_csid", + "vfe3_axi", + "vfe3_src", + "vfe3", + "vfe3_cphy_rx", + "vfe3_csid_src", + "vfe3_csid", + "vfe_lite0_src", + "vfe_lite0", + "vfe_lite0_cphy_rx", + "vfe_lite0_csid_src", + "vfe_lite0_csid", + "vfe_lite1_src", + "vfe_lite1", + "vfe_lite1_cphy_rx", + "vfe_lite1_csid_src", + "vfe_lite1_csid", + "vfe_lite2_src", + "vfe_lite2", + "vfe_lite2_cphy_rx", + "vfe_lite2_csid_src", + "vfe_lite2_csid", + "vfe_lite3_src", + "vfe_lite3", + "vfe_lite3_cphy_rx", + "vfe_lite3_csid_src", + "vfe_lite3_csid", + "gcc_axi_hf", + "gcc_axi_sf", + "slow_ahb_src"; + + iommus =3D <&apps_smmu 0x2000 0x4e0>, + <&apps_smmu 0x2020 0x4e0>, + <&apps_smmu 0x2040 0x4e0>, + <&apps_smmu 0x2060 0x4e0>, + <&apps_smmu 0x2080 0x4e0>, + <&apps_smmu 0x20e0 0x4e0>, + <&apps_smmu 0x20c0 0x4e0>, + <&apps_smmu 0x20a0 0x4e0>, + <&apps_smmu 0x2400 0x4e0>, + <&apps_smmu 0x2420 0x4e0>, + <&apps_smmu 0x2440 0x4e0>, + <&apps_smmu 0x2460 0x4e0>, + <&apps_smmu 0x2480 0x4e0>, + <&apps_smmu 0x24e0 0x4e0>, + <&apps_smmu 0x24c0 0x4e0>, + <&apps_smmu 0x24a0 0x4e0>; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMER= A_CFG 0>, + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "cam_ahb", + "cam_hf_mnoc", + "cam_sf_mnoc", + "cam_sf_icp_mnoc"; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + port@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + port@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + port@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + }; + camcc: clock-controller@ad00000 { compatible =3D "qcom,sc8280xp-camcc"; reg =3D <0 0x0ad00000 0 0x20000>; --=20 2.40.1