From nobody Fri Sep 20 12:29:43 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7CA8CDB482 for ; Thu, 12 Oct 2023 09:58:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343729AbjJLJ6y (ORCPT ); Thu, 12 Oct 2023 05:58:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59956 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235628AbjJLJ6E (ORCPT ); Thu, 12 Oct 2023 05:58:04 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9153C6 for ; Thu, 12 Oct 2023 02:57:56 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id AAED66607354; Thu, 12 Oct 2023 10:57:54 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1697104675; bh=kE4xYln1H3vYAzVz5ckJegqLjKvVvNwbUjwODAr7b6I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eZKU5RSOCY9RHfx4yarEb75ggkhZjyQUINmE4jOinyW+vOySM8TEWzdZnmTcnrTl2 hEVtTNNuwb+BsJgyMF00UzEuMk9852sUyA15s3TIDga2Nx+i73LUBc3UVz6KhCfGi9 V3M1U829zMKEVF7K7UecXz5UwySA34VDPZktxBUQ+x0YpJU334YIDmjytTGmBF9vvg 1/0AbSKDWZRQB+pMzl4tT7uUBbylsLVIB9Rn8jmurG21h1bAt1pezGKLmu8IFklXyo R/NcvaqZcRoA7zyevdTCxvz5A0B5BRC26fdZOy5cO0vOnfPzRelJKXGX/fSjqy0KRy KN7y+Lvs0zH7w== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, nfraprado@collabora.com, "Jason-JH . Lin" , Alexandre Mergnat , CK Hu Subject: [PATCH v11 13/16] drm/mediatek: gamma: Program gamma LUT type for descending or rising Date: Thu, 12 Oct 2023 11:57:33 +0200 Message-ID: <20231012095736.100784-14-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> References: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All of the SoCs that don't have dithering control in the gamma IP have got a GAMMA_LUT_TYPE bit that tells to the IP if the LUT is "descending" (bit set) or "rising" (bit cleared): make sure to set it correctly after programming the LUT. Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index 6746033615db..0f116c0e51b5 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -22,6 +22,7 @@ #define GAMMA_RELAY_MODE BIT(0) #define GAMMA_LUT_EN BIT(1) #define GAMMA_DITHERING BIT(2) +#define GAMMA_LUT_TYPE BIT(2) #define DISP_GAMMA_SIZE 0x0030 #define DISP_GAMMA_SIZE_HSIZE GENMASK(28, 16) #define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) @@ -82,6 +83,17 @@ unsigned int mtk_gamma_get_lut_size(struct device *dev) return 0; } =20 +static bool mtk_gamma_lut_is_descending(struct drm_color_lut *lut, u32 lut= _size) +{ + u64 first, last; + int last_entry =3D lut_size - 1; + + first =3D lut[0].red + lut[0].green + lut[0].blue; + last =3D lut[last_entry].red + lut[last_entry].green + lut[last_entry].bl= ue; + + return !!(first > last); +} + /* * SoCs supporting 12-bits LUTs are using a new register layout that does * always support (by HW) both 12-bits and 10-bits LUT but, on those, we @@ -173,6 +185,14 @@ void mtk_gamma_set(struct device *dev, struct drm_crtc= _state *state) =20 cfg_val =3D readl(gamma->regs + DISP_GAMMA_CFG); =20 + if (!gamma->data->has_dither) { + /* Descending or Rising LUT */ + if (mtk_gamma_lut_is_descending(lut, gamma->data->lut_size - 1)) + cfg_val |=3D FIELD_PREP(GAMMA_LUT_TYPE, 1); + else + cfg_val &=3D ~GAMMA_LUT_TYPE; + } + /* Enable the gamma table */ cfg_val |=3D FIELD_PREP(GAMMA_LUT_EN, 1); =20 --=20 2.42.0