From nobody Thu Dec 18 19:20:24 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80D31CDB46E for ; Thu, 12 Oct 2023 08:10:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235352AbjJLIKa convert rfc822-to-8bit (ORCPT ); Thu, 12 Oct 2023 04:10:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58262 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235331AbjJLIK2 (ORCPT ); Thu, 12 Oct 2023 04:10:28 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C1D290; Thu, 12 Oct 2023 01:10:24 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id A465724E37D; Thu, 12 Oct 2023 16:10:17 +0800 (CST) Received: from EXMBX061.cuchost.com (172.16.6.61) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 12 Oct 2023 16:10:17 +0800 Received: from localhost.localdomain (183.27.96.95) by EXMBX061.cuchost.com (172.16.6.61) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 12 Oct 2023 16:10:16 +0800 From: Xingyu Wu To: Daniel Lezcano , Thomas Gleixner , Emil Renner Berthing , Walker Chen CC: , , "Rob Herring" , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Xingyu Wu , Samin Guo , , Conor Dooley Subject: [PATCH v6 1/3] dt-bindings: timer: Add timer for StarFive JH7110 SoC Date: Thu, 12 Oct 2023 16:10:13 +0800 Message-ID: <20231012081015.33121-2-xingyu.wu@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231012081015.33121-1-xingyu.wu@starfivetech.com> References: <20231012081015.33121-1-xingyu.wu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.96.95] X-ClientProxiedBy: EXCAS063.cuchost.com (172.16.6.23) To EXMBX061.cuchost.com (172.16.6.61) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add bindings for the timer on the JH7110 RISC-V SoC by StarFive Technology Ltd. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Xingyu Wu --- .../bindings/timer/starfive,jh7110-timer.yaml | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/starfive,jh7110= -timer.yaml diff --git a/Documentation/devicetree/bindings/timer/starfive,jh7110-timer.= yaml b/Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml new file mode 100644 index 000000000000..9a2dac11eb06 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/starfive,jh7110-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 Timer + +maintainers: + - Xingyu Wu + - Samin Guo + +description: + This timer has four free-running 32 bit counters in StarFive JH7110 SoC. + And each channel(counter) triggers an interrupt when timeout. They suppo= rt + one-shot mode and continuous-run mode. + +properties: + compatible: + const: starfive,jh7110-timer + + reg: + maxItems: 1 + + interrupts: + items: + - description: channel 0 + - description: channel 1 + - description: channel 2 + - description: channel 3 + + clocks: + items: + - description: timer APB + - description: channel 0 + - description: channel 1 + - description: channel 2 + - description: channel 3 + + clock-names: + items: + - const: apb + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 + + resets: + items: + - description: timer APB + - description: channel 0 + - description: channel 1 + - description: channel 2 + - description: channel 3 + + reset-names: + items: + - const: apb + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + timer@13050000 { + compatible =3D "starfive,jh7110-timer"; + reg =3D <0x13050000 0x10000>; + interrupts =3D <69>, <70>, <71> ,<72>; + clocks =3D <&clk 124>, + <&clk 125>, + <&clk 126>, + <&clk 127>, + <&clk 128>; + clock-names =3D "apb", "ch0", "ch1", + "ch2", "ch3"; + resets =3D <&rst 117>, + <&rst 118>, + <&rst 119>, + <&rst 120>, + <&rst 121>; + reset-names =3D "apb", "ch0", "ch1", + "ch2", "ch3"; + }; + --=20 2.25.1 From nobody Thu Dec 18 19:20:24 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F41CCDB46E for ; Thu, 12 Oct 2023 08:10:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235390AbjJLIKs convert rfc822-to-8bit (ORCPT ); Thu, 12 Oct 2023 04:10:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235345AbjJLIKi (ORCPT ); Thu, 12 Oct 2023 04:10:38 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1FBF7DD; Thu, 12 Oct 2023 01:10:33 -0700 (PDT) Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ex01.ufhost.com (Postfix) with ESMTP id 7AD5C24E382; Thu, 12 Oct 2023 16:10:18 +0800 (CST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 5A6497FC9; Thu, 12 Oct 2023 16:10:18 +0800 (CST) Received: from EXMBX061.cuchost.com (172.16.6.61) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 12 Oct 2023 16:10:18 +0800 Received: from localhost.localdomain (183.27.96.95) by EXMBX061.cuchost.com (172.16.6.61) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 12 Oct 2023 16:10:17 +0800 From: Xingyu Wu To: Daniel Lezcano , Thomas Gleixner , Emil Renner Berthing , Walker Chen CC: , , "Rob Herring" , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Xingyu Wu , Samin Guo , , Conor Dooley Subject: [PATCH v6 2/3] clocksource: Add JH7110 timer driver Date: Thu, 12 Oct 2023 16:10:14 +0800 Message-ID: <20231012081015.33121-3-xingyu.wu@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231012081015.33121-1-xingyu.wu@starfivetech.com> References: <20231012081015.33121-1-xingyu.wu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.96.95] X-ClientProxiedBy: EXCAS063.cuchost.com (172.16.6.23) To EXMBX061.cuchost.com (172.16.6.61) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add timer driver for the StarFive JH7110 SoC. Signed-off-by: Xingyu Wu --- MAINTAINERS | 7 + drivers/clocksource/Kconfig | 11 + drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-jh7110.c | 387 +++++++++++++++++++++++++++++ 4 files changed, 406 insertions(+) create mode 100644 drivers/clocksource/timer-jh7110.c diff --git a/MAINTAINERS b/MAINTAINERS index 6c4cce45a09d..1525f031d4a2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20472,6 +20472,13 @@ S: Maintained F: Documentation/devicetree/bindings/sound/starfive,jh7110-tdm.yaml F: sound/soc/starfive/jh7110_tdm.c =20 +STARFIVE JH7110 TIMER DRIVER +M: Samin Guo +M: Xingyu Wu +S: Supported +F: Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml +F: drivers/clocksource/timer-jh7110.c + STARFIVE JH71X0 CLOCK DRIVERS M: Emil Renner Berthing M: Hal Feng diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 0ba0dc4ecf06..821abcc1e517 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -641,6 +641,17 @@ config RISCV_TIMER is accessed via both the SBI and the rdcycle instruction. This is required for all RISC-V systems. =20 +config STARFIVE_JH7110_TIMER + bool "Timer for the STARFIVE JH7110 SoC" + depends on ARCH_STARFIVE || COMPILE_TEST + select TIMER_OF + select CLKSRC_MMIO + default ARCH_STARFIVE + help + This enables the timer for StarFive JH7110 SoC. On RISC-V platform, + the system has started RISCV_TIMER, but you can also use this timer + which can provide four channels to do a lot more things on JH7110 SoC. + config CLINT_TIMER bool "CLINT Timer for the RISC-V platform" if COMPILE_TEST depends on GENERIC_SCHED_CLOCK && RISCV diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 368c3461dab8..b66ac05ec086 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -80,6 +80,7 @@ obj-$(CONFIG_INGENIC_TIMER) +=3D ingenic-timer.o obj-$(CONFIG_CLKSRC_ST_LPC) +=3D clksrc_st_lpc.o obj-$(CONFIG_X86_NUMACHIP) +=3D numachip.o obj-$(CONFIG_RISCV_TIMER) +=3D timer-riscv.o +obj-$(CONFIG_STARFIVE_JH7110_TIMER) +=3D timer-jh7110.o obj-$(CONFIG_CLINT_TIMER) +=3D timer-clint.o obj-$(CONFIG_CSKY_MP_TIMER) +=3D timer-mp-csky.o obj-$(CONFIG_GX6605S_TIMER) +=3D timer-gx6605s.o diff --git a/drivers/clocksource/timer-jh7110.c b/drivers/clocksource/timer= -jh7110.c new file mode 100644 index 000000000000..914424368290 --- /dev/null +++ b/drivers/clocksource/timer-jh7110.c @@ -0,0 +1,387 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Starfive JH7110 Timer driver + * + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. + * + * Author: + * Xingyu Wu + * Samin Guo + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Bias: Ch0-0x0, Ch1-0x40, Ch2-0x80, and so on. */ +#define JH7110_TIMER_CH_LEN 0x40 +#define JH7110_TIMER_CH_BASE(x) ((x) * JH7110_TIMER_CH_LEN) +#define JH7110_TIMER_CH_MAX 4 + +#define JH7110_CLOCK_SOURCE_RATING 200 +#define JH7110_VALID_BITS 32 +#define JH7110_DELAY_US 0 +#define JH7110_TIMEOUT_US 10000 +#define JH7110_CLOCKEVENT_RATING 300 +#define JH7110_TIMER_MAX_TICKS 0xffffffff +#define JH7110_TIMER_MIN_TICKS 0xf +#define JH7110_TIMER_NAME_NUM 19 + +#define JH7110_TIMER_INT_STATUS 0x00 /* RO[0:4]: Interrupt Status for cha= nnel0~4 */ +#define JH7110_TIMER_CTL 0x04 /* RW[0]: 0-continuous run, 1-single run */ +#define JH7110_TIMER_LOAD 0x08 /* RW: load value to counter */ +#define JH7110_TIMER_ENABLE 0x10 /* RW[0]: timer enable register */ +#define JH7110_TIMER_RELOAD 0x14 /* RW: write 1 or 0 both reload counter = */ +#define JH7110_TIMER_VALUE 0x18 /* RO: timer value register */ +#define JH7110_TIMER_INT_CLR 0x20 /* RW: timer interrupt clear register */ +#define JH7110_TIMER_INT_MASK 0x24 /* RW[0]: timer interrupt mask registe= r */ +#define JH7110_TIMER_INT_CLR_AVA_MASK BIT(1) + +struct jh7110_clkevt { + struct clock_event_device evt; + struct clocksource cs; + struct clk *clk; + char name[JH7110_TIMER_NAME_NUM]; + int irq; + u32 rate; + u32 reload_val; + void __iomem *base; +}; + +static inline struct jh7110_clkevt *to_jh7110_clkevt(struct clock_event_de= vice *evt) +{ + return container_of(evt, struct jh7110_clkevt, evt); +} + +/* 0:continuous-run mode, 1:single-run mode */ +static inline void jh7110_timer_set_continuous_mod(struct jh7110_clkevt *c= lkevt) +{ + writel(0, clkevt->base + JH7110_TIMER_CTL); +} + +static inline void jh7110_timer_set_single_mod(struct jh7110_clkevt *clkev= t) +{ + writel(1, clkevt->base + JH7110_TIMER_CTL); +} + +/* Interrupt Mask Register, 0:Unmask, 1:Mask */ +static inline void jh7110_timer_int_enable(struct jh7110_clkevt *clkevt) +{ + writel(0, clkevt->base + JH7110_TIMER_INT_MASK); +} + +static inline void jh7110_timer_int_disable(struct jh7110_clkevt *clkevt) +{ + writel(1, clkevt->base + JH7110_TIMER_INT_MASK); +} + +/* + * BIT(0): Read value represent channel intr status. + * Write 1 to this bit to clear interrupt. Write 0 has no effects. + * BIT(1): "1" means that it is clearing interrupt. BIT(0) can not be writ= ten. + */ +static inline int jh7110_timer_int_clear(struct jh7110_clkevt *clkevt) +{ + u32 value; + int ret; + + /* waiting interrupt can be to clearing */ + ret =3D readl_poll_timeout_atomic(clkevt->base + JH7110_TIMER_INT_CLR, va= lue, + !(value & JH7110_TIMER_INT_CLR_AVA_MASK), + JH7110_DELAY_US, JH7110_TIMEOUT_US); + if (!ret) + writel(0x1, clkevt->base + JH7110_TIMER_INT_CLR); + + return ret; +} + +/* + * The initial value to be loaded into the + * counter and is also used as the reload value. + * val =3D clock rate --> 1s + */ +static inline void jh7110_timer_set_load(struct jh7110_clkevt *clkevt, u32= val) +{ + writel(val, clkevt->base + JH7110_TIMER_LOAD); +} + +static inline u32 jh7110_timer_get_val(struct jh7110_clkevt *clkevt) +{ + return readl(clkevt->base + JH7110_TIMER_VALUE); +} + +/* + * Write RELOAD register to reload preset value to counter. + * Write 0 and write 1 are both ok. + */ +static inline void jh7110_timer_set_reload(struct jh7110_clkevt *clkevt) +{ + writel(0, clkevt->base + JH7110_TIMER_RELOAD); +} + +static inline void jh7110_timer_enable(struct jh7110_clkevt *clkevt) +{ + writel(1, clkevt->base + JH7110_TIMER_ENABLE); +} + +static inline void jh7110_timer_disable(struct jh7110_clkevt *clkevt) +{ + writel(0, clkevt->base + JH7110_TIMER_ENABLE); +} + +static int jh7110_timer_int_init_enable(struct jh7110_clkevt *clkevt) +{ + int ret; + + jh7110_timer_int_disable(clkevt); + ret =3D jh7110_timer_int_clear(clkevt); + if (ret) + return ret; + + jh7110_timer_int_enable(clkevt); + jh7110_timer_enable(clkevt); + + return 0; +} + +static int jh7110_timer_shutdown(struct clock_event_device *evt) +{ + struct jh7110_clkevt *clkevt =3D to_jh7110_clkevt(evt); + + jh7110_timer_disable(clkevt); + return jh7110_timer_int_clear(clkevt); +} + +static void jh7110_timer_suspend(struct clock_event_device *evt) +{ + struct jh7110_clkevt *clkevt =3D to_jh7110_clkevt(evt); + + clkevt->reload_val =3D jh7110_timer_get_val(clkevt); + jh7110_timer_shutdown(evt); +} + +static void jh7110_timer_resume(struct clock_event_device *evt) +{ + struct jh7110_clkevt *clkevt =3D to_jh7110_clkevt(evt); + + jh7110_timer_set_load(clkevt, clkevt->reload_val); + jh7110_timer_set_reload(clkevt); + jh7110_timer_int_enable(clkevt); + jh7110_timer_enable(clkevt); +} + +static int jh7110_timer_tick_resume(struct clock_event_device *evt) +{ + jh7110_timer_resume(evt); + + return 0; +} + +/* IRQ handler for the timer */ +static irqreturn_t jh7110_timer_interrupt(int irq, void *priv) +{ + struct clock_event_device *evt =3D (struct clock_event_device *)priv; + struct jh7110_clkevt *clkevt =3D to_jh7110_clkevt(evt); + + if (jh7110_timer_int_clear(clkevt)) + return IRQ_NONE; + + if (evt->event_handler) + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static int jh7110_timer_set_periodic(struct clock_event_device *evt) +{ + struct jh7110_clkevt *clkevt =3D to_jh7110_clkevt(evt); + u32 periodic =3D DIV_ROUND_CLOSEST(clkevt->rate, HZ); + + jh7110_timer_disable(clkevt); + jh7110_timer_set_continuous_mod(clkevt); + jh7110_timer_set_load(clkevt, periodic); + + return jh7110_timer_int_init_enable(clkevt); +} + +static int jh7110_timer_set_oneshot(struct clock_event_device *evt) +{ + struct jh7110_clkevt *clkevt =3D to_jh7110_clkevt(evt); + + jh7110_timer_disable(clkevt); + jh7110_timer_set_single_mod(clkevt); + jh7110_timer_set_load(clkevt, JH7110_TIMER_MAX_TICKS); + + return jh7110_timer_int_init_enable(clkevt); +} + +static int jh7110_timer_set_next_event(unsigned long next, + struct clock_event_device *evt) +{ + struct jh7110_clkevt *clkevt =3D to_jh7110_clkevt(evt); + + jh7110_timer_disable(clkevt); + jh7110_timer_set_single_mod(clkevt); + jh7110_timer_set_load(clkevt, next); + jh7110_timer_enable(clkevt); + + return 0; +} + +static void jh7110_set_clockevent(struct clock_event_device *evt) +{ + evt->features =3D CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_ONESHOT | + CLOCK_EVT_FEAT_DYNIRQ; + evt->set_state_shutdown =3D jh7110_timer_shutdown; + evt->set_state_periodic =3D jh7110_timer_set_periodic; + evt->set_state_oneshot =3D jh7110_timer_set_oneshot; + evt->set_state_oneshot_stopped =3D jh7110_timer_shutdown; + evt->tick_resume =3D jh7110_timer_tick_resume; + evt->set_next_event =3D jh7110_timer_set_next_event; + evt->suspend =3D jh7110_timer_suspend; + evt->resume =3D jh7110_timer_resume; + evt->rating =3D JH7110_CLOCKEVENT_RATING; +} + +static u64 jh7110_timer_clocksource_read(struct clocksource *cs) +{ + struct jh7110_clkevt *clkevt =3D container_of(cs, struct jh7110_clkevt, c= s); + + return (u64)jh7110_timer_get_val(clkevt); +} + +static int jh7110_clocksource_init(struct jh7110_clkevt *clkevt) +{ + int ret; + + jh7110_timer_set_continuous_mod(clkevt); + jh7110_timer_set_load(clkevt, JH7110_TIMER_MAX_TICKS); + + ret =3D jh7110_timer_int_init_enable(clkevt); + if (ret) + return ret; + + clkevt->cs.name =3D clkevt->name; + clkevt->cs.rating =3D JH7110_CLOCK_SOURCE_RATING; + clkevt->cs.read =3D jh7110_timer_clocksource_read; + clkevt->cs.mask =3D CLOCKSOURCE_MASK(JH7110_VALID_BITS); + clkevt->cs.flags =3D CLOCK_SOURCE_IS_CONTINUOUS; + + return clocksource_register_hz(&clkevt->cs, clkevt->rate); +} + +static void jh7110_clockevents_register(struct jh7110_clkevt *clkevt) +{ + clkevt->rate =3D clk_get_rate(clkevt->clk); + + jh7110_set_clockevent(&clkevt->evt); + clkevt->evt.name =3D clkevt->name; + clkevt->evt.cpumask =3D cpu_possible_mask; + + clockevents_config_and_register(&clkevt->evt, clkevt->rate, + JH7110_TIMER_MIN_TICKS, JH7110_TIMER_MAX_TICKS); +} + +static int jh7110_timer_probe(struct platform_device *pdev) +{ + struct jh7110_clkevt *clkevt[JH7110_TIMER_CH_MAX]; + char name[4]; + struct clk *pclk; + struct reset_control *rst; + int ch; + int ret; + void __iomem *base; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return dev_err_probe(&pdev->dev, PTR_ERR(base), + "failed to map registers\n"); + + rst =3D devm_reset_control_get_exclusive(&pdev->dev, "apb"); + if (IS_ERR(rst)) + return dev_err_probe(&pdev->dev, PTR_ERR(rst), "failed to get apb reset\= n"); + + pclk =3D devm_clk_get_enabled(&pdev->dev, "apb"); + if (IS_ERR(pclk)) + return dev_err_probe(&pdev->dev, PTR_ERR(pclk), + "failed to get & enable apb clock\n"); + + ret =3D reset_control_deassert(rst); + if (ret) + return dev_err_probe(&pdev->dev, ret, "failed to deassert apb reset\n"); + + for (ch =3D 0; ch < JH7110_TIMER_CH_MAX; ch++) { + clkevt[ch] =3D devm_kzalloc(&pdev->dev, sizeof(*clkevt[ch]), GFP_KERNEL); + if (!clkevt[ch]) + return -ENOMEM; + + snprintf(name, sizeof(name), "ch%d", ch); + + clkevt[ch]->base =3D base + JH7110_TIMER_CH_BASE(ch); + /* Ensure timer is disabled */ + jh7110_timer_disable(clkevt[ch]); + + rst =3D devm_reset_control_get_exclusive(&pdev->dev, name); + if (IS_ERR(rst)) + return PTR_ERR(rst); + + clkevt[ch]->clk =3D devm_clk_get_enabled(&pdev->dev, name); + if (IS_ERR(clkevt[ch]->clk)) + return PTR_ERR(clkevt[ch]->clk); + + ret =3D reset_control_deassert(rst); + if (ret) + return ret; + + clkevt[ch]->evt.irq =3D platform_get_irq(pdev, ch); + if (clkevt[ch]->evt.irq < 0) + return clkevt[ch]->evt.irq; + + snprintf(clkevt[ch]->name, sizeof(clkevt[ch]->name), "%s.ch%d", pdev->na= me, ch); + jh7110_clockevents_register(clkevt[ch]); + + ret =3D devm_request_irq(&pdev->dev, clkevt[ch]->evt.irq, jh7110_timer_i= nterrupt, + IRQF_TIMER | IRQF_IRQPOLL, + clkevt[ch]->name, &clkevt[ch]->evt); + if (ret) + return ret; + + ret =3D jh7110_clocksource_init(clkevt[ch]); + if (ret) + return ret; + } + + return 0; +} + +static const struct of_device_id jh7110_timer_match[] =3D { + { .compatible =3D "starfive,jh7110-timer", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jh7110_timer_match); + +static struct platform_driver jh7110_timer_driver =3D { + .probe =3D jh7110_timer_probe, + .driver =3D { + .name =3D "jh7110-timer", + .of_match_table =3D jh7110_timer_match, + }, +}; +module_platform_driver(jh7110_timer_driver); + +MODULE_AUTHOR("Xingyu Wu "); +MODULE_DESCRIPTION("StarFive JH7110 timer driver"); +MODULE_LICENSE("GPL"); --=20 2.25.1 From nobody Thu Dec 18 19:20:24 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39DC4CDB46E for ; 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Thu, 12 Oct 2023 16:10:17 +0800 From: Xingyu Wu To: Daniel Lezcano , Thomas Gleixner , Emil Renner Berthing , Walker Chen CC: , , "Rob Herring" , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Xingyu Wu , Samin Guo , , Conor Dooley Subject: [PATCH v6 3/3] riscv: dts: jh7110: starfive: Add timer node Date: Thu, 12 Oct 2023 16:10:15 +0800 Message-ID: <20231012081015.33121-4-xingyu.wu@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231012081015.33121-1-xingyu.wu@starfivetech.com> References: <20231012081015.33121-1-xingyu.wu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.96.95] X-ClientProxiedBy: EXCAS063.cuchost.com (172.16.6.23) To EXMBX061.cuchost.com (172.16.6.61) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the timer node for the Starfive JH7110 SoC. Reviewed-by: Walker Chen Signed-off-by: Xingyu Wu --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts= /starfive/jh7110.dtsi index e85464c328d0..d17c8005aaf6 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -811,6 +811,26 @@ sysgpio: pinctrl@13040000 { #gpio-cells =3D <2>; }; =20 + timer@13050000 { + compatible =3D "starfive,jh7110-timer"; + reg =3D <0x0 0x13050000 0x0 0x10000>; + interrupts =3D <69>, <70>, <71> ,<72>; + clocks =3D <&syscrg JH7110_SYSCLK_TIMER_APB>, + <&syscrg JH7110_SYSCLK_TIMER0>, + <&syscrg JH7110_SYSCLK_TIMER1>, + <&syscrg JH7110_SYSCLK_TIMER2>, + <&syscrg JH7110_SYSCLK_TIMER3>; + clock-names =3D "apb", "ch0", "ch1", + "ch2", "ch3"; + resets =3D <&syscrg JH7110_SYSRST_TIMER_APB>, + <&syscrg JH7110_SYSRST_TIMER0>, + <&syscrg JH7110_SYSRST_TIMER1>, + <&syscrg JH7110_SYSRST_TIMER2>, + <&syscrg JH7110_SYSRST_TIMER3>; + reset-names =3D "apb", "ch0", "ch1", + "ch2", "ch3"; + }; + watchdog@13070000 { compatible =3D "starfive,jh7110-wdt"; reg =3D <0x0 0x13070000 0x0 0x10000>; --=20 2.25.1