From nobody Thu Dec 18 19:26:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E949ACDB46E for ; Thu, 12 Oct 2023 05:15:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377055AbjJLFPf (ORCPT ); Thu, 12 Oct 2023 01:15:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44060 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233879AbjJLFP0 (ORCPT ); Thu, 12 Oct 2023 01:15:26 -0400 Received: from mail-pg1-x52a.google.com (mail-pg1-x52a.google.com [IPv6:2607:f8b0:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A07EC9 for ; Wed, 11 Oct 2023 22:15:24 -0700 (PDT) Received: by mail-pg1-x52a.google.com with SMTP id 41be03b00d2f7-5859a7d6556so452891a12.0 for ; Wed, 11 Oct 2023 22:15:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1697087723; x=1697692523; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=B8bTrDTugOefVQ1gZ31VUL3xKHXyC/9v3hCQTi2FF0M=; b=PNA01VWNv5rr7c5hvYy72qP2gSfhJBWYL7GkWB8vh2i5whAT7kBzB6WDQw4dcv8hNn R62hI6nuQIewYkRRvBc9uLH1pmZvirjGJOV6fTkSKOBSJJo80ejAsm+bEIjp+SDfaWmj R1A+1kX6zyq8OguCZyQccqWG5F9KLoA0fAHhkCS6jpnI7+Iw3QCptJqgv+4qne2Z0uNn evtQPvTolgsxS1q4C3Hc+NR+UtS1AKAES3JOnK490mxa5mhhq1frmc9v6QnPJP9pJmCg nEEyk0D1eZlKfJyA8rLtDAoaSL4a4m/RPzZ2HCkencgQEDdyCVFarfChRgA6ECwVKpNi T77g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697087723; x=1697692523; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B8bTrDTugOefVQ1gZ31VUL3xKHXyC/9v3hCQTi2FF0M=; b=Of25+GUvqZdmiYznQEc+YtGODfz97a2iolbJ0TSbBJlAO3BpJQDdvMV+xufKXOMTSj c0ylcZ2MyHkmDJsgzaEfffc9tqmeNrDrYP8iYIf75zjs5AYDZhXbxTpUCdNoIpWcaGtr JEQ6Cop3kBtXmgEaok/Pf9jfH55DnVJreFXH66DDqZa36yHHTGI4Z5J7pcrX0b6NsN2D byFCAhHbtzM7kdfG2maknQD1vxG4IFblQXzzvwYmn/k12uKBKIWbKz8+SlxMR5kgALD/ XCNu5YLhqd5kO1dvjWhVSnX1FRBX+qOUe1Ef++YmJdwMMKghZp8xPVsvmaknQibAJZWf tLAQ== X-Gm-Message-State: AOJu0YzN74WsD+a1OIiQ4qFRwiHlv3iFit29Jkkzpz3Od5E86j2SuRTb 2/egJba97LkC6nQ9B0hlZvSMJA== X-Google-Smtp-Source: AGHT+IF5O37nt3kva1oplLeK9oTh/UptqKIJMOtFRGHJUvOY3IKhqZJUhVs0shUGm9K4PlGiYUf6Xg== X-Received: by 2002:a05:6a20:1609:b0:153:7515:9919 with SMTP id l9-20020a056a20160900b0015375159919mr27813886pzj.21.1697087723486; Wed, 11 Oct 2023 22:15:23 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([106.51.83.242]) by smtp.gmail.com with ESMTPSA id s18-20020a17090330d200b001b9d95945afsm851309plc.155.2023.10.11.22.15.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 22:15:23 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Greg Kroah-Hartman , Jiri Slaby Cc: Conor Dooley , Andrew Jones , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v2 1/8] RISC-V: Add defines for SBI debug console extension Date: Thu, 12 Oct 2023 10:45:02 +0530 Message-Id: <20231012051509.738750-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231012051509.738750-1-apatel@ventanamicro.com> References: <20231012051509.738750-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We add SBI debug console extension related defines/enum to the asm/sbi.h header. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- arch/riscv/include/asm/sbi.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 5b4a1bf5f439..12dfda6bb924 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -30,6 +30,7 @@ enum sbi_ext_id { SBI_EXT_HSM =3D 0x48534D, SBI_EXT_SRST =3D 0x53525354, SBI_EXT_PMU =3D 0x504D55, + SBI_EXT_DBCN =3D 0x4442434E, =20 /* Experimentals extensions must lie within this range */ SBI_EXT_EXPERIMENTAL_START =3D 0x08000000, @@ -236,6 +237,12 @@ enum sbi_pmu_ctr_type { /* Flags defined for counter stop function */ #define SBI_PMU_STOP_FLAG_RESET (1 << 0) =20 +enum sbi_ext_dbcn_fid { + SBI_EXT_DBCN_CONSOLE_WRITE =3D 0, + SBI_EXT_DBCN_CONSOLE_READ =3D 1, + SBI_EXT_DBCN_CONSOLE_WRITE_BYTE =3D 2, +}; + #define SBI_SPEC_VERSION_DEFAULT 0x1 #define SBI_SPEC_VERSION_MAJOR_SHIFT 24 #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f --=20 2.34.1 From nobody Thu Dec 18 19:26:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A9DBCDB47E for ; Thu, 12 Oct 2023 05:15:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377079AbjJLFPk (ORCPT ); Thu, 12 Oct 2023 01:15:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44142 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377111AbjJLFP3 (ORCPT ); Thu, 12 Oct 2023 01:15:29 -0400 Received: from mail-pf1-x429.google.com (mail-pf1-x429.google.com [IPv6:2607:f8b0:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9795DBE for ; Wed, 11 Oct 2023 22:15:28 -0700 (PDT) Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-68fb85afef4so492832b3a.1 for ; Wed, 11 Oct 2023 22:15:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1697087728; x=1697692528; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=l3lhlJZP7U6sfVX0rlDY0S8d2x8DhhVnWXy5WEJL0wg=; b=bO+joST4fnerVfNdvxbD3G3EoUdUyb/IiYMN7kJDot/319BBpvmqIEXizqDQpzw4fo Zr71ov/sReYoJpVlsLm+EYW8Y0K0WOwapk0LVesTMBkXNfV4GShQfOza4eChN6syVvUn GnGch/9x0NYKMJnJN7NWWdonUf5rTM90CKKcOU0mJGwc62UI5u4dSrOValXKOmSFap/b alTHuwF8ML7KvPL0/HQITD035UCzdTBp+7YnJOhRdaq5oDZtarz3pdVCDdJK6lZEjaTP V//DM5DKE0DsYP+ErdQZiOrK8UcJOb9mLLl9CYmCW/sXMYZ1pJcXiJuqUAKlon7wYXC9 9LAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697087728; x=1697692528; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=l3lhlJZP7U6sfVX0rlDY0S8d2x8DhhVnWXy5WEJL0wg=; b=WCy0HXAzmBQ1X2okyp2QNysQQ5xWK5WXidfWXEdrq1gH6R8r+zYJIKoh3kpp3j4wu1 PRphdNzCkvS9NqaWwXo+Yd6lmp/1yGdw8tXQWTScDWZCAVfjDOlcWp+DzHgtFHw++NGv nc8n9H5XoMZRDnePT5cV+uyZurDkyamEEsVaXoO+ts/xQM0ccxE+vqMKVedxXj9I9EfF 8+9ML95iT9kQFhxQRZJjaM6uAuXbct4ZZRLmPGNITkAxrb7CvUG8d4EvxYlL31lQmiG2 vboMyS02GKYcDKI/FqlOXBtamk6CWMuMlqTVs3Kbo/i9bqPULlz3VmWIMrP5ZOBmV6Jx iICA== X-Gm-Message-State: AOJu0Yxl1oWxkEQEcfrQVugP78aBz5yIEMNSZIXtTtsB7HFIVcOTKa4n QRKHIBQq8M+5PV4m9a1eQY6dCw== X-Google-Smtp-Source: AGHT+IEYTYmKd3tYlh3LiHGeR+Se06zPGfuu6PsLv0v0PYM+oZ1DNY/YAR7he8NCW/RMMx46gl3FeQ== X-Received: by 2002:a05:6a21:7784:b0:173:318:b1ec with SMTP id bd4-20020a056a21778400b001730318b1ecmr5209664pzc.35.1697087727987; Wed, 11 Oct 2023 22:15:27 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([106.51.83.242]) by smtp.gmail.com with ESMTPSA id s18-20020a17090330d200b001b9d95945afsm851309plc.155.2023.10.11.22.15.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 22:15:27 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Greg Kroah-Hartman , Jiri Slaby Cc: Conor Dooley , Andrew Jones , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v2 2/8] RISC-V: KVM: Change the SBI specification version to v2.0 Date: Thu, 12 Oct 2023 10:45:03 +0530 Message-Id: <20231012051509.738750-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231012051509.738750-1-apatel@ventanamicro.com> References: <20231012051509.738750-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We will be implementing SBI DBCN extension for KVM RISC-V so let us change the KVM RISC-V SBI specification version to v2.0. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- arch/riscv/include/asm/kvm_vcpu_sbi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm= /kvm_vcpu_sbi.h index cdcf0ff07be7..8d6d4dce8a5e 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h @@ -11,7 +11,7 @@ =20 #define KVM_SBI_IMPID 3 =20 -#define KVM_SBI_VERSION_MAJOR 1 +#define KVM_SBI_VERSION_MAJOR 2 #define KVM_SBI_VERSION_MINOR 0 =20 enum kvm_riscv_sbi_ext_status { --=20 2.34.1 From nobody Thu Dec 18 19:26:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0EC3DCDB46E for ; Thu, 12 Oct 2023 05:16:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377097AbjJLFP6 (ORCPT ); Thu, 12 Oct 2023 01:15:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44194 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235304AbjJLFPu (ORCPT ); Thu, 12 Oct 2023 01:15:50 -0400 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5BD0FE4 for ; Wed, 11 Oct 2023 22:15:33 -0700 (PDT) Received: by mail-pj1-x1035.google.com with SMTP id 98e67ed59e1d1-27d1f57bda7so325221a91.0 for ; Wed, 11 Oct 2023 22:15:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1697087732; x=1697692532; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UnnUYFylMM7osLHu6Gv9hbGwiUDTuyMbxo3uWzdsMQU=; b=dqE0nNGaOHUpekPXSfgZl7ELDKFozCRnkUzlU0U79v0qa1HjKV6VKTn94IdJwbs7Dx WBV/TEw69VackiL3io9W+O9SJwsvcYvVtefCIgaZoqRtZnERLNvu65TF/AgODJigZ47c 280MMqvMu3EwXueYABWHYwTTE0vrpmw64V4PpYZ1mNhJCDxHoF9732oki6ogsw79wnMI cKAWequtAgEVA1UaAM8ryMEpuhk5DmWBr0U2XsK9sObQRyqiLxJuS72bVkcVKKe2bbsK V5Tn47JSKahVP3WomCV1qh0HsGySjZ9K9NFL40HoxkmMuhTLhikGx3gjT/2t9ahU4scX jQJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697087732; x=1697692532; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UnnUYFylMM7osLHu6Gv9hbGwiUDTuyMbxo3uWzdsMQU=; b=ftnDzXBf+dJob9T8iwHu/gqxh3GNPV81LOQ6JWWKSuaFQT+xMicdGvD/NhUgaFUnkc RBkwM1PdwJI5RcSCFBOypbXkUYHSTAb1rLfaYtv0kQSS63PztQeDg74rMXPBm4hExRRm ohzb+4D61Ons9RHELbeaqeenWKb/gAuDLzinCir0cp8ttXhAfNbjfnF+UWQ6SDs3HlOg IJzHWh4gh3NgT0zj1R0OCt7n4ejEZXClXCLkZ6c8hUH6OmVTaeEr3PzR/HeruwxmK4hs XoaJlMpEbjSYVGxu2RsDnOpLddC9BDLeyqW3EM71Y8pG7axR3wjgZHYTdIAb9DmIby9c 5New== X-Gm-Message-State: AOJu0Yx3LwmDbbZkmGWwI0N0U3lYWvQtxxoqFcE+3QpGy5JBOgs/4K8v wYz4BnrJz9owepwXqdBThOCVG9u853QM9P4gSSo= X-Google-Smtp-Source: AGHT+IFfVbiUmgMwoeGwA3ZIdiIUuzVdm9gRZ3aJR2yt7ibzGaKFZJms3sDVibgDvTppejsGgzuaOA== X-Received: by 2002:a17:90a:c254:b0:27d:1f9f:a57f with SMTP id d20-20020a17090ac25400b0027d1f9fa57fmr918230pjx.32.1697087732343; Wed, 11 Oct 2023 22:15:32 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([106.51.83.242]) by smtp.gmail.com with ESMTPSA id s18-20020a17090330d200b001b9d95945afsm851309plc.155.2023.10.11.22.15.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 22:15:31 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Greg Kroah-Hartman , Jiri Slaby Cc: Conor Dooley , Andrew Jones , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v2 3/8] RISC-V: KVM: Allow some SBI extensions to be disabled by default Date: Thu, 12 Oct 2023 10:45:04 +0530 Message-Id: <20231012051509.738750-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231012051509.738750-1-apatel@ventanamicro.com> References: <20231012051509.738750-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently, all SBI extensions are enabled by default which is problematic for SBI extensions (such as DBCN) which are forwarded to the KVM user-space because we might have an older KVM user-space which is not aware/ready to handle newer SBI extensions. Ideally, the SBI extensions forwarded to the KVM user-space must be disabled by default. To address above, we allow certain SBI extensions to be disabled by default so that KVM user-space must explicitly enable such SBI extensions to receive forwarded calls from Guest VCPU. Signed-off-by: Anup Patel --- arch/riscv/include/asm/kvm_vcpu_sbi.h | 4 +++ arch/riscv/kvm/vcpu.c | 6 ++++ arch/riscv/kvm/vcpu_sbi.c | 45 ++++++++++++++++----------- 3 files changed, 36 insertions(+), 19 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm= /kvm_vcpu_sbi.h index 8d6d4dce8a5e..c02bda5559d7 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h @@ -35,6 +35,9 @@ struct kvm_vcpu_sbi_return { struct kvm_vcpu_sbi_extension { unsigned long extid_start; unsigned long extid_end; + + bool default_unavail; + /** * SBI extension handler. It can be defined for a given extension or grou= p of * extension. But it should always return linux error codes rather than S= BI @@ -59,6 +62,7 @@ int kvm_riscv_vcpu_get_reg_sbi_ext(struct kvm_vcpu *vcpu, const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext( struct kvm_vcpu *vcpu, unsigned long extid); int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run); +void kvm_riscv_vcpu_sbi_init(struct kvm_vcpu *vcpu); =20 #ifdef CONFIG_RISCV_SBI_V01 extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_v01; diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index c061a1c5fe98..e087c809073c 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -141,6 +141,12 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) if (rc) return rc; =20 + /* + * Setup SBI extensions + * NOTE: This must be the last thing to be initialized. + */ + kvm_riscv_vcpu_sbi_init(vcpu); + /* Reset VCPU */ kvm_riscv_reset_vcpu(vcpu); =20 diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c index 9cd97091c723..1b1cee86efda 100644 --- a/arch/riscv/kvm/vcpu_sbi.c +++ b/arch/riscv/kvm/vcpu_sbi.c @@ -155,14 +155,8 @@ static int riscv_vcpu_set_sbi_ext_single(struct kvm_vc= pu *vcpu, if (!sext) return -ENOENT; =20 - /* - * We can't set the extension status to available here, since it may - * have a probe() function which needs to confirm availability first, - * but it may be too early to call that here. We can set the status to - * unavailable, though. - */ - if (!reg_val) - scontext->ext_status[sext->ext_idx] =3D + scontext->ext_status[sext->ext_idx] =3D (reg_val) ? + KVM_RISCV_SBI_EXT_AVAILABLE : KVM_RISCV_SBI_EXT_UNAVAILABLE; =20 return 0; @@ -337,18 +331,8 @@ const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find= _ext( scontext->ext_status[entry->ext_idx] =3D=3D KVM_RISCV_SBI_EXT_AVAILABLE) return ext; - if (scontext->ext_status[entry->ext_idx] =3D=3D - KVM_RISCV_SBI_EXT_UNAVAILABLE) - return NULL; - if (ext->probe && !ext->probe(vcpu)) { - scontext->ext_status[entry->ext_idx] =3D - KVM_RISCV_SBI_EXT_UNAVAILABLE; - return NULL; - } =20 - scontext->ext_status[entry->ext_idx] =3D - KVM_RISCV_SBI_EXT_AVAILABLE; - return ext; + return NULL; } } =20 @@ -419,3 +403,26 @@ int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, st= ruct kvm_run *run) =20 return ret; } + +void kvm_riscv_vcpu_sbi_init(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_sbi_context *scontext =3D &vcpu->arch.sbi_context; + const struct kvm_riscv_sbi_extension_entry *entry; + const struct kvm_vcpu_sbi_extension *ext; + int i; + + for (i =3D 0; i < ARRAY_SIZE(sbi_ext); i++) { + entry =3D &sbi_ext[i]; + ext =3D entry->ext_ptr; + + if (ext->probe && !ext->probe(vcpu)) { + scontext->ext_status[entry->ext_idx] =3D + KVM_RISCV_SBI_EXT_UNAVAILABLE; + continue; + } + + scontext->ext_status[entry->ext_idx] =3D ext->default_unavail ? + KVM_RISCV_SBI_EXT_UNAVAILABLE : + KVM_RISCV_SBI_EXT_AVAILABLE; + } +} --=20 2.34.1 From nobody Thu Dec 18 19:26:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D330CDB46E for ; Thu, 12 Oct 2023 05:16:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377151AbjJLFQE (ORCPT ); Thu, 12 Oct 2023 01:16:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44194 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235334AbjJLFPw (ORCPT ); Thu, 12 Oct 2023 01:15:52 -0400 Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8DDC7110 for ; Wed, 11 Oct 2023 22:15:37 -0700 (PDT) Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-1c9b95943beso5323465ad.1 for ; Wed, 11 Oct 2023 22:15:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1697087737; x=1697692537; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5F82Co3/cdirw9N8c47oejx7W6gl4Raymf8m/hgF9mg=; b=Aa8pV8cmo1PCC0/FwyfvUQZbJPtmLkPsmt3DzZIZkibCUodWHn9RE7KnXVOv5dt2SU RQWrTvQeSPsO00eEjdIcS4AvOv2Vtevi6mF2c4L7FXWl83JbX1DtGN2y7oGIR05y2NUY Q3bPGo8jDAlYCxsnHZteeHzCbjCrfRDPmVJWn4f9mvc1BLU/RLGwK0IYZnf7qM7XTJnK rE/zjjn0mRowhqTQlb6q7h+4vWLDqtpIAZEmojxSoL7GPhUaAWaswytlV9A2w0LoZdpv hpz6YVrKA/+cF53/td7Zhb1v0sO2u4+61GEpflGdbIQd92XUDlFM1laQJvEiYNnuBFKy R1JQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697087737; x=1697692537; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5F82Co3/cdirw9N8c47oejx7W6gl4Raymf8m/hgF9mg=; b=JS/3hJCWjjblECHLDPB+ibFjYhnItCtABj9BRDy5GW9HnB8Fujx3nfPhIyj/e8Mz6x EuYaOeLKLxErYhfQwl6xQT0zTPU3rVFlxn1o3DzKBN/aYmdT1KinK8JaUd/A2yyh6l9A f3sWw4sfSGjnBXpog8KJqavsUcKm+zQtQPUZTpsiguNSjyqll1Rss6mF/xmk4XJPrc4P oaYBwX1ObJD/0bhVVfcchK6ATs3l0XGmetf/Us4zX7LNI8kZYn4791QDWOWQVPX4EgZ2 kGOr6jf0q7lzprvumiZhAk122LvvYjjvSDFDecQ4VAjAIyAZDkcx61DfnwaoLY++WNX2 OWBA== X-Gm-Message-State: AOJu0YyTm/kCnSqFuOLbdWWYtu+d3vGebSIfA6jODc9vpFDRJfg0jUpZ xeq84Kcu/5+KvL22bdjDiATRyw== X-Google-Smtp-Source: AGHT+IFZ9PIs/5Xdz63daF5WgvnqI8HA2E47f1F59gFa33dzVCANlp1ZCJBRk4958EXc+DlXohYaDw== X-Received: by 2002:a17:902:d48f:b0:1c9:d358:b3c9 with SMTP id c15-20020a170902d48f00b001c9d358b3c9mr2956911plg.19.1697087736652; Wed, 11 Oct 2023 22:15:36 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([106.51.83.242]) by smtp.gmail.com with ESMTPSA id s18-20020a17090330d200b001b9d95945afsm851309plc.155.2023.10.11.22.15.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 22:15:36 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Greg Kroah-Hartman , Jiri Slaby Cc: Conor Dooley , Andrew Jones , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v2 4/8] RISC-V: KVM: Forward SBI DBCN extension to user-space Date: Thu, 12 Oct 2023 10:45:05 +0530 Message-Id: <20231012051509.738750-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231012051509.738750-1-apatel@ventanamicro.com> References: <20231012051509.738750-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The frozen SBI v2.0 specification defines the SBI debug console (DBCN) extension which replaces the legacy SBI v0.1 console functions namely sbi_console_getchar() and sbi_console_putchar(). The SBI DBCN extension needs to be emulated in the KVM user-space (i.e. QEMU-KVM or KVMTOOL) so we forward SBI DBCN calls from KVM guest to the KVM user-space which can then redirect the console input/output to wherever it wants (e.g. telnet, file, stdio, etc). The SBI debug console is simply a early console available to KVM guest for early prints and it does not intend to replace the proper console devices such as 8250, VirtIO console, etc. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- arch/riscv/include/asm/kvm_vcpu_sbi.h | 1 + arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu_sbi.c | 4 ++++ arch/riscv/kvm/vcpu_sbi_replace.c | 32 +++++++++++++++++++++++++++ 4 files changed, 38 insertions(+) diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm= /kvm_vcpu_sbi.h index c02bda5559d7..6a453f7f8b56 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h @@ -73,6 +73,7 @@ extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_i= pi; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_rfence; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_srst; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_hsm; +extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_dbcn; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_experimental; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_vendor; =20 diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index 917d8cc2489e..60d3b21dead7 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -156,6 +156,7 @@ enum KVM_RISCV_SBI_EXT_ID { KVM_RISCV_SBI_EXT_PMU, KVM_RISCV_SBI_EXT_EXPERIMENTAL, KVM_RISCV_SBI_EXT_VENDOR, + KVM_RISCV_SBI_EXT_DBCN, KVM_RISCV_SBI_EXT_MAX, }; =20 diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c index 1b1cee86efda..bb76c3cf633f 100644 --- a/arch/riscv/kvm/vcpu_sbi.c +++ b/arch/riscv/kvm/vcpu_sbi.c @@ -66,6 +66,10 @@ static const struct kvm_riscv_sbi_extension_entry sbi_ex= t[] =3D { .ext_idx =3D KVM_RISCV_SBI_EXT_PMU, .ext_ptr =3D &vcpu_sbi_ext_pmu, }, + { + .ext_idx =3D KVM_RISCV_SBI_EXT_DBCN, + .ext_ptr =3D &vcpu_sbi_ext_dbcn, + }, { .ext_idx =3D KVM_RISCV_SBI_EXT_EXPERIMENTAL, .ext_ptr =3D &vcpu_sbi_ext_experimental, diff --git a/arch/riscv/kvm/vcpu_sbi_replace.c b/arch/riscv/kvm/vcpu_sbi_re= place.c index 7c4d5d38a339..23b57c931b15 100644 --- a/arch/riscv/kvm/vcpu_sbi_replace.c +++ b/arch/riscv/kvm/vcpu_sbi_replace.c @@ -175,3 +175,35 @@ const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_srst = =3D { .extid_end =3D SBI_EXT_SRST, .handler =3D kvm_sbi_ext_srst_handler, }; + +static int kvm_sbi_ext_dbcn_handler(struct kvm_vcpu *vcpu, + struct kvm_run *run, + struct kvm_vcpu_sbi_return *retdata) +{ + struct kvm_cpu_context *cp =3D &vcpu->arch.guest_context; + unsigned long funcid =3D cp->a6; + + switch (funcid) { + case SBI_EXT_DBCN_CONSOLE_WRITE: + case SBI_EXT_DBCN_CONSOLE_READ: + case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: + /* + * The SBI debug console functions are unconditionally + * forwarded to the userspace. + */ + kvm_riscv_vcpu_sbi_forward(vcpu, run); + retdata->uexit =3D true; + break; + default: + retdata->err_val =3D SBI_ERR_NOT_SUPPORTED; + } + + return 0; +} + +const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_dbcn =3D { + .extid_start =3D SBI_EXT_DBCN, + .extid_end =3D SBI_EXT_DBCN, + .default_unavail =3D true, + .handler =3D kvm_sbi_ext_dbcn_handler, +}; --=20 2.34.1 From nobody Thu Dec 18 19:26:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD0FFC46CA1 for ; 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Wed, 11 Oct 2023 22:15:41 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([106.51.83.242]) by smtp.gmail.com with ESMTPSA id s18-20020a17090330d200b001b9d95945afsm851309plc.155.2023.10.11.22.15.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 22:15:40 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Greg Kroah-Hartman , Jiri Slaby Cc: Conor Dooley , Andrew Jones , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v2 5/8] RISC-V: Add inline version of sbi_console_putchar/getchar() functions Date: Thu, 12 Oct 2023 10:45:06 +0530 Message-Id: <20231012051509.738750-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231012051509.738750-1-apatel@ventanamicro.com> References: <20231012051509.738750-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The functions sbi_console_putchar() and sbi_console_getchar() are not defined when CONFIG_RISCV_SBI_V01 is disabled so let us add inline version of these functions to avoid "#ifdef" on user side. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- arch/riscv/include/asm/sbi.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 12dfda6bb924..cbcefa344417 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -271,8 +271,13 @@ struct sbiret sbi_ecall(int ext, int fid, unsigned lon= g arg0, unsigned long arg3, unsigned long arg4, unsigned long arg5); =20 +#ifdef CONFIG_RISCV_SBI_V01 void sbi_console_putchar(int ch); int sbi_console_getchar(void); +#else +static inline void sbi_console_putchar(int ch) { } +static inline int sbi_console_getchar(void) { return -1; } +#endif long sbi_get_mvendorid(void); long sbi_get_marchid(void); long sbi_get_mimpid(void); --=20 2.34.1 From nobody Thu Dec 18 19:26:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 401AFCDB47E for ; Thu, 12 Oct 2023 05:16:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347079AbjJLFQn (ORCPT ); Thu, 12 Oct 2023 01:16:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36370 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377379AbjJLFQM (ORCPT ); Thu, 12 Oct 2023 01:16:12 -0400 Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F46BD45 for ; Wed, 11 Oct 2023 22:15:46 -0700 (PDT) Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1c9b70b9656so4365815ad.1 for ; Wed, 11 Oct 2023 22:15:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1697087745; x=1697692545; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/KVKi7QKmfPZrGchNrI6Bys6/KZCng6FE4wZxaod/J0=; b=DZaVzU0+AyzRJc3ufgtqqgJlOGxXQ3xades2Uu+jUbKqS15LvNRzis3rHmFBCFSNRG 6uxFbGimWp8FuwvYU5DZwy6hQG8VkS7CRwUWhIV7lv7/HhjQehL71w6bDjuPq4qVKYmY dquOpgiI3jkqDo9iQLKxKKuxKyc8CbTLhldvXQxnrjgOra/z5KK0U1HP26VFl9ofujqH 3EEcGu4sm/cF8k3mpcRVmjYhOe9qrz2vn1U9iX8lbCvj1M8DEW2xo7qO9aJWLvqm3qmW Wnk2XyWAqAblZoUQ3ZkzbQvrAHVeaD6yO9pBCoUxIOfyNbFOX0Rplf5j4S4VmRDW7AAb S7hg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697087745; x=1697692545; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/KVKi7QKmfPZrGchNrI6Bys6/KZCng6FE4wZxaod/J0=; b=V9jSBfHWo0QhzFLcpWv6hI3+FCX3AZALNSni8I8yIEXcmmgT4T1pktWKXcGw6/Byj3 M3Uw27oiKJZv9qx7cKhrhanskx4izJ2MplzwISRTJCn5bQ2KJ9w0N5uvHxV7lKQnIFaE u3iDkNRUZwFKJfiQwJBPyOHdxt0/ffmoBBlz8wjNQk/NdvNafFitf3ao7Wxd/vk/0kq3 nPc8o3BdGYuHdN4C/ricpSMD5jaJGQ5JxeaoY1ZGOzeSxnle1qqsl714ZERHhFCLKfOb 3V15zs2/wDrMxEN8JkhxKIrLRivINSAosAAljsEWKpDU61PLVIJxKy3UN/pUJc8CLFXR dGhg== X-Gm-Message-State: AOJu0YzDMmN+H+L19/CrerPVCf1AB+rxU3m9R6W31GQfUh5eFhULm+Xl Ns2wL6C5htl1FmhcU+S0A7hHcQ== X-Google-Smtp-Source: AGHT+IGQA5WgnUWZWzG9GzMA7WhXboUt0Cn4w+hL60tDRhhBnvH97ndWcYP/2d/cQ1fXpGrnegy9iQ== X-Received: by 2002:a17:903:278e:b0:1c9:dc52:9d69 with SMTP id jw14-20020a170903278e00b001c9dc529d69mr1250864plb.64.1697087745576; Wed, 11 Oct 2023 22:15:45 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([106.51.83.242]) by smtp.gmail.com with ESMTPSA id s18-20020a17090330d200b001b9d95945afsm851309plc.155.2023.10.11.22.15.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 22:15:45 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Greg Kroah-Hartman , Jiri Slaby Cc: Conor Dooley , Andrew Jones , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v2 6/8] tty/serial: Add RISC-V SBI debug console based earlycon Date: Thu, 12 Oct 2023 10:45:07 +0530 Message-Id: <20231012051509.738750-7-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231012051509.738750-1-apatel@ventanamicro.com> References: <20231012051509.738750-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We extend the existing RISC-V SBI earlycon support to use the new RISC-V SBI debug console extension. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- drivers/tty/serial/Kconfig | 2 +- drivers/tty/serial/earlycon-riscv-sbi.c | 32 +++++++++++++++++++++---- 2 files changed, 29 insertions(+), 5 deletions(-) diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index bdc568a4ab66..cec46091a716 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -87,7 +87,7 @@ config SERIAL_EARLYCON_SEMIHOST =20 config SERIAL_EARLYCON_RISCV_SBI bool "Early console using RISC-V SBI" - depends on RISCV_SBI_V01 + depends on RISCV_SBI select SERIAL_CORE select SERIAL_CORE_CONSOLE select SERIAL_EARLYCON diff --git a/drivers/tty/serial/earlycon-riscv-sbi.c b/drivers/tty/serial/e= arlycon-riscv-sbi.c index 27afb0b74ea7..c21cdef254e7 100644 --- a/drivers/tty/serial/earlycon-riscv-sbi.c +++ b/drivers/tty/serial/earlycon-riscv-sbi.c @@ -15,17 +15,41 @@ static void sbi_putc(struct uart_port *port, unsigned c= har c) sbi_console_putchar(c); } =20 -static void sbi_console_write(struct console *con, - const char *s, unsigned n) +static void sbi_0_1_console_write(struct console *con, + const char *s, unsigned int n) { struct earlycon_device *dev =3D con->data; uart_console_write(&dev->port, s, n, sbi_putc); } =20 +static void sbi_dbcn_console_write(struct console *con, + const char *s, unsigned int n) +{ + phys_addr_t pa =3D __pa(s); + + if (IS_ENABLED(CONFIG_32BIT)) + sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE, + n, lower_32_bits(pa), upper_32_bits(pa), 0, 0, 0); + else + sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE, + n, pa, 0, 0, 0, 0); +} + static int __init early_sbi_setup(struct earlycon_device *device, const char *opt) { - device->con->write =3D sbi_console_write; - return 0; + int ret =3D 0; + + if ((sbi_spec_version >=3D sbi_mk_version(2, 0)) && + (sbi_probe_extension(SBI_EXT_DBCN) > 0)) { + device->con->write =3D sbi_dbcn_console_write; + } else { + if (IS_ENABLED(CONFIG_RISCV_SBI_V01)) + device->con->write =3D sbi_0_1_console_write; + else + ret =3D -ENODEV; + } + + return ret; } EARLYCON_DECLARE(sbi, early_sbi_setup); --=20 2.34.1 From nobody Thu Dec 18 19:26:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B67E0CDB46E for ; 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Wed, 11 Oct 2023 22:15:50 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([106.51.83.242]) by smtp.gmail.com with ESMTPSA id s18-20020a17090330d200b001b9d95945afsm851309plc.155.2023.10.11.22.15.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 22:15:49 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Greg Kroah-Hartman , Jiri Slaby Cc: Conor Dooley , Andrew Jones , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Atish Patra , Anup Patel Subject: [PATCH v2 7/8] tty: Add SBI debug console support to HVC SBI driver Date: Thu, 12 Oct 2023 10:45:08 +0530 Message-Id: <20231012051509.738750-8-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231012051509.738750-1-apatel@ventanamicro.com> References: <20231012051509.738750-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Atish Patra RISC-V SBI specification supports advanced debug console support via SBI DBCN extension. Extend the HVC SBI driver to support it. Signed-off-by: Atish Patra Signed-off-by: Anup Patel --- drivers/tty/hvc/Kconfig | 2 +- drivers/tty/hvc/hvc_riscv_sbi.c | 76 ++++++++++++++++++++++++++++++--- 2 files changed, 70 insertions(+), 8 deletions(-) diff --git a/drivers/tty/hvc/Kconfig b/drivers/tty/hvc/Kconfig index 4f9264d005c0..6e05c5c7bca1 100644 --- a/drivers/tty/hvc/Kconfig +++ b/drivers/tty/hvc/Kconfig @@ -108,7 +108,7 @@ config HVC_DCC_SERIALIZE_SMP =20 config HVC_RISCV_SBI bool "RISC-V SBI console support" - depends on RISCV_SBI_V01 + depends on RISCV_SBI select HVC_DRIVER help This enables support for console output via RISC-V SBI calls, which diff --git a/drivers/tty/hvc/hvc_riscv_sbi.c b/drivers/tty/hvc/hvc_riscv_sb= i.c index 31f53fa77e4a..da318d7f55c5 100644 --- a/drivers/tty/hvc/hvc_riscv_sbi.c +++ b/drivers/tty/hvc/hvc_riscv_sbi.c @@ -39,21 +39,83 @@ static int hvc_sbi_tty_get(uint32_t vtermno, char *buf,= int count) return i; } =20 -static const struct hv_ops hvc_sbi_ops =3D { +static const struct hv_ops hvc_sbi_v01_ops =3D { .get_chars =3D hvc_sbi_tty_get, .put_chars =3D hvc_sbi_tty_put, }; =20 -static int __init hvc_sbi_init(void) +static int hvc_sbi_dbcn_tty_put(uint32_t vtermno, const char *buf, int cou= nt) { - return PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_ops, 16)); + phys_addr_t pa; + struct sbiret ret; + + if (is_vmalloc_addr(buf)) + pa =3D page_to_phys(vmalloc_to_page(buf)) + offset_in_page(buf); + else + pa =3D __pa(buf); + + if (IS_ENABLED(CONFIG_32BIT)) + ret =3D sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE, + count, lower_32_bits(pa), upper_32_bits(pa), + 0, 0, 0); + else + ret =3D sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE, + count, pa, 0, 0, 0, 0); + if (ret.error) + return 0; + + return count; } -device_initcall(hvc_sbi_init); =20 -static int __init hvc_sbi_console_init(void) +static int hvc_sbi_dbcn_tty_get(uint32_t vtermno, char *buf, int count) { - hvc_instantiate(0, 0, &hvc_sbi_ops); + phys_addr_t pa; + struct sbiret ret; + + if (is_vmalloc_addr(buf)) + pa =3D page_to_phys(vmalloc_to_page(buf)) + offset_in_page(buf); + else + pa =3D __pa(buf); + + if (IS_ENABLED(CONFIG_32BIT)) + ret =3D sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_READ, + count, lower_32_bits(pa), upper_32_bits(pa), + 0, 0, 0); + else + ret =3D sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_READ, + count, pa, 0, 0, 0, 0); + if (ret.error) + return 0; + + return ret.value; +} + +static const struct hv_ops hvc_sbi_dbcn_ops =3D { + .put_chars =3D hvc_sbi_dbcn_tty_put, + .get_chars =3D hvc_sbi_dbcn_tty_get, +}; + +static int __init hvc_sbi_init(void) +{ + int err; + + if ((sbi_spec_version >=3D sbi_mk_version(2, 0)) && + (sbi_probe_extension(SBI_EXT_DBCN) > 0)) { + err =3D PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_dbcn_ops, 16)); + if (err) + return err; + hvc_instantiate(0, 0, &hvc_sbi_dbcn_ops); + } else { + if (IS_ENABLED(CONFIG_RISCV_SBI_V01)) { + err =3D PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_v01_ops, 16)); + if (err) + return err; + hvc_instantiate(0, 0, &hvc_sbi_v01_ops); + } else { + return -ENODEV; + } + } =20 return 0; } -console_initcall(hvc_sbi_console_init); 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Wed, 11 Oct 2023 22:15:54 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Greg Kroah-Hartman , Jiri Slaby Cc: Conor Dooley , Andrew Jones , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v2 8/8] RISC-V: Enable SBI based earlycon support Date: Thu, 12 Oct 2023 10:45:09 +0530 Message-Id: <20231012051509.738750-9-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231012051509.738750-1-apatel@ventanamicro.com> References: <20231012051509.738750-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Let us enable SBI based earlycon support in defconfigs for both RV32 and RV64 so that "earlycon=3Dsbi" can be used again. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- arch/riscv/configs/defconfig | 1 + arch/riscv/configs/rv32_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index ab86ec3b9eab..f82700da0056 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -132,6 +132,7 @@ CONFIG_SERIAL_8250_CONSOLE=3Dy CONFIG_SERIAL_8250_DW=3Dy CONFIG_SERIAL_OF_PLATFORM=3Dy CONFIG_SERIAL_SH_SCI=3Dy +CONFIG_SERIAL_EARLYCON_RISCV_SBI=3Dy CONFIG_VIRTIO_CONSOLE=3Dy CONFIG_HW_RANDOM=3Dy CONFIG_HW_RANDOM_VIRTIO=3Dy diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_de= fconfig index 89b601e253a6..5721af39afd1 100644 --- a/arch/riscv/configs/rv32_defconfig +++ b/arch/riscv/configs/rv32_defconfig @@ -66,6 +66,7 @@ CONFIG_INPUT_MOUSEDEV=3Dy CONFIG_SERIAL_8250=3Dy CONFIG_SERIAL_8250_CONSOLE=3Dy CONFIG_SERIAL_OF_PLATFORM=3Dy +CONFIG_SERIAL_EARLYCON_RISCV_SBI=3Dy CONFIG_VIRTIO_CONSOLE=3Dy CONFIG_HW_RANDOM=3Dy CONFIG_HW_RANDOM_VIRTIO=3Dy --=20 2.34.1