From nobody Fri Jan 2 13:50:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B625CDB47E for ; Wed, 11 Oct 2023 21:59:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376482AbjJKV7Q (ORCPT ); Wed, 11 Oct 2023 17:59:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40158 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233743AbjJKV7I (ORCPT ); Wed, 11 Oct 2023 17:59:08 -0400 Received: from vps.xff.cz (vps.xff.cz [195.181.215.36]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0AF95B7; Wed, 11 Oct 2023 14:59:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xff.cz; s=mail; t=1697061542; bh=k36YQDivoyTeV5suOtLF8HApcFeZ48PWUcsrgNwF6lA=; h=From:To:Cc:Subject:Date:References:From; b=spB6Xj81UicAVLZX6kjnJ5464qoDWDYCuYm4++7nie1/f04nqyb/ZbgoQtWIBLb/T a8PLACvNlZmo1NejfPil2T9x7NR5IOIVj86AQv0D5eWIS2LqcQLrEsAPC22YoVshql d7mM9InyLGHaooNJJ/HdFYNns4mBxbowIUYxkbYQ= From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Ondrej Jirman , Jagan Teki , Jonas Karlman , Chris Morgan , Sebastian Reichel , Kever Yang , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/2] arm64: dts: rk3588-quartzpro64: Add QuartzPro64 SBC device tree Date: Wed, 11 Oct 2023 23:58:45 +0200 Message-ID: <20231011215856.2082241-3-megi@xff.cz> In-Reply-To: <20231011215856.2082241-1-megi@xff.cz> References: <20231011215856.2082241-1-megi@xff.cz> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ondrej Jirman QuartzPro64 dev board features: - RK3588 SoC - 16 GiB LPDDR4 RAM - 2x RK806 PMIC - RTC chip - eMMC, uSD card interface - 2x GMAC (one is PCIe connected) - SATA port - 2x USB 2.0 host only ports - 1x usb 3.0 host only port - 1x Type-C port (USB 3.0 + Alt-DP), TCPM support - 1x PCIe 3.0 4x slot - Audio codec (ES8388) + power amps - WiFi/Bluetooth - Power and work LEDs - 4 adc ladder buttons, 1 power button, 1 maskrom button Signed-off-by: Ondrej Jirman --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3588-quartzpro64.dts | 1137 +++++++++++++++++ 2 files changed, 1138 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index e7728007fd1b..e6ad0a30d6c8 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -101,6 +101,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-edgeble-neu6a-i= o.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-edgeble-neu6b-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-nanopc-t6.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-quartzpro64.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-rock-5b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-indiedroid-nova.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-khadas-edge2.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts b/arch/arm= 64/boot/dts/rockchip/rk3588-quartzpro64.dts new file mode 100644 index 000000000000..5c59f9571dce --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts @@ -0,0 +1,1137 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Ond=C5=99ej Jirman + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "rk3588.dtsi" + +/ { + model =3D "PINE64 QuartzPro64"; + compatible =3D "pine64,quartzpro64", "rockchip,rk3588"; + + aliases { + mmc0 =3D &sdhci; + mmc1 =3D &sdmmc; + serial2 =3D &uart2; + }; + + chosen { + stdout-path =3D "serial2:1500000n8"; + }; + + adc-keys-0 { + compatible =3D "adc-keys"; + io-channels =3D <&saradc 0>; + io-channel-names =3D "buttons"; + keyup-threshold-microvolt =3D <1800000>; + poll-interval =3D <100>; + + button-maskrom { + label =3D "Mask Rom"; + linux,code =3D ; + press-threshold-microvolt =3D <393>; + }; + }; + + adc-keys-1 { + compatible =3D "adc-keys"; + io-channels =3D <&saradc 1>; + io-channel-names =3D "buttons"; + keyup-threshold-microvolt =3D <1800000>; + poll-interval =3D <100>; + + button-volume-up { + label =3D "V+/REC"; + linux,code =3D ; + press-threshold-microvolt =3D <17821>; + }; + + button-volume-down { + label =3D "V-"; + linux,code =3D ; + press-threshold-microvolt =3D <415384>; + }; + + button-menu { + label =3D "MENU"; + linux,code =3D ; + press-threshold-microvolt =3D <890909>; + }; + + button-esc { + label =3D "ESC"; + linux,code =3D ; + press-threshold-microvolt =3D <1233962>; + }; + }; + + headphone_amp: audio-amplifier-headphone { + compatible =3D "simple-audio-amplifier"; + enable-gpios =3D <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + sound-name-prefix =3D "Headphones Amp"; + }; + + speaker_amp: audio-amplifier-speaker { + compatible =3D "simple-audio-amplifier"; + enable-gpios =3D <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + sound-name-prefix =3D "Speaker Amp"; + }; + + leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&led_pins>; + + led-1 { + color =3D ; + function =3D LED_FUNCTION_INDICATOR; + gpios =3D <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + }; + }; + + sound { + compatible =3D "simple-audio-card"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hp_detect>; + simple-audio-card,name =3D "Analog"; + simple-audio-card,aux-devs =3D <&speaker_amp>, <&headphone_amp>; + simple-audio-card,format =3D "i2s"; + simple-audio-card,mclk-fs =3D <256>; + simple-audio-card,hp-det-gpio =3D <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + simple-audio-card,bitclock-master =3D <&daicpu>; + simple-audio-card,frame-master =3D <&daicpu>; + /* SARADC_IN3 is used as MIC detection / key input */ + + simple-audio-card,widgets =3D + "Microphone", "Onboard Microphone", + "Microphone", "Microphone Jack", + "Speaker", "Speaker", + "Headphone", "Headphones"; + + simple-audio-card,routing =3D + "Headphones", "LOUT1", + "Headphones", "ROUT1", + "Speaker", "LOUT2", + "Speaker", "ROUT2", + + "Headphones", "Headphones Amp OUTL", + "Headphones", "Headphones Amp OUTR", + "Headphones Amp INL", "LOUT1", + "Headphones Amp INR", "ROUT1", + + "Speaker", "Speaker Amp OUTL", + "Speaker", "Speaker Amp OUTR", + "Speaker Amp INL", "LOUT2", + "Speaker Amp INR", "ROUT2", + + /* single ended signal to LINPUT1 */ + "LINPUT1", "Microphone Jack", + "RINPUT1", "Microphone Jack", + /* differential signal */ + "LINPUT2", "Onboard Microphone", + "RINPUT2", "Onboard Microphone"; + + daicpu: simple-audio-card,cpu { + sound-dai =3D <&i2s0_8ch>; + system-clock-frequency =3D <12288000>; + }; + + daicodec: simple-audio-card,codec { + sound-dai =3D <&es8388>; + system-clock-frequency =3D <12288000>; + }; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + }; + + vcc3v3_bt: vcc3v3-bt-regulator { + compatible =3D "regulator-fixed"; + enable-active-high; + gpios =3D <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + regulator-name =3D "vcc3v3_bt"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + startup-delay-us =3D <50000>; + vin-supply =3D <&vcc_3v3_s0>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30-regulator { + compatible =3D "regulator-fixed"; + enable-active-high; + gpios =3D <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + regulator-name =3D "vcc3v3_pcie30"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + startup-delay-us =3D <5000>; + vin-supply =3D <&vcc12v_dcin>; + }; + + vcc3v3_wf: vcc3v3-wf-regulator { + compatible =3D "regulator-fixed"; + enable-active-high; + gpios =3D <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; + regulator-name =3D "vcc3v3_wf"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + startup-delay-us =3D <50000>; + vin-supply =3D <&vcc_3v3_s0>; + }; + + vcc4v0_sys: vcc4v0-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc4v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <4000000>; + regulator-max-microvolt =3D <4000000>; + vin-supply =3D <&vcc12v_dcin>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc5v0_host_en>; + regulator-name =3D "vcc5v0_host"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_usb>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc12v_dcin>; + }; +}; + +&combphy0_ps { + status =3D "okay"; +}; + +&combphy1_ps { + status =3D "okay"; +}; + +&combphy2_psu { + status =3D "okay"; +}; + +&cpu_b0 { + cpu-supply =3D <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply =3D <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply =3D <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply =3D <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&gmac0 { + clock_in_out =3D "output"; + phy-handle =3D <&rgmii_phy>; + phy-mode =3D "rgmii-rxid"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + rx_delay =3D <0x00>; + tx_delay =3D <0x43>; + status =3D "okay"; +}; + +&i2c2 { + status =3D "okay"; + + hym8563: rtc@51 { + compatible =3D "haoyu,hym8563"; + reg =3D <0x51>; + #clock-cells =3D <0>; + clock-output-names =3D "hym8563"; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hym8563_int>; + wakeup-source; + }; +}; + +&i2c7 { + status =3D "okay"; + + es8388: audio-codec@11 { + compatible =3D "everest,es8388"; + reg =3D <0x11>; + assigned-clocks =3D <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates =3D <12288000>; + clocks =3D <&cru I2S0_8CH_MCLKOUT>; + clock-names =3D "mclk"; + AVDD-supply =3D <&avcc_1v8_codec_s0>; + DVDD-supply =3D <&avcc_1v8_codec_s0>; + HPVDD-supply =3D <&vcc_3v3_s0>; + PVDD-supply =3D <&vcc_3v3_s0>; + #sound-dai-cells =3D <0>; + }; +}; + +&i2s0_8ch { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status =3D "okay"; +}; + +&mdio0 { + rgmii_phy: ethernet-phy@1 { + /* RTL8211F */ + compatible =3D "ethernet-phy-id001c.c916"; + reg =3D <0x1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rtl8211f_rst>; + reset-assert-us =3D <20000>; + reset-deassert-us =3D <100000>; + reset-gpios =3D <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins =3D <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + led_pins: led-pins { + rockchip,pins =3D <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rtl8111 { + rtl8111_isolate: rtl8111-isolate { + rockchip,pins =3D <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rtl8211f { + rtl8211f_rst: rtl8211f-rst { + rockchip,pins =3D <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + }; + + sound { + hp_detect: hp-detect { + rockchip,pins =3D <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins =3D <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +/* WIFI */ +&pcie2x1l0 { + reset-gpios =3D <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_wf>; + status =3D "okay"; +}; + +/* GMAC1 */ +&pcie2x1l1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rtl8111_isolate>; + reset-gpios =3D <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + status =3D "okay"; +}; + +&pcie30phy { + status =3D "okay"; +}; + +&pcie3x4 { + reset-gpios =3D <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_pcie30>; + status =3D "okay"; +}; + +&saradc { + vref-supply =3D <&vcc_1v8_s0>; + status =3D "okay"; +}; + +&sata0 { + status =3D "okay"; +}; + +&sdhci { + bus-width =3D <8>; + no-sdio; + no-sd; + non-removable; + max-frequency =3D <150000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status =3D "okay"; +}; + +&sdmmc { + bus-width =3D <4>; + cap-sd-highspeed; + cd-gpios =3D <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency =3D <150000000>; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply =3D <&vcc_3v3_s3>; + vqmmc-supply =3D <&vccio_sd_s0>; + status =3D "okay"; +}; + +&spi2 { + assigned-clocks =3D <&cru CLK_SPI2>; + assigned-clock-rates =3D <200000000>; + num-cs =3D <2>; + status =3D "okay"; + + pmic@0 { + compatible =3D "rockchip,rk806"; + reg =3D <0x0>; + #gpio-cells =3D <2>; + gpio-controller; + interrupt-parent =3D <&gpio0>; + interrupts =3D <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 =3D <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + pinctrl-names =3D "default"; + spi-max-frequency =3D <1000000>; + + vcc1-supply =3D <&vcc4v0_sys>; + vcc2-supply =3D <&vcc4v0_sys>; + vcc3-supply =3D <&vcc4v0_sys>; + vcc4-supply =3D <&vcc4v0_sys>; + vcc5-supply =3D <&vcc4v0_sys>; + vcc6-supply =3D <&vcc4v0_sys>; + vcc7-supply =3D <&vcc4v0_sys>; + vcc8-supply =3D <&vcc4v0_sys>; + vcc9-supply =3D <&vcc4v0_sys>; + vcc10-supply =3D <&vcc4v0_sys>; + vcc11-supply =3D <&vcc_2v0_pldo_s3>; + vcc12-supply =3D <&vcc4v0_sys>; + vcc13-supply =3D <&vcc_1v1_nldo_s3>; + vcc14-supply =3D <&vcc_1v1_nldo_s3>; + vcca-supply =3D <&vcc4v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins =3D "gpio_pwrctrl1"; + function =3D "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: dcdc-reg1 { + regulator-name =3D "vdd_gpu_s0"; + regulator-boot-on; + regulator-enable-ramp-delay =3D <400>; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_s0: dcdc-reg2 { + regulator-name =3D "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name =3D "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <750000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vdd_vdenc_s0: dcdc-reg4 { + regulator-name =3D "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + + }; + + vdd_gpu_mem_s0: dcdc-reg5 { + regulator-name =3D "vdd_gpu_mem_s0"; + regulator-boot-on; + regulator-enable-ramp-delay =3D <400>; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + + }; + + vdd_npu_mem_s0: dcdc-reg6 { + regulator-name =3D "vdd_npu_mem_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name =3D "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <2000000>; + regulator-max-microvolt =3D <2000000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <2000000>; + }; + }; + + vdd_vdenc_mem_s0: dcdc-reg8 { + regulator-name =3D "vdd_vdenc_mem_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd2_ddr_s3: dcdc-reg9 { + regulator-name =3D "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v1_nldo_s3: dcdc-reg10 { + regulator-name =3D "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1100000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-name =3D "avcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd1_1v8_ddr_s3: pldo-reg2 { + regulator-name =3D "vdd1_1v8_ddr_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + avcc_1v8_codec_s0: pldo-reg3 { + regulator-name =3D "avcc_1v8_codec_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s3: pldo-reg4 { + regulator-name =3D "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name =3D "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: pldo-reg6 { + regulator-name =3D "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name =3D "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + /* reserved for LPDDR5, unused? */ + vdd2l_0v9_ddr_s3: nldo-reg2 { + regulator-name =3D "vdd2l_0v9_ddr_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vdd_0v75_hdmi_edp_s0: nldo-reg3 { + regulator-name =3D "vdd_0v75_hdmi_edp_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_0v75_s0: nldo-reg4 { + regulator-name =3D "avdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg5 { + regulator-name =3D "vdd_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + pmic@1 { + compatible =3D "rockchip,rk806"; + reg =3D <0x01>; + #gpio-cells =3D <2>; + gpio-controller; + interrupt-parent =3D <&gpio0>; + interrupts =3D <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 =3D <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>, + <&rk806_slave_dvs3_null>; + pinctrl-names =3D "default"; + spi-max-frequency =3D <1000000>; + + vcc1-supply =3D <&vcc4v0_sys>; + vcc2-supply =3D <&vcc4v0_sys>; + vcc3-supply =3D <&vcc4v0_sys>; + vcc4-supply =3D <&vcc4v0_sys>; + vcc5-supply =3D <&vcc4v0_sys>; + vcc6-supply =3D <&vcc4v0_sys>; + vcc7-supply =3D <&vcc4v0_sys>; + vcc8-supply =3D <&vcc4v0_sys>; + vcc9-supply =3D <&vcc4v0_sys>; + vcc10-supply =3D <&vcc4v0_sys>; + vcc11-supply =3D <&vcc_2v0_pldo_s3>; + vcc12-supply =3D <&vcc4v0_sys>; + vcc13-supply =3D <&vcc_1v1_nldo_s3>; + vcc14-supply =3D <&vcc_2v0_pldo_s3>; + vcca-supply =3D <&vcc4v0_sys>; + + rk806_slave_dvs1_null: dvs1-null-pins { + pins =3D "gpio_pwrctrl1"; + function =3D "pin_fun0"; + }; + + rk806_slave_dvs2_null: dvs2-null-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun0"; + }; + + rk806_slave_dvs3_null: dvs3-null-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun0"; + }; + + regulators { + vdd_cpu_big1_s0: dcdc-reg1 { + regulator-name =3D "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <1050000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big0_s0: dcdc-reg2 { + regulator-name =3D "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <1050000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg3 { + regulator-name =3D "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: dcdc-reg4 { + regulator-name =3D "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_mem_s0: dcdc-reg5 { + regulator-name =3D "vdd_cpu_big1_mem_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <1050000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + + vdd_cpu_big0_mem_s0: dcdc-reg6 { + regulator-name =3D "vdd_cpu_big0_mem_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <1050000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: dcdc-reg7 { + regulator-name =3D "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_mem_s0: dcdc-reg8 { + regulator-name =3D "vdd_cpu_lit_mem_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name =3D "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg10 { + regulator-name =3D "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <900000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* reserved, unused? */ + vcc_1v8_cam_s0: pldo-reg1 { + regulator-name =3D "vcc_1v8_cam_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd1v8_ddr_pll_s0: pldo-reg2 { + regulator-name =3D "avdd1v8_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_1v8_pll_s0: pldo-reg3 { + regulator-name =3D "vdd_1v8_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* reserved, unused? */ + vcc_3v3_sd_s0: pldo-reg4 { + regulator-name =3D "vcc_3v3_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* reserved, unused? */ + vcc_2v8_cam_s0: pldo-reg5 { + regulator-name =3D "vcc_2v8_cam_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* unused */ + pldo6_s3: pldo-reg6 { + regulator-name =3D "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdd_0v75_pll_s0: nldo-reg1 { + regulator-name =3D "vdd_0v75_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-name =3D "vdd_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_0v85_s0: nldo-reg3 { + regulator-name =3D "avdd_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* reserved, unused */ + avdd_1v2_cam_s0: nldo-reg4 { + regulator-name =3D "avdd_1v2_cam_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_1v2_s0: nldo-reg5 { + regulator-name =3D "avdd_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status =3D "okay"; +}; + +&u2phy2 { + status =3D "okay"; +}; + +&u2phy2_host { + phy-supply =3D <&vcc5v0_host>; + status =3D "okay"; +}; + +&u2phy3 { + status =3D "okay"; +}; + +&u2phy3_host { + phy-supply =3D <&vcc5v0_host>; + status =3D "okay"; +}; + +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart2m0_xfer>; + status =3D "okay"; +}; + +&usb_host0_ehci { + status =3D "okay"; +}; + +&usb_host0_ohci { + status =3D "okay"; +}; + +&usb_host1_ehci { + status =3D "okay"; +}; + +&usb_host1_ohci { + status =3D "okay"; +}; --=20 2.42.0