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([2a01:e0a:999:a3a0:9134:b302:d8b:a200]) by smtp.gmail.com with ESMTPSA id a4-20020a05600c224400b003fe2b081661sm18945715wmm.30.2023.10.11.04.19.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 04:19:14 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley Subject: [PATCH v1 01/13] riscv: fatorize hwprobe ISA extension reporting Date: Wed, 11 Oct 2023 13:14:26 +0200 Message-ID: <20231011111438.909552-2-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231011111438.909552-1-cleger@rivosinc.com> References: <20231011111438.909552-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Factorize ISA extension reporting by using a macro rather than copy/pasting extension names. This will allow adding new extensions more easily. Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- arch/riscv/kernel/sys_riscv.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 473159b5f303..5ce593ce07a4 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -145,20 +145,18 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pa= ir, for_each_cpu(cpu, cpus) { struct riscv_isainfo *isainfo =3D &hart_isa[cpu]; =20 - if (riscv_isa_extension_available(isainfo->isa, ZBA)) - pair->value |=3D RISCV_HWPROBE_EXT_ZBA; - else - missing |=3D RISCV_HWPROBE_EXT_ZBA; - - if (riscv_isa_extension_available(isainfo->isa, ZBB)) - pair->value |=3D RISCV_HWPROBE_EXT_ZBB; - else - missing |=3D RISCV_HWPROBE_EXT_ZBB; - - if (riscv_isa_extension_available(isainfo->isa, ZBS)) - pair->value |=3D RISCV_HWPROBE_EXT_ZBS; - else - missing |=3D RISCV_HWPROBE_EXT_ZBS; +#define CHECK_ISA_EXT(__ext) \ + do { \ + if (riscv_isa_extension_available(isainfo->isa, __ext)) \ + pair->value |=3D RISCV_HWPROBE_EXT_##__ext; \ + else \ + missing |=3D RISCV_HWPROBE_EXT_##__ext; \ + } while (false) \ + + CHECK_ISA_EXT(ZBA); + CHECK_ISA_EXT(ZBB); + CHECK_ISA_EXT(ZBS); +#undef CHECK_ISA_EXT } =20 /* Now turn off reporting features if any CPU is missing it. */ --=20 2.42.0 From nobody Fri Jan 2 13:27:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC074CD6E5A for ; Wed, 11 Oct 2023 11:19:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346393AbjJKLTv (ORCPT ); Wed, 11 Oct 2023 07:19:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34934 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345736AbjJKLTT (ORCPT ); Wed, 11 Oct 2023 07:19:19 -0400 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F3D64B8 for ; Wed, 11 Oct 2023 04:19:17 -0700 (PDT) Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-405d70d19bcso10032685e9.0 for ; Wed, 11 Oct 2023 04:19:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697023156; x=1697627956; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0IIANjo80zFqhbyLhR/zqKY0ZEpCfYarjbj4J5oFHCU=; b=EyJoq/pX4QSeF/AhVnio1RBlLrkrSHENsqPTJCwKYFgEgJiLkEonaeVnFQBAGFmDrD BYZaxIJAj1mVIiRNoHrA8bFdkUQ5JIo3ZTk0GKVt3UIf3TvkgYp/n9IIe2qo5giK5KbC jEzJlfxJvrF+rO560o0cwmJ223Iloqckc/6Kq+43ryrv3NBl+LmLBk+D/fFo7DtCO2g+ sbfO3huHpBtmbaGPjokeEgwm/dsGK7ZRNy3XXVwy18AEdSQ4lqAyqp4sBwpQwo+/xdAP mbNqoFTvBzd9zcFs+Zy/eWyNPkNY8wAFSz6baOa+1gu1htFZ5cpNfiRI4m7MqNcVlBnZ 6p8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697023156; x=1697627956; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0IIANjo80zFqhbyLhR/zqKY0ZEpCfYarjbj4J5oFHCU=; b=umeitMuCV0X0N58GoHpO+L9zChYdOzk4K/Nrd0UeBqe88xTm4LRDnOrnCikrZ/3Rgp DHO2w3K8sMnaxnMPH55WvsXYQDdMfdhBd+eVeT8qPUF7o1yooyNvzoyxlEmohPAnF3bg HqXI4SNS6/HPOwYzFvjtjjsDwLrIkkXUmLTOhwwAoQry2m2weiZtz6ok8CmjZ5JPJY80 Qgtuw3kkGsZIcmEHM8yK+lv9KfybOqJBUutCajXAC1s6guMoLS4Xtr9LiQVLvpgMUfhK IS4yrVaBGvrQFJqdlcn2HWQmAM9fDDQajIkzqoOjofhkBEi3bjY0E8elTQBtq0KWTDK9 DxmA== X-Gm-Message-State: AOJu0YwG6LkMFUQPLLEZQSZoDqdUpS9u5YUhPFnhNuTPHKkNstobJpys gAVaJeFw6RQnds7F9v+4Hill9w== X-Google-Smtp-Source: AGHT+IG/DnLus+yEPlI6bYFmkh9ll2Q+J+N/2Mo1GvXrndFzK7mO/7rr0oVK3NtPpfUMi8b7II3bfA== X-Received: by 2002:a7b:cc99:0:b0:401:7d3b:cc84 with SMTP id p25-20020a7bcc99000000b004017d3bcc84mr18354424wma.0.1697023155672; Wed, 11 Oct 2023 04:19:15 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:9134:b302:d8b:a200]) by smtp.gmail.com with ESMTPSA id a4-20020a05600c224400b003fe2b081661sm18945715wmm.30.2023.10.11.04.19.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 04:19:15 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley Subject: [PATCH v1 02/13] riscv: add ISA extension probing for Zv* extensions Date: Wed, 11 Oct 2023 13:14:27 +0200 Message-ID: <20231011111438.909552-3-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231011111438.909552-1-cleger@rivosinc.com> References: <20231011111438.909552-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add probing of some Zv* ISA extensions that are mentioned in "RISC-V Cryptography Extensions Volume II" [1]. These ISA extensions are the following: - Zvbb: Vector Basic Bit-manipulation - Zvbc: Vector Carryless Multiplication - Zvkb: Vector Cryptography Bit-manipulation - Zvkg: Vector GCM/GMAC. - Zvkned: NIST Suite: Vector AES Block Cipher - Zvknh[ab]: NIST Suite: Vector SHA-2 Secure Hash - Zvksed: ShangMi Suite: SM4 Block Cipher - Zvksh: ShangMi Suite: SM3 Secure Hash - Zvkn: NIST Algorithm Suite - Zvknc: NIST Algorithm Suite with carryless multiply - Zvkng: NIST Algorithm Suite with GCM. - Zvks: ShangMi Algorithm Suite - Zvksc: ShangMi Algorithm Suite with carryless multiplication - Zvksg: ShangMi Algorithm Suite with GCM. - Zvkt: Vector Data-Independent Execution Latency. [1] https://drive.google.com/file/d/1gb9OLH-DhbCgWp7VwpPOVrrY6f3oSJLL/view Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- arch/riscv/include/asm/hwcap.h | 16 ++++++++++++++++ arch/riscv/kernel/cpufeature.c | 16 ++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index b7b58258f6c7..4e46981ac6c8 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -58,6 +58,22 @@ #define RISCV_ISA_EXT_ZICSR 40 #define RISCV_ISA_EXT_ZIFENCEI 41 #define RISCV_ISA_EXT_ZIHPM 42 +#define RISCV_ISA_EXT_ZVBB 43 +#define RISCV_ISA_EXT_ZVBC 44 +#define RISCV_ISA_EXT_ZVKB 45 +#define RISCV_ISA_EXT_ZVKG 46 +#define RISCV_ISA_EXT_ZVKN 47 +#define RISCV_ISA_EXT_ZVKNC 48 +#define RISCV_ISA_EXT_ZVKNED 49 +#define RISCV_ISA_EXT_ZVKNG 50 +#define RISCV_ISA_EXT_ZVKNHA 51 +#define RISCV_ISA_EXT_ZVKNHB 52 +#define RISCV_ISA_EXT_ZVKS 53 +#define RISCV_ISA_EXT_ZVKSC 54 +#define RISCV_ISA_EXT_ZVKSED 55 +#define RISCV_ISA_EXT_ZVKSH 56 +#define RISCV_ISA_EXT_ZVKSG 57 +#define RISCV_ISA_EXT_ZVKT 58 =20 #define RISCV_ISA_EXT_MAX 64 =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 1cfbba65d11a..859d647f3ced 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -174,6 +174,22 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), + __RISCV_ISA_EXT_DATA(zvbb, RISCV_ISA_EXT_ZVBB), + __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC), + __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB), + __RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG), + __RISCV_ISA_EXT_DATA(zvkn, RISCV_ISA_EXT_ZVKN), + __RISCV_ISA_EXT_DATA(zvknc, RISCV_ISA_EXT_ZVKNC), + __RISCV_ISA_EXT_DATA(zvkned, RISCV_ISA_EXT_ZVKNED), + __RISCV_ISA_EXT_DATA(zvkng, RISCV_ISA_EXT_ZVKNG), + __RISCV_ISA_EXT_DATA(zvknha, RISCV_ISA_EXT_ZVKNHA), + __RISCV_ISA_EXT_DATA(zvknhb, RISCV_ISA_EXT_ZVKNHB), + __RISCV_ISA_EXT_DATA(zvks, RISCV_ISA_EXT_ZVKS), + __RISCV_ISA_EXT_DATA(zvksc, RISCV_ISA_EXT_ZVKSC), + __RISCV_ISA_EXT_DATA(zvksed, RISCV_ISA_EXT_ZVKSED), + __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH), + __RISCV_ISA_EXT_DATA(zvksg, RISCV_ISA_EXT_ZVKSG), + __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), --=20 2.42.0 From nobody Fri Jan 2 13:27:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27C2BCD6E5C for ; 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([2a01:e0a:999:a3a0:9134:b302:d8b:a200]) by smtp.gmail.com with ESMTPSA id a4-20020a05600c224400b003fe2b081661sm18945715wmm.30.2023.10.11.04.19.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 04:19:16 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley Subject: [PATCH v1 03/13] riscv: hwprobe: export Zv* ISA extensions Date: Wed, 11 Oct 2023 13:14:28 +0200 Message-ID: <20231011111438.909552-4-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231011111438.909552-1-cleger@rivosinc.com> References: <20231011111438.909552-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Export Zv* ISA extensions that were added in "RISC-V Cryptography Extensions Volume II" specification[1] through hwprobe. This adds support for the following instructions: - Zvbb: Vector Basic Bit-manipulation - Zvbc: Vector Carryless Multiplication - Zvkb: Vector Cryptography Bit-manipulation - Zvkg: Vector GCM/GMAC. - Zvkned: NIST Suite: Vector AES Block Cipher - Zvknh[ab]: NIST Suite: Vector SHA-2 Secure Hash - Zvksed: ShangMi Suite: SM4 Block Cipher - Zvksh: ShangMi Suite: SM3 Secure Hash - Zvkn: NIST Algorithm Suite - Zvknc: NIST Algorithm Suite with carryless multiply - Zvkng: NIST Algorithm Suite with GCM. - Zvks: ShangMi Algorithm Suite - Zvksc: ShangMi Algorithm Suite with carryless multiplication - Zvksg: ShangMi Algorithm Suite with GCM. - Zvkt: Vector Data-Independent Execution Latency. [1] https://drive.google.com/file/d/1gb9OLH-DhbCgWp7VwpPOVrrY6f3oSJLL/view Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- Documentation/riscv/hwprobe.rst | 48 +++++++++++++++++++++++++++ arch/riscv/include/uapi/asm/hwprobe.h | 16 +++++++++ arch/riscv/kernel/sys_riscv.c | 19 +++++++++++ 3 files changed, 83 insertions(+) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.= rst index a52996b22f75..edfed33669ea 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -77,6 +77,54 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as d= efined in version 1.0 of the Bit-Manipulation ISA extensions. =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZVBB`: The Zvbb extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVBC`: The Zvbc extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKB`: The Zvkb extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKG`: The Zvkg extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKN`: The Zvkn extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKNC`: The Zvknc extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKNED`: The Zvkned extension is supported= as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKNG`: The Zvkng extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKNHA`: The Zvknha extension is supported= as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKNHB`: The Zvknhb extension is supported= as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKS`: The Zvks extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKSC`: The Zvksc extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKSED`: The Zvksed extension is supported= as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKSH`: The Zvksh extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKSG`: The Zvksg extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvkt extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 006bfb48343d..d868eb431cd6 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -29,6 +29,22 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZBA (1 << 3) #define RISCV_HWPROBE_EXT_ZBB (1 << 4) #define RISCV_HWPROBE_EXT_ZBS (1 << 5) +#define RISCV_HWPROBE_EXT_ZVBB (1 << 6) +#define RISCV_HWPROBE_EXT_ZVBC (1 << 7) +#define RISCV_HWPROBE_EXT_ZVKB (1 << 8) +#define RISCV_HWPROBE_EXT_ZVKG (1 << 9) +#define RISCV_HWPROBE_EXT_ZVKN (1 << 10) +#define RISCV_HWPROBE_EXT_ZVKNC (1 << 11) +#define RISCV_HWPROBE_EXT_ZVKNED (1 << 12) +#define RISCV_HWPROBE_EXT_ZVKNG (1 << 13) +#define RISCV_HWPROBE_EXT_ZVKNHA (1 << 14) +#define RISCV_HWPROBE_EXT_ZVKNHB (1 << 15) +#define RISCV_HWPROBE_EXT_ZVKS (1 << 16) +#define RISCV_HWPROBE_EXT_ZVKSC (1 << 17) +#define RISCV_HWPROBE_EXT_ZVKSED (1 << 18) +#define RISCV_HWPROBE_EXT_ZVKSH (1 << 19) +#define RISCV_HWPROBE_EXT_ZVKSG (1 << 20) +#define RISCV_HWPROBE_EXT_ZVKT (1 << 21) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 5ce593ce07a4..4f5e51c192d5 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -156,6 +156,25 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pai= r, CHECK_ISA_EXT(ZBA); CHECK_ISA_EXT(ZBB); CHECK_ISA_EXT(ZBS); + + if (has_vector()) { + CHECK_ISA_EXT(ZVBB); + CHECK_ISA_EXT(ZVBC); + CHECK_ISA_EXT(ZVKB); + CHECK_ISA_EXT(ZVKG); + CHECK_ISA_EXT(ZVKN); + CHECK_ISA_EXT(ZVKNC); + CHECK_ISA_EXT(ZVKNED); + CHECK_ISA_EXT(ZVKNG); + CHECK_ISA_EXT(ZVKNHA); + CHECK_ISA_EXT(ZVKNHB); + CHECK_ISA_EXT(ZVKS); + CHECK_ISA_EXT(ZVKSC); + CHECK_ISA_EXT(ZVKSED); + CHECK_ISA_EXT(ZVKSH); + CHECK_ISA_EXT(ZVKSG); + CHECK_ISA_EXT(ZVKT); + } #undef CHECK_ISA_EXT } =20 --=20 2.42.0 From nobody Fri Jan 2 13:27:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFD43CD6E5C for ; Wed, 11 Oct 2023 11:20:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234830AbjJKLUE (ORCPT ); Wed, 11 Oct 2023 07:20:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34948 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232023AbjJKLTV (ORCPT ); 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([2a01:e0a:999:a3a0:9134:b302:d8b:a200]) by smtp.gmail.com with ESMTPSA id a4-20020a05600c224400b003fe2b081661sm18945715wmm.30.2023.10.11.04.19.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 04:19:17 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley Subject: [PATCH v1 04/13] dt-bindings: riscv: add Zv* ratified crypto ISA extensions description Date: Wed, 11 Oct 2023 13:14:29 +0200 Message-ID: <20231011111438.909552-5-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231011111438.909552-1-cleger@rivosinc.com> References: <20231011111438.909552-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add Zv* vector crypto extensions that were added in "RISC-V Cryptography Extensions Volume II" specificationi[1]: - Zvbb: Vector Basic Bit-manipulation - Zvbc: Vector Carryless Multiplication - Zvkb: Vector Cryptography Bit-manipulation - Zvkg: Vector GCM/GMAC. - Zvkned: NIST Suite: Vector AES Block Cipher - Zvknh[ab]: NIST Suite: Vector SHA-2 Secure Hash - Zvksed: ShangMi Suite: SM4 Block Cipher - Zvksh: ShangMi Suite: SM3 Secure Hash - Zvkn: NIST Algorithm Suite - Zvknc: NIST Algorithm Suite with carryless multiply - Zvkng: NIST Algorithm Suite with GCM. - Zvks: ShangMi Algorithm Suite - Zvksc: ShangMi Algorithm Suite with carryless multiplication - Zvksg: ShangMi Algorithm Suite with GCM. - Zvkt: Vector Data-Independent Execution Latency. [1] https://drive.google.com/file/d/1gb9OLH-DhbCgWp7VwpPOVrrY6f3oSJLL/view Signed-off-by: Cl=C3=A9ment L=C3=A9ger Acked-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index cc1f546fdbdc..4002c65145c9 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -246,5 +246,101 @@ properties: in commit 2e5236 ("Ztso is now ratified.") of the riscv-isa-manual. =20 + - const: zvbb + description: + The standard Zvbb extension for vectored basic bit-manipulation + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvbc + description: + The standard Zvbc extension for vectored carryless multiplicat= ion + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvkb + description: + The standard Zvkb extension for vector cryptography bit-manipu= lation + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvkg + description: + The standard Zvkg extension for vector GCM/GMAC instructions, = as + ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.a= doc") + of riscv-crypto. + + - const: zvkn + description: + The standard Zvkn extension for NIST algorithm suite instructi= ons, as + ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.a= doc") + of riscv-crypto. + + - const: zvknc + description: + The standard Zvknc extension for NIST algorithm suite with car= ryless + multiply instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvkned + description: + The standard Zvkned extension for Vector AES block cipher + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvkng + description: + The standard Zvkng extension for NIST algorithm suite with GCM + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvknha + description: | + The standard Zvknha extension for NIST suite: vector SHA-2 sec= ure, + hash (SHA-256 only) instructions, as ratified in commit + 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-cryp= to. + + - const: zvknhb + description: | + The standard Zvknhb extension for NIST suite: vector SHA-2 sec= ure, + hash (SHA-256 and SHA-512) instructions, as ratified in commit + 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-cryp= to. + + - const: zvks + description: + The standard Zvks extension for ShangMi algorithm suite + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvksc + description: + The standard Zvksc extension for ShangMi algorithm suite with + carryless multiplication instructions, as ratified in commit 5= 6ed795 + ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvksed + description: | + The standard Zvksed extension for ShangMi suite: SM4 block cip= her + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvksh + description: | + The standard Zvksh extension for ShangMi suite: SM3 secure hash + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvksg + description: + The standard Zvksg extension for ShangMi algorithm suite with = GCM + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvkt + description: + The standard zvkt extension for vector data-independent execut= ion + latency, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + additionalProperties: true ... --=20 2.42.0 From nobody Fri Jan 2 13:27:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E5A6CD6E5A for ; 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([2a01:e0a:999:a3a0:9134:b302:d8b:a200]) by smtp.gmail.com with ESMTPSA id a4-20020a05600c224400b003fe2b081661sm18945715wmm.30.2023.10.11.04.19.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 04:19:18 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley Subject: [PATCH v1 05/13] riscv: add ISA extension probing for Zfh/Zfhmin Date: Wed, 11 Oct 2023 13:14:30 +0200 Message-ID: <20231011111438.909552-6-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231011111438.909552-1-cleger@rivosinc.com> References: <20231011111438.909552-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add probing for Zvfh/Zfhmin ISA extensions[1]. [1] https://drive.google.com/file/d/1z3tQQLm5ALsAD77PM0l0CHnapxWCeVzP/view Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/kernel/cpufeature.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 4e46981ac6c8..35f00401afc8 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -74,6 +74,8 @@ #define RISCV_ISA_EXT_ZVKSH 56 #define RISCV_ISA_EXT_ZVKSG 57 #define RISCV_ISA_EXT_ZVKT 58 +#define RISCV_ISA_EXT_ZFH 59 +#define RISCV_ISA_EXT_ZFHMIN 60 =20 #define RISCV_ISA_EXT_MAX 64 =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 859d647f3ced..9ee7814641a4 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -171,6 +171,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI), __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), + __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), + __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN), __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), --=20 2.42.0 From nobody Fri Jan 2 13:27:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 292A0CD6E5C for ; Wed, 11 Oct 2023 11:20:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346577AbjJKLUN (ORCPT ); Wed, 11 Oct 2023 07:20:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234780AbjJKLTX (ORCPT ); Wed, 11 Oct 2023 07:19:23 -0400 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77CF2C4 for ; Wed, 11 Oct 2023 04:19:21 -0700 (PDT) Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-406aaccb41dso18558235e9.0 for ; Wed, 11 Oct 2023 04:19:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697023160; x=1697627960; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zBNgr4CfRjqqsWxQ2+6f8weSNRNIv9nwhwGw5L11t7E=; b=rOHMONfHM93YWtd5GUio9nmRIB4OWwOPZmyZc1185UHpTKBRoLHNPUxgO0o3IvBzuN J8DmTMtN+ZdJVGIQIX3lpcFzv2v/Rseo2tdRWXYzpkpntFmdeI1C9KhdK0JyNMHO96Md GwIm+PThwEKLlfZD7enltjd8MiWeYg42w7R4fqyTWZmXuB/GHIV6dK5QtQ86EtaBOYXf +iwh5YCYl1zQOiAeyFv7CFSdO48OV6vZaOLdUR1gMganXqj6AuZ13+4/TNAi5arTKqOh UnUpLV1xJy7sRUyV6ReVBdChEpmUGM7Z7TpwqN2i44PVQGlOZn2Lb0tT6LA0EYE1Syyh mK1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697023160; x=1697627960; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zBNgr4CfRjqqsWxQ2+6f8weSNRNIv9nwhwGw5L11t7E=; b=jwGThi5EY3YcFlOZ/y4CjqQMOmpAq8Z3auje7xvr0j9+u6E4sZ0rvvptV8SZTCfvVJ BLIgSCXyCAi6QGnYwPJ5q8DZJ1zb7Oh2ASCjeu0dGQoZwZ2VhmmYmNk4jSaBRovUqgf+ LfRlVlEtaPilB8U38+n9TTzscEsd8hhIzN5ek8jqPFYLl0rdDOMg1Gms77C/PJwcmU8G 3ewtesrFoxLZP6wLQuVJnv9jh04KsWebgC3PCGbtRIP+rU4S3h3/rLnGIjAZ7zP6VOJL q9tYe+kLgyXtI/Ht/kX+byEzfVknIWM7SQLBmJhNMJ4F8uZAhkRiPzgZ//0txGsN2LIt Q15w== X-Gm-Message-State: AOJu0YyDW6LBvpnPPHLXRip5DOl0E+T+mPs4tQY3NCJHszQGOJwcEwGj BG+ZUaaOlrDGFyNNPDWG52HvGw== X-Google-Smtp-Source: AGHT+IGz2OBUFL5jTgh2YCxEN7qoM5h2KX6lIy42xfQJumWv/niH0yRdWTx+Aa/sRSbVnW7ryNwO9Q== X-Received: by 2002:a05:600c:214f:b0:406:513d:738f with SMTP id v15-20020a05600c214f00b00406513d738fmr18787533wml.2.1697023159566; Wed, 11 Oct 2023 04:19:19 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:9134:b302:d8b:a200]) by smtp.gmail.com with ESMTPSA id a4-20020a05600c224400b003fe2b081661sm18945715wmm.30.2023.10.11.04.19.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 04:19:19 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley Subject: [PATCH v1 06/13] riscv: hwprobe: export Zfh/Zfhmin ISA extensions Date: Wed, 11 Oct 2023 13:14:31 +0200 Message-ID: <20231011111438.909552-7-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231011111438.909552-1-cleger@rivosinc.com> References: <20231011111438.909552-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Export Zfh/Zfhmin ISA extensions[1] through hwprobe only if FPU support is available. [1] https://drive.google.com/file/d/1z3tQQLm5ALsAD77PM0l0CHnapxWCeVzP/view Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- Documentation/riscv/hwprobe.rst | 6 ++++++ arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ arch/riscv/kernel/sys_riscv.c | 5 +++++ 3 files changed, 13 insertions(+) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.= rst index edfed33669ea..06f49a095f19 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -125,6 +125,12 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvkt extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZFH`: The Zfh extension version 1.0 is sup= ported + as defined in the RISC-V ISA manual. + + * :c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 = is + supported as defined in the RISC-V ISA manual. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index d868eb431cd6..c9016abf099e 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -45,6 +45,8 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZVKSH (1 << 19) #define RISCV_HWPROBE_EXT_ZVKSG (1 << 20) #define RISCV_HWPROBE_EXT_ZVKT (1 << 21) +#define RISCV_HWPROBE_EXT_ZFH (1 << 22) +#define RISCV_HWPROBE_EXT_ZFHMIN (1 << 23) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 4f5e51c192d5..da916981934b 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -175,6 +175,11 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pai= r, CHECK_ISA_EXT(ZVKSG); CHECK_ISA_EXT(ZVKT); } + + if (has_fpu()) { + CHECK_ISA_EXT(ZFH); + CHECK_ISA_EXT(ZFHMIN); + } #undef CHECK_ISA_EXT } =20 --=20 2.42.0 From nobody Fri Jan 2 13:27:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32748CD6E5C for ; Wed, 11 Oct 2023 11:20:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346520AbjJKLUU (ORCPT ); Wed, 11 Oct 2023 07:20:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34968 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234796AbjJKLTX (ORCPT ); Wed, 11 Oct 2023 07:19:23 -0400 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C17CB0 for ; Wed, 11 Oct 2023 04:19:22 -0700 (PDT) Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-406aaccb41dso18558375e9.0 for ; Wed, 11 Oct 2023 04:19:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697023161; x=1697627961; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=k1iP2iExuR7IS677Qe2UFfmGvnhfXBRfGhWxe/84qUE=; b=FtzyWwHLdVl19Qm0uB4F6Ikpk+6kODJHbGZd1t91pnFPAXJ/5QFcXwDH9zGjWKEKmN Da+xtBBDjwDWzvCv4LRyxyXpyUNVR9FYVJYbQmaBK83GbzaGNrGIOfAxo6Zk3CM4ZdfQ 5mmK6Z9CSVnknCH7xMGc547s9J/b185OAYt5gjpVpiYPZbUEtgtLVr+JMH+6BY2Hd9LZ RI53SYul7NPHUQb8A1xHAUK+b//YbBWYlThPZFWKCpLg7xZe9gQeozHDun302zOOcAWv KOGAd9z15K4VA8vmd8Plpjn8GT0UZzuA84BWKRb05GHkxvEzNGNZ269YkYvGH4ZUEK83 4iMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697023161; x=1697627961; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=k1iP2iExuR7IS677Qe2UFfmGvnhfXBRfGhWxe/84qUE=; b=QUnH+v1jBdwHKxJgVMn/6e4Tg6ZN3kc/VrPloiTr/eGU3moVtlNtcnJHADyHK9Ymtu yn4Tzw32T0DGlZ0RzZZtyWkpDryB1FLi2C2vOnTM0QNAu1nfr5QkyXoq0yvufbtpHSXW b1eO2YlUR5SmY5l15gk9Tcym6Wrjuy9gpOjoDAwTdnsiE62VA9IsJtesImcYcCM5dmHz Rsn9JcMXuyG3Di0pzby0o0SlF0vua9+CWSiVzh3i7VE+6HkjYy4589qfo47UIUSWi/F9 hIn60jUvk6FfVKXrRce+VQ/M+QXF7tSjqIk/wu9syo4bLI3w9EpQj+5bTGy0AGl6KxTm RA8Q== X-Gm-Message-State: AOJu0YwgXAOZ/K3zDkfE7R4Z7rM1/dTIKdjpZnucOi0ITkIFmSsUUx42 hy+RuBuVC+REuaL6WpFl7Lu0NA== X-Google-Smtp-Source: AGHT+IHN1jrPE5e/OFNBPSwpg81Ym2JZZudWxgKZK78wyWJftAy9XEh6ziseuRa2e9MUXZKDACfVXQ== X-Received: by 2002:a05:600c:511d:b0:401:b53e:6c3e with SMTP id o29-20020a05600c511d00b00401b53e6c3emr18807477wms.1.1697023160607; Wed, 11 Oct 2023 04:19:20 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:9134:b302:d8b:a200]) by smtp.gmail.com with ESMTPSA id a4-20020a05600c224400b003fe2b081661sm18945715wmm.30.2023.10.11.04.19.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 04:19:20 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley Subject: [PATCH v1 07/13] dt-bindings: riscv: add Zfh/Zfhmin ISA extensions description Date: Wed, 11 Oct 2023 13:14:32 +0200 Message-ID: <20231011111438.909552-8-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231011111438.909552-1-cleger@rivosinc.com> References: <20231011111438.909552-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add description of Zfh and Zfhmin ISA extensions[1] which can now be reported through hwprobe for userspace usage. [1] https://drive.google.com/file/d/1z3tQQLm5ALsAD77PM0l0CHnapxWCeVzP/view Signed-off-by: Cl=C3=A9ment L=C3=A9ger Acked-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 4002c65145c9..4c923800d751 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -190,6 +190,19 @@ properties: instructions as ratified at commit 6d33919 ("Merge pull reques= t #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. =20 + - const: zfh + description: + The standard Zfh extension for 16-bit half-precision binary + floating-point instructions, as ratified in commit 64074bc ("U= pdate + version numbers for Zfh/Zfinx") of riscv-isa-manual. + + - const: zfhmin + description: + The standard Zfhmin extension which provides minimal support f= or + 16-bit half-precision binary floating-point instructions, as r= atified + in commit 64074bc ("Update version numbers for Zfh/Zfinx") of + riscv-isa-manual. + - const: zicbom description: The standard Zicbom extension for base cache management operat= ions as --=20 2.42.0 From nobody Fri Jan 2 13:27:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCE5CCD6E5C for ; Wed, 11 Oct 2023 11:20:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346698AbjJKLU0 (ORCPT ); Wed, 11 Oct 2023 07:20:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33900 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345956AbjJKLT0 (ORCPT ); Wed, 11 Oct 2023 07:19:26 -0400 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4B53C6 for ; Wed, 11 Oct 2023 04:19:23 -0700 (PDT) Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-40651b22977so11504905e9.1 for ; Wed, 11 Oct 2023 04:19:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697023162; x=1697627962; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uPwBFtd40HLyGqXLen0KbaY9uN71oHhwHjqBqDa/Amo=; b=iVKe1O2hh6mtDRMq/avX8IsREhNQZ5Cd46lRcv874rzX8ZgNazQuovcQAkvFKrWeJB SJwjm7Qf+Q/WQpJN1R/vdugq3ScJCmVXe0pIDU7hyeYI7y6vQ+3QW0u6c5+8MY1EzpxB Dkeo/7YzS5VAgGvNKB8vTxB+D7j7mk4a6Fzhakl8bL8cPH/5k+7d2ACJYbJRM1ETm4zl wRzimPPCk7Mifj31I81F6wM9GQk4HAJfn8IZ6UItR0yjNOuCAwWeytbrPkFHgNspdMSZ ILmZedft4+YImQDIvmuyCUptiZFrcsLu9lG/mSph8lsAK5LUhPdf4tYCL4IEYQG07FME GmXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697023162; x=1697627962; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uPwBFtd40HLyGqXLen0KbaY9uN71oHhwHjqBqDa/Amo=; b=nICgC+feR7jE/UpcrqZ2DMmWa5ubZv9UNVlSNwv42tjFvpgYRAjdEopOQ7myda+lu/ 3Zwjh1By587LBqV6NQMJFXBLIsmJm+jriYjnWIMCpMrylM4MSwv0Z/TCi+XhaJTqJLsq FsYs+xGKw0LSHi6WW3E/9K7rI5BOgX1psVGkc0hCmWd5HfNtJbec1EpGvBMntzZqvdyd Te9BAV63wIgnW4BeG82/CW81QqhQg7nXZCUqUeANEvFNPKjMAIWiTxiqdMuOynd1H+c5 FZN4TAt+r6Cq8fyxeqY+aYak4/bws4m3m+3ytaUHVdh5AVXrIKksDjGTXWe6NROx10KW q44g== X-Gm-Message-State: AOJu0Yx6iXLcRYArREzUlftGtpdXV6zBjXdXzOVQcsgzwGH9tH8rnCGt d/Xzijjo13r+/X6t3hTntVca4Q== X-Google-Smtp-Source: AGHT+IExnIHp9l/UnaTbrZ3Z3/Wvq+vo4xX0Z23oITLpc5cVbubkCxO0IQd8/NJP5tC/mEAiM4RIRw== X-Received: by 2002:a05:600c:1d18:b0:404:72f9:d59a with SMTP id l24-20020a05600c1d1800b0040472f9d59amr18737359wms.0.1697023161691; Wed, 11 Oct 2023 04:19:21 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:9134:b302:d8b:a200]) by smtp.gmail.com with ESMTPSA id a4-20020a05600c224400b003fe2b081661sm18945715wmm.30.2023.10.11.04.19.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 04:19:21 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley Subject: [PATCH v1 08/13] riscv: add ISA extension probing for Zihintntl Date: Wed, 11 Oct 2023 13:14:33 +0200 Message-ID: <20231011111438.909552-9-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231011111438.909552-1-cleger@rivosinc.com> References: <20231011111438.909552-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add probing for Zihintntl ISA extension[1] that was ratified in commit 0dc91f5 ("Zihintntl is ratified") in riscv-isa-manual[2]. [1] https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/view [2] https://github.com/riscv/riscv-isa-manual/commit/0dc91f505e6d Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 35f00401afc8..1f09b8b3da2a 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -76,6 +76,7 @@ #define RISCV_ISA_EXT_ZVKT 58 #define RISCV_ISA_EXT_ZFH 59 #define RISCV_ISA_EXT_ZFHMIN 60 +#define RISCV_ISA_EXT_ZIHINTNTL 61 =20 #define RISCV_ISA_EXT_MAX 64 =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 9ee7814641a4..136e90263ba2 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -169,6 +169,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI), + __RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL), __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), --=20 2.42.0 From nobody Fri Jan 2 13:27:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29842CD6E5C for ; Wed, 11 Oct 2023 11:20:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346398AbjJKLUh (ORCPT ); Wed, 11 Oct 2023 07:20:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33926 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234821AbjJKLT0 (ORCPT ); Wed, 11 Oct 2023 07:19:26 -0400 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC7BFC0 for ; Wed, 11 Oct 2023 04:19:24 -0700 (PDT) Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-40651b22977so11504955e9.1 for ; Wed, 11 Oct 2023 04:19:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697023163; x=1697627963; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4tXTHfOF9l2oA3bnmaAaKSnwfTQRRdZhw8v+5/SMqC8=; b=N04xmegZV+lKKeXl1ojADZgfRibjKxsCegf6l8KNRpoOGSi1p+Or42fV/6nK/fl4h2 HBnBgThG/fN1Bjk5KaRKmLr34uj0f0UilGBdkXNptV+oBzweekSPUXR5rbsxY5BV7Ct6 WbIdxc9AEVnlTdrDy8sbhRNZCowdQcfB+v++gy7OwlMrdjp/cTzqUiCCf1wSe4pCBxox Yz9tTvd0xDr4+CW1ApvHLDciaffION4EoLEoP02vRAIrcHY7Vd17hAWG40Dt6JwKVhOt 9YWIQyrR32R4gpnAxHXNlUU0scvqrUwR5hVnxx+eGZ9W+IuJzxb0AgeOQSLqglsuxVg7 PGKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697023163; x=1697627963; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4tXTHfOF9l2oA3bnmaAaKSnwfTQRRdZhw8v+5/SMqC8=; b=v9qtPCXDgvI99W6Nd44Ea5U01QjgqO3hGVGpRG9+X/Il4aN/mFQ0Qgz55yJQjA+I9M PfrSpN75wHNMwuLTRtW7qQQjCBwYXi9/O+4Lw459zDzHnUbktfZfLUCXKpdVeKRdf3On jTXhWXHRCO0dRVxNY7pNPAS0L3/kxEWMoJfu5nn8Bo+LztwK5XGbegNbrEHhebVyOuTF 3GMkqMZc6cqfFr/ObWYhRXIE1cYrE2g7q+3owLhr48/63MGMbmTCT3nkSAzusn2DbfHe wmoopbaiMsb5JMJ09oG4bUUIJvBPzxaaCTmRGq0zPFpcsjeI8Sj9UpQqsCBcKxFnOnRh E5VQ== X-Gm-Message-State: AOJu0Yy3qi75H61tEFQAQMx0iMGFm+tXUU0RmtIIqWgL819gz4UJPV5a agTgY1n8AEWTOEFJKXOMCEaTwg== X-Google-Smtp-Source: AGHT+IGArMLkH9j0nR6q6ZxQVwuBHeskjOjNvD5ZUnKc5yiKkdCwzXcWhurTv5ALmG1Vajfi3OEIlw== X-Received: by 2002:a05:600c:3c96:b0:403:334:fb0d with SMTP id bg22-20020a05600c3c9600b004030334fb0dmr18654577wmb.4.1697023162835; Wed, 11 Oct 2023 04:19:22 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:9134:b302:d8b:a200]) by smtp.gmail.com with ESMTPSA id a4-20020a05600c224400b003fe2b081661sm18945715wmm.30.2023.10.11.04.19.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 04:19:22 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley Subject: [PATCH v1 09/13] riscv: hwprobe: export Zhintntl ISA extension Date: Wed, 11 Oct 2023 13:14:34 +0200 Message-ID: <20231011111438.909552-10-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231011111438.909552-1-cleger@rivosinc.com> References: <20231011111438.909552-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Export Zihintntl extension[1] through hwprobe. [1] https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/view Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- Documentation/riscv/hwprobe.rst | 3 +++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_riscv.c | 1 + 3 files changed, 5 insertions(+) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.= rst index 06f49a095f19..a577b1d72dff 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -131,6 +131,9 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 = is supported as defined in the RISC-V ISA manual. =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension versio= n 1.0 + is supported as defined in the RISC-V ISA manual. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index c9016abf099e..3c4aa5d01f93 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -47,6 +47,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZVKT (1 << 21) #define RISCV_HWPROBE_EXT_ZFH (1 << 22) #define RISCV_HWPROBE_EXT_ZFHMIN (1 << 23) +#define RISCV_HWPROBE_EXT_ZIHINTNTL (1 << 24) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index da916981934b..ca17829f3e16 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -156,6 +156,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, CHECK_ISA_EXT(ZBA); CHECK_ISA_EXT(ZBB); CHECK_ISA_EXT(ZBS); + CHECK_ISA_EXT(ZIHINTNTL); =20 if (has_vector()) { CHECK_ISA_EXT(ZVBB); --=20 2.42.0 From nobody Fri Jan 2 13:27:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06624CD6E5A for ; Wed, 11 Oct 2023 11:20:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234854AbjJKLUl (ORCPT ); Wed, 11 Oct 2023 07:20:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33960 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346137AbjJKLT3 (ORCPT ); Wed, 11 Oct 2023 07:19:29 -0400 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D1CC29E for ; Wed, 11 Oct 2023 04:19:25 -0700 (PDT) Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-406553f6976so17190225e9.1 for ; Wed, 11 Oct 2023 04:19:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697023164; x=1697627964; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tgOpomIA0gFd2Dumo10XdK5WbanlcO0t/Ib98/qFyoU=; b=nCJtqCc94cfvZTkE+xghYUTxC4nV6QIGHXPU0p6Cu1fQbBmiZoJt4f5TJCpFYqKBVj yB0j6+683LJUgv5DfSppE4KuOwtnAjNU+jywjEa4gey+7sTwh1TqZRrvGvnANGnVvL7t 2zdghABIO3ApI2S1ilCCFL1iDxCm6wXBHgmiXDrLy6//hG2cgVQivetNRsmJyP7AXq8V Tok4Rzv1mMTE6hgsTg5wcygX0Z0Kn3W8KGH1EaMONvdE1HfMU9Ykryj8RfQiHZV7jlDD a2EGfE2GKNywn6SXhAAS/y7ZHssqJW8TzWyIVK3PnnvzC3fpwlr9DEDpMkvzoRrSZtWw ADTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697023164; x=1697627964; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tgOpomIA0gFd2Dumo10XdK5WbanlcO0t/Ib98/qFyoU=; b=CSmDOGik1Ww3z02k4s/5la6H7Z81wGR0Q281IdutMYCcWMsUFluA6+CXrUPjDSXv5c woyilhHPjtnLYLs40P/8j4pakKHsVFOEGYyZkSxLU+ggvn1BXLfIVCakMrJQphDzL4zN LwWAbkEOKLwfNPIfD6VS+UShrNEqW/w08j1YjI483iqXX33CDZ5sNRp86+IbFbd7PyKv PVchRcTQ/sT+LPJGFOWhwj5fhm0jrpgdQZhqxFhnel7VAFbL+NiPheJdfHqmspjiqT4C 3qFVG97tDdNPdn7o5HJ2BBcfXv6OBBqIdwnhvOwlx1fYHHEcxZ1HqZg3rgWnt8zFIci4 uiXA== X-Gm-Message-State: AOJu0Yyu5BzAkR8ZBNeTz514tkGQ3JaEWIHa7ezisslEE9AJf0ZPSw9l 3wSDHfTmGd17WOhFnfZpGQglKg== X-Google-Smtp-Source: AGHT+IFVFIbx7DKNbft8CuPYlaXxcUAmVstIo+qHMKhRiCsnw92NpkwOTsKvZdeKecHBMfd8bUqpbw== X-Received: by 2002:a05:600c:1c1f:b0:405:38d1:621 with SMTP id j31-20020a05600c1c1f00b0040538d10621mr18328348wms.3.1697023163815; Wed, 11 Oct 2023 04:19:23 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:9134:b302:d8b:a200]) by smtp.gmail.com with ESMTPSA id a4-20020a05600c224400b003fe2b081661sm18945715wmm.30.2023.10.11.04.19.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 04:19:23 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley Subject: [PATCH v1 10/13] dt-bindings: riscv: add Zihintntl ISA extension description Date: Wed, 11 Oct 2023 13:14:35 +0200 Message-ID: <20231011111438.909552-11-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231011111438.909552-1-cleger@rivosinc.com> References: <20231011111438.909552-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add description for Zihintntl ISA extension[1] which can now be reported through hwprobe for userspace usage. [1] https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/view Signed-off-by: Cl=C3=A9ment L=C3=A9ger Acked-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 4c923800d751..70c2b0351357 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -247,6 +247,12 @@ properties: The standard Zihintpause extension for pause hints, as ratifie= d in commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-ma= nual. =20 + - const: zihintntl + description: + The standard Zihintntl extension for non-temporal locality hin= ts, as + ratified in commit 0dc91f5 ("Zihintntl is ratified") of the + riscv-isa-manual. + - const: zihpm description: The standard Zihpm extension for hardware performance counters= , as --=20 2.42.0 From nobody Fri Jan 2 13:27:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5AB85CD6E5C for ; Wed, 11 Oct 2023 11:20:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346700AbjJKLUc (ORCPT ); Wed, 11 Oct 2023 07:20:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33944 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346089AbjJKLT2 (ORCPT ); Wed, 11 Oct 2023 07:19:28 -0400 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0232CC4 for ; Wed, 11 Oct 2023 04:19:26 -0700 (PDT) Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-406532c49dcso17186335e9.0 for ; Wed, 11 Oct 2023 04:19:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697023165; x=1697627965; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ELrfmr7/+eL4h+O/hGMHN5n5h58B6vu8kUgBEeprKDM=; b=JwV/jeoRE8dXiEwdRSx01ibal7orBV/WcFAnPyz7D5Y/HBzKwGwfDbqrr07JeRe3cA gxWqDxydGrs7Fku6fkli/Rp19klM9dD5EfzZPlidAd/LV+SdSjJpgs/7dPh0eWikXKzD JIN3gZNnjtrWeEnSVFMpzJ0QCgcGPIoCZp8aH7Vxb+f9LQ/ASkH0JeCdCwFw1M0ydT0B v7im0MlJhGLIbSqXO/GQ9GQUGtWwKlkzmJd9voK8qiqnbuV/eIeyyBvh1y66J/61o+xt u0NUsKnJreqUM1yXVqP9yoHXZ2aADJSj+f7zf5+pC6XgzN0YTn5Muafwiqa4FAYTJzAZ G34Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697023165; x=1697627965; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ELrfmr7/+eL4h+O/hGMHN5n5h58B6vu8kUgBEeprKDM=; b=KeqsG9xof56Gxouos3JvgPY7MLsxooeIN5A7cBuEnzxhxiutejfUmm8b7od9VsGwPq CmCvDm1UegJlAxa0QZb9To8NBBIEXmELssnvRqXGvY5ubzeLQsIIIcAFqgRRu5F6cALX UcCJQWYGksB+m8B710qJDBD3hRUojDy6GyrdUW9Y+OtMPCj4WotfjQFZ38SbrtF783ix uH7G2RHPoRaOwGjk0+tz3ah4orkMtC4edAMyAwIaAwsqWWDtj6J7KbhD1QnfpokBrMTX xUFNdkmGl738M5ouWj9hBS6grmTtILdtwcrsN+Kbj5I5+My54dFtHS6qqVd/8Ny/uc3V nO5g== X-Gm-Message-State: AOJu0YyMdLCyD4Yq8fJGWq9hXuoK2I/xhobiVOid1QP/2V2bgHeHJoGj pcSHmUJ7VnU68qsTYIwTv8dZbA== X-Google-Smtp-Source: AGHT+IE2y/iGfOk9x0FcfGmLs9von/gSyi9IxV8X3T9o1LjNrBHKENRhq76JY7LxinEZmPIgMRylzA== X-Received: by 2002:a05:600c:5114:b0:405:4127:f471 with SMTP id o20-20020a05600c511400b004054127f471mr18363952wms.1.1697023165036; Wed, 11 Oct 2023 04:19:25 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:9134:b302:d8b:a200]) by smtp.gmail.com with ESMTPSA id a4-20020a05600c224400b003fe2b081661sm18945715wmm.30.2023.10.11.04.19.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 04:19:24 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley Subject: [PATCH v1 11/13] riscv: add ISA extension probing for Zvfh[min] Date: Wed, 11 Oct 2023 13:14:36 +0200 Message-ID: <20231011111438.909552-12-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231011111438.909552-1-cleger@rivosinc.com> References: <20231011111438.909552-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add probing for Zvfh[min] ISA extension[1] which were ratified in june 2023 around commit e2ccd0548d6c ("Remove draft warnings from Zvfh[min]") in riscv-v-spec[2]. [1] https://drive.google.com/file/d/1_Yt60HGAf1r1hx7JnsIptw0sqkBd9BQ8/view [2] https://github.com/riscv/riscv-v-spec/commits/e2ccd0548d6c Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/kernel/cpufeature.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 1f09b8b3da2a..ea141cfb8f9c 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -77,6 +77,8 @@ #define RISCV_ISA_EXT_ZFH 59 #define RISCV_ISA_EXT_ZFHMIN 60 #define RISCV_ISA_EXT_ZIHINTNTL 61 +#define RISCV_ISA_EXT_ZVFH 62 +#define RISCV_ISA_EXT_ZVFHMIN 63 =20 #define RISCV_ISA_EXT_MAX 64 =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 136e90263ba2..f17b9aca5fba 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -179,6 +179,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), __RISCV_ISA_EXT_DATA(zvbb, RISCV_ISA_EXT_ZVBB), __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC), + __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH), + __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN), __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB), __RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG), __RISCV_ISA_EXT_DATA(zvkn, RISCV_ISA_EXT_ZVKN), --=20 2.42.0 From nobody Fri Jan 2 13:27:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3613CD6E5C for ; Wed, 11 Oct 2023 11:20:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346014AbjJKLUq (ORCPT ); Wed, 11 Oct 2023 07:20:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33990 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346190AbjJKLTa (ORCPT ); Wed, 11 Oct 2023 07:19:30 -0400 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DCFA8E1 for ; Wed, 11 Oct 2023 04:19:27 -0700 (PDT) Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-4053e6e8ca7so19944915e9.1 for ; Wed, 11 Oct 2023 04:19:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697023166; x=1697627966; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nDxU+S/2S9Zyokkzv2m0SOvysTHMfn1aGA6JYhknF4k=; b=P4jJhMMZ6ZNxm2Izz+fUqWMv9qSRjyYHIfHGSozkxI2BbWtIG9LpgxqLaSrMz3jQty drsToi4H3/tpUyukuHxT18zwVn/Ff38bte1ux2BW+0pQxZOV+s+T/aXzUhiOiUObQ/7M lAyTjYy6nJSKL+es7SJhVRaPfZdZc5sEgkqLcvdUAdRdEepLzN9c/CsvkaqGYI2JZ/cu iuRjZyBXDLu5egzSugkUwkJgxYOYeS4KIv6FHkh2Jb3Oi7BMx0qVspcqy4WRpGc1f7SE 6CcWqjvZOwNtiEBirV8qxwclfAPBlATTapQBi8JiU7o3vnAuRGDuQr8BUWiJguIdFybY e95g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697023166; x=1697627966; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nDxU+S/2S9Zyokkzv2m0SOvysTHMfn1aGA6JYhknF4k=; b=wXi6oxqm/ZguHJhAU77B7j61DECC8uqWsGopdLFgcb08oLHWPUAX7bdBtR6MXuw5E2 w2Oa5oLdiS/H67QMbu9KMHlgiYfYwf3Ka1h0wSR3lWDeXRcRSaIX7ghHkGB/SO+KCxZ+ i34ZyDtkZmw9FiwK3QQL3twupIlZBKpZ/9eQNurXKdC26tj068gyoXEnVbJrFnouerjV WL+CDwGMXRR61B4/cOOY+llD3nsMWA8TQ5PcANCamxZgYFsSpdrwSWs6dzP96DSbHszE e6uXIuicaFrvj7s7dcbCqUKmvmc0DFKZcIn+6fMKMstUx0Zf0mxskFxjg1Ae/vcWNoxw fQyQ== X-Gm-Message-State: AOJu0YyEqTQA9lLXSzDGIkWHIiYWUrHd3FpQtLEXEfQdz1r+2ycjUw1s VwHsIElw29D9ce75rCpdkLVZxw== X-Google-Smtp-Source: AGHT+IFL8F9ISrFJv94kKo0D+DqyUmKI3p+OtOo8OtLvqm7OkyywkV6XfNe2K2nOJgZP+i+4KXShHQ== X-Received: by 2002:a05:600c:3ca1:b0:405:3cc1:e115 with SMTP id bg33-20020a05600c3ca100b004053cc1e115mr18775209wmb.3.1697023166187; Wed, 11 Oct 2023 04:19:26 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:9134:b302:d8b:a200]) by smtp.gmail.com with ESMTPSA id a4-20020a05600c224400b003fe2b081661sm18945715wmm.30.2023.10.11.04.19.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 04:19:25 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley Subject: [PATCH v1 12/13] riscv: hwprobe: export Zvfh[min] ISA extensions Date: Wed, 11 Oct 2023 13:14:37 +0200 Message-ID: <20231011111438.909552-13-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231011111438.909552-1-cleger@rivosinc.com> References: <20231011111438.909552-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Export Zvfh[min] ISA extension[1] through hwprobe. [1] https://drive.google.com/file/d/1_Yt60HGAf1r1hx7JnsIptw0sqkBd9BQ8/view Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- Documentation/riscv/hwprobe.rst | 8 ++++++++ arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ arch/riscv/kernel/sys_riscv.c | 2 ++ 3 files changed, 12 insertions(+) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.= rst index a577b1d72dff..c2c3588891d1 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -134,6 +134,14 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension versio= n 1.0 is supported as defined in the RISC-V ISA manual. =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZVFH`: The Zvfh extension is supported as + defined in the RISC-V Vector manual starting from commit e2ccd0548d= 6c + ("Remove draft warnings from Zvfh[min]"). + + * :c:macro:`RISCV_HWPROBE_EXT_ZVFHMIN`: The Zvfhmin extension is support= ed as + defined in the RISC-V Vector manual starting from commit e2ccd0548d= 6c + ("Remove draft warnings from Zvfh[min]"). + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 3c4aa5d01f93..ee68eb90d4c7 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -48,6 +48,8 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZFH (1 << 22) #define RISCV_HWPROBE_EXT_ZFHMIN (1 << 23) #define RISCV_HWPROBE_EXT_ZIHINTNTL (1 << 24) +#define RISCV_HWPROBE_EXT_ZVFH (1 << 25) +#define RISCV_HWPROBE_EXT_ZVFHMIN (1 << 26) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index ca17829f3e16..63e123314524 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -175,6 +175,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, CHECK_ISA_EXT(ZVKSH); CHECK_ISA_EXT(ZVKSG); CHECK_ISA_EXT(ZVKT); + CHECK_ISA_EXT(ZVFH); + CHECK_ISA_EXT(ZVFHMIN); } =20 if (has_fpu()) { --=20 2.42.0 From nobody Fri Jan 2 13:27:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C5E2CD6E5C for ; Wed, 11 Oct 2023 11:20:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234893AbjJKLUx (ORCPT ); Wed, 11 Oct 2023 07:20:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33990 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346136AbjJKLTc (ORCPT ); Wed, 11 Oct 2023 07:19:32 -0400 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F016D3 for ; Wed, 11 Oct 2023 04:19:29 -0700 (PDT) Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-406aaccb41dso18558755e9.0 for ; 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([2a01:e0a:999:a3a0:9134:b302:d8b:a200]) by smtp.gmail.com with ESMTPSA id a4-20020a05600c224400b003fe2b081661sm18945715wmm.30.2023.10.11.04.19.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 04:19:26 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley Subject: [PATCH v1 13/13] dt-bindings: riscv: add Zvfh[min] ISA extension description Date: Wed, 11 Oct 2023 13:14:38 +0200 Message-ID: <20231011111438.909552-14-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231011111438.909552-1-cleger@rivosinc.com> References: <20231011111438.909552-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add description for Zvfh[min] ISA extension[1] which can now be reported through hwprobe for userspace usage. [1] https://drive.google.com/file/d/1_Yt60HGAf1r1hx7JnsIptw0sqkBd9BQ8/view Signed-off-by: Cl=C3=A9ment L=C3=A9ger Acked-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 70c2b0351357..ae7db420ab92 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -277,6 +277,18 @@ properties: instructions, as ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. =20 + - const: zvfh + description: + The standard Zvfh extension for vectored half-precision + floating-point instructions, as ratified in commit e2ccd05 + ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. + + - const: zvfhmin + description: + The standard Zvfhmin extension for vectored minimal half-preci= sion + floating-point instructions, as ratified in commit e2ccd05 + ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. + - const: zvkb description: The standard Zvkb extension for vector cryptography bit-manipu= lation --=20 2.42.0