From nobody Fri Sep 20 09:32:50 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2EBACD98F8 for ; Wed, 11 Oct 2023 07:50:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229883AbjJKHup (ORCPT ); Wed, 11 Oct 2023 03:50:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35542 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229602AbjJKHuo (ORCPT ); Wed, 11 Oct 2023 03:50:44 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB5AF92; Wed, 11 Oct 2023 00:50:39 -0700 (PDT) X-UUID: db7142e0680a11eea33bb35ae8d461a2-20231011 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=P5JM1/wrQBmccE0zOhCn8sdA72w5RjiESxn0FFMljNE=; b=szkl1O1E5GdvTxP89TQeQBN2r6JtwHXpboupFa7pvf7qkztJ17DDAtaOrPNfpb7eZh17z5AetdeeEbAR04xlh50xtM+43LEGP4bAGnWYqbykpqVZX631mS56TBbh7OgXv7shj97+9261aDCEkenztwdu3LDe1gDXhntXOwd4AKM=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:6dc7a16f-f6e1-4920-84c6-243c49189e1c,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5f78ec9,CLOUDID:73cce614-4929-4845-9571-38c601e9c3c9,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: db7142e0680a11eea33bb35ae8d461a2-20231011 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 260589970; Wed, 11 Oct 2023 15:50:33 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 11 Oct 2023 15:50:32 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 11 Oct 2023 15:50:32 +0800 From: Moudy Ho To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno CC: "Nancy . Lin" , , , , , Moudy Ho Subject: [PATCH v7 1/3] arm64: dts: mediatek: mt8183: correct MDP3 DMA-related nodes Date: Wed, 11 Oct 2023 15:50:29 +0800 Message-ID: <20231011075031.30660-2-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231011075031.30660-1-moudy.ho@mediatek.com> References: <20231011075031.30660-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In order to generalize the node names, the DMA-related nodes corresponding to MT8183 MDP3 need to be corrected. Fixes: 60a2fb8d202a ("arm64: dts: mt8183: add MediaTek MDP3 nodes") Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts= /mediatek/mt8183.dtsi index 5169779d01df..bab68c233792 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1781,7 +1781,7 @@ mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0 0x1000>; }; =20 - mdp3-rdma0@14001000 { + dma-controller0@14001000 { compatible =3D "mediatek,mt8183-mdp3-rdma"; reg =3D <0 0x14001000 0 0x1000>; mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x1000 0x1000>; @@ -1793,6 +1793,7 @@ iommus =3D <&iommu M4U_PORT_MDP_RDMA0>; mboxes =3D <&gce 20 CMDQ_THR_PRIO_LOWEST 0>, <&gce 21 CMDQ_THR_PRIO_LOWEST 0>; + #dma-cells =3D <1>; }; =20 mdp3-rsz0@14003000 { @@ -1813,7 +1814,7 @@ clocks =3D <&mmsys CLK_MM_MDP_RSZ1>; }; =20 - mdp3-wrot0@14005000 { + dma-controller@14005000 { compatible =3D "mediatek,mt8183-mdp3-wrot"; reg =3D <0 0x14005000 0 0x1000>; mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x5000 0x1000>; @@ -1822,6 +1823,7 @@ power-domains =3D <&spm MT8183_POWER_DOMAIN_DISP>; clocks =3D <&mmsys CLK_MM_MDP_WROT0>; iommus =3D <&iommu M4U_PORT_MDP_WROT0>; + #dma-cells =3D <1>; }; =20 mdp3-wdma@14006000 { --=20 2.18.0 From nobody Fri Sep 20 09:32:50 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF8D5CD98F8 for ; Wed, 11 Oct 2023 07:51:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230042AbjJKHvA (ORCPT ); Wed, 11 Oct 2023 03:51:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35582 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229821AbjJKHup (ORCPT ); Wed, 11 Oct 2023 03:50:45 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D6BDD9B; Wed, 11 Oct 2023 00:50:42 -0700 (PDT) X-UUID: db8eb780680a11ee8051498923ad61e6-20231011 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=uIIHqi30PoZOPWI6f23EZPfgJ7kfJrkJHQPKD5B9bfI=; b=KZZDsMIYzfp/wSbotQXkffUI7mqlT7LFjp1ecul6RK3EE0Jd/ODuGrnh88dOeSQmYWVrW0hI/H2WOPzdtMjRgrj6AFsuGt68SumTBaJ45haSBz5qWhTxRJRX9AHV9M9cv7wX/gJkykFx0nNUXK1bstHQrqsJz+8hZLMfMJQcgLc=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:010e6c4d-9a5a-44ea-b738-0315c419b443,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5f78ec9,CLOUDID:8fcce614-4929-4845-9571-38c601e9c3c9,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: db8eb780680a11ee8051498923ad61e6-20231011 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1987408879; Wed, 11 Oct 2023 15:50:33 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 11 Oct 2023 15:50:32 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 11 Oct 2023 15:50:32 +0800 From: Moudy Ho To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno CC: "Nancy . Lin" , , , , , Moudy Ho Subject: [PATCH v7 2/3] arm64: dts: mediatek: mt8195: revise VDOSYS RDMA node name Date: Wed, 11 Oct 2023 15:50:30 +0800 Message-ID: <20231011075031.30660-3-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231011075031.30660-1-moudy.ho@mediatek.com> References: <20231011075031.30660-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" DMA-related nodes have their own standardized naming. Therefore, the MT8195 VDOSYS RDMA has been unified and corrected. Additionally, these modifications will facilitate the further integration of bindings. Fixes: 92d2c23dc269 ("arm64: dts: mt8195: add display node for vdosys1") Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index a9e52b50c8c4..0bfaa6db59de 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -2868,7 +2868,7 @@ power-domains =3D <&spm MT8195_POWER_DOMAIN_VDOSYS1>; }; =20 - vdo1_rdma0: rdma@1c104000 { + vdo1_rdma0: dma-controller@1c104000 { compatible =3D "mediatek,mt8195-vdo1-rdma"; reg =3D <0 0x1c104000 0 0x1000>; interrupts =3D ; @@ -2876,9 +2876,10 @@ power-domains =3D <&spm MT8195_POWER_DOMAIN_VDOSYS1>; iommus =3D <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>; mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>; + #dma-cells =3D <1>; }; =20 - vdo1_rdma1: rdma@1c105000 { + vdo1_rdma1: dma-controller@1c105000 { compatible =3D "mediatek,mt8195-vdo1-rdma"; reg =3D <0 0x1c105000 0 0x1000>; interrupts =3D ; @@ -2886,9 +2887,10 @@ power-domains =3D <&spm MT8195_POWER_DOMAIN_VDOSYS1>; iommus =3D <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>; mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>; + #dma-cells =3D <1>; }; =20 - vdo1_rdma2: rdma@1c106000 { + vdo1_rdma2: dma-controller@1c106000 { compatible =3D "mediatek,mt8195-vdo1-rdma"; reg =3D <0 0x1c106000 0 0x1000>; interrupts =3D ; @@ -2896,9 +2898,10 @@ power-domains =3D <&spm MT8195_POWER_DOMAIN_VDOSYS1>; iommus =3D <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>; mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>; + #dma-cells =3D <1>; }; =20 - vdo1_rdma3: rdma@1c107000 { + vdo1_rdma3: dma-controller@1c107000 { compatible =3D "mediatek,mt8195-vdo1-rdma"; reg =3D <0 0x1c107000 0 0x1000>; interrupts =3D ; @@ -2906,9 +2909,10 @@ power-domains =3D <&spm MT8195_POWER_DOMAIN_VDOSYS1>; iommus =3D <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>; mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>; + #dma-cells =3D <1>; }; =20 - vdo1_rdma4: rdma@1c108000 { + vdo1_rdma4: dma-controller@1c108000 { compatible =3D "mediatek,mt8195-vdo1-rdma"; reg =3D <0 0x1c108000 0 0x1000>; interrupts =3D ; @@ -2916,9 +2920,10 @@ power-domains =3D <&spm MT8195_POWER_DOMAIN_VDOSYS1>; iommus =3D <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>; mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>; + #dma-cells =3D <1>; }; =20 - vdo1_rdma5: rdma@1c109000 { + vdo1_rdma5: dma-controller@1c109000 { compatible =3D "mediatek,mt8195-vdo1-rdma"; reg =3D <0 0x1c109000 0 0x1000>; interrupts =3D ; @@ -2926,9 +2931,10 @@ power-domains =3D <&spm MT8195_POWER_DOMAIN_VDOSYS1>; iommus =3D <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>; mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>; + #dma-cells =3D <1>; }; =20 - vdo1_rdma6: rdma@1c10a000 { + vdo1_rdma6: dma-controller@1c10a000 { compatible =3D "mediatek,mt8195-vdo1-rdma"; reg =3D <0 0x1c10a000 0 0x1000>; interrupts =3D ; @@ -2936,9 +2942,10 @@ power-domains =3D <&spm MT8195_POWER_DOMAIN_VDOSYS1>; iommus =3D <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>; mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>; + #dma-cells =3D <1>; }; =20 - vdo1_rdma7: rdma@1c10b000 { + vdo1_rdma7: dma-controller@1c10b000 { compatible =3D "mediatek,mt8195-vdo1-rdma"; reg =3D <0 0x1c10b000 0 0x1000>; interrupts =3D ; @@ -2946,6 +2953,7 @@ power-domains =3D <&spm MT8195_POWER_DOMAIN_VDOSYS1>; iommus =3D <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>; mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>; + #dma-cells =3D <1>; }; =20 merge1: vpp-merge@1c10c000 { --=20 2.18.0 From nobody Fri Sep 20 09:32:50 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34FB5CD98F8 for ; Wed, 11 Oct 2023 07:50:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230017AbjJKHuu (ORCPT ); Wed, 11 Oct 2023 03:50:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35554 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229806AbjJKHup (ORCPT ); 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Lin" , , , , , Moudy Ho Subject: [PATCH v7 3/3] arm64: dts: mediatek: mt8195: add MDP3 nodes Date: Wed, 11 Oct 2023 15:50:31 +0800 Message-ID: <20231011075031.30660-4-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231011075031.30660-1-moudy.ho@mediatek.com> References: <20231011075031.30660-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--8.986800-8.000000 X-TMASE-MatchedRID: k8Cd32tj8sGuhCBFl/b63kfhraIl1XgxkUtSee+57IFAtKM3hDDAfGb6 PphVtfZgTPeZkapFnH8kAzbREWz9my2w9y+uUSpWCz1WR8KHe4B3Bf9JIqsoeKkp8F/qKdS/o8W MkQWv6iXBcIE78YqRWo6HM5rqDwqtQE1HOv+iFzIMkXusMQAzBhzBiOOd3fxS6r0Fmkrc7v02LO YqWklQDw== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--8.986800-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: CE4E8A7E3D5E43F303FB0FD9DC8B348FB98A54A6E18B8691854EBB59661894B32000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device nodes for Media Data Path 3 (MDP3) modules. Signed-off-by: Moudy Ho --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 392 +++++++++++++++++++++++ 1 file changed, 392 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 0bfaa6db59de..f75ed1d36343 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1960,6 +1960,115 @@ #clock-cells =3D <1>; }; =20 + dma-controller@14001000 { + compatible =3D "mediatek,mt8195-mdp3-rdma"; + reg =3D <0 0x14001000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>; + mediatek,gce-events =3D , + ; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + iommus =3D <&iommu_vpp M4U_PORT_L4_MDP_RDMA>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_RDMA>; + mboxes =3D <&gce1 12 CMDQ_THR_PRIO_1>, + <&gce1 13 CMDQ_THR_PRIO_1>, + <&gce1 14 CMDQ_THR_PRIO_1>, + <&gce1 21 CMDQ_THR_PRIO_1>, + <&gce1 22 CMDQ_THR_PRIO_1>; + #dma-cells =3D <1>; + }; + + display@14002000 { + compatible =3D "mediatek,mt8195-mdp3-fg"; + reg =3D <0 0x14002000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_FG>; + }; + + display@14003000 { + compatible =3D "mediatek,mt8195-mdp3-stitch"; + reg =3D <0 0x14003000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_STITCH>; + }; + + display@14004000 { + compatible =3D "mediatek,mt8195-mdp3-hdr"; + reg =3D <0 0x14004000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_HDR>; + }; + + display@14005000 { + compatible =3D "mediatek,mt8195-mdp3-aal"; + reg =3D <0 0x14005000 0 0x1000>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_AAL>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + display@14006000 { + compatible =3D "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; + reg =3D <0 0x14006000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys0 CLK_VPP0_MDP_RSZ>; + }; + + display@14007000 { + compatible =3D "mediatek,mt8195-mdp3-tdshp"; + reg =3D <0 0x14007000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_TDSHP>; + }; + + display@14008000 { + compatible =3D "mediatek,mt8195-mdp3-color"; + reg =3D <0 0x14008000 0 0x1000>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_COLOR>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + display@14009000 { + compatible =3D "mediatek,mt8195-mdp3-ovl"; + reg =3D <0 0x14009000 0 0x1000>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_OVL>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + iommus =3D <&iommu_vpp M4U_PORT_L4_MDP_OVL>; + }; + + display@1400a000 { + compatible =3D "mediatek,mt8195-mdp3-pad"; + reg =3D <0 0x1400a000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_PADDING>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + display@1400b000 { + compatible =3D "mediatek,mt8195-mdp3-tcc"; + reg =3D <0 0x1400b000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_TCC>; + }; + + dma-controller@1400c000 { + compatible =3D "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; + reg =3D <0 0x1400c000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys0 CLK_VPP0_MDP_WROT>; + iommus =3D <&iommu_vpp M4U_PORT_L4_MDP_WROT>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + #dma-cells =3D <1>; + }; + mutex@1400f000 { compatible =3D "mediatek,mt8195-vpp-mutex"; reg =3D <0 0x1400f000 0 0x1000>; @@ -2107,6 +2216,289 @@ power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; }; =20 + display@14f06000 { + compatible =3D "mediatek,mt8195-mdp3-split"; + reg =3D <0 0x14f06000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0x6000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_VPP_SPLIT>, + <&vppsys1 CLK_VPP1_HDMI_META>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f07000 { + compatible =3D "mediatek,mt8195-mdp3-tcc"; + reg =3D <0 0x14f07000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0x7000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_TCC>; + }; + + dma-controller@14f08000 { + compatible =3D "mediatek,mt8195-mdp3-rdma"; + reg =3D <0 0x14f08000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0x8000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_RDMA>; + iommus =3D <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_RDMA>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + #dma-cells =3D <1>; + }; + + dma-controller@14f09000 { + compatible =3D "mediatek,mt8195-mdp3-rdma"; + reg =3D <0 0x14f09000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>; + iommus =3D <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_RDMA>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + #dma-cells =3D <1>; + }; + + dma-controller@14f0a000 { + compatible =3D "mediatek,mt8195-mdp3-rdma"; + reg =3D <0 0x14f0a000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>; + iommus =3D <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_RDMA>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + #dma-cells =3D <1>; + }; + + display@14f0b000 { + compatible =3D "mediatek,mt8195-mdp3-fg"; + reg =3D <0 0x14f0b000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0xb000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_FG>; + }; + + display@14f0c000 { + compatible =3D "mediatek,mt8195-mdp3-fg"; + reg =3D <0 0x14f0c000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>; + }; + + display@14f0d000 { + compatible =3D "mediatek,mt8195-mdp3-fg"; + reg =3D <0 0x14f0d000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>; + }; + + display@14f0e000 { + compatible =3D "mediatek,mt8195-mdp3-hdr"; + reg =3D <0 0x14f0e000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0xe000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_HDR>; + }; + + display@14f0f000 { + compatible =3D "mediatek,mt8195-mdp3-hdr"; + reg =3D <0 0x14f0f000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>; + }; + + display@14f10000 { + compatible =3D "mediatek,mt8195-mdp3-hdr"; + reg =3D <0 0x14f10000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>; + }; + + display@14f11000 { + compatible =3D "mediatek,mt8195-mdp3-aal"; + reg =3D <0 0x14f11000 0 0x1000>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x1000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_AAL>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f12000 { + compatible =3D "mediatek,mt8195-mdp3-aal"; + reg =3D <0 0x14f12000 0 0x1000>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f13000 { + compatible =3D "mediatek,mt8195-mdp3-aal"; + reg =3D <0 0x14f13000 0 0x1000>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f14000 { + compatible =3D "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; + reg =3D <0 0x14f14000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x4000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_RSZ>; + }; + + display@14f15000 { + compatible =3D "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; + reg =3D <0 0x14f15000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>; + }; + + display@14f16000 { + compatible =3D "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; + reg =3D <0 0x14f16000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>; + }; + + display@14f17000 { + compatible =3D "mediatek,mt8195-mdp3-tdshp"; + reg =3D <0 0x14f17000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x7000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_TDSHP>; + }; + + display@14f18000 { + compatible =3D "mediatek,mt8195-mdp3-tdshp"; + reg =3D <0 0x14f18000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>; + }; + + display@14f19000 { + compatible =3D "mediatek,mt8195-mdp3-tdshp"; + reg =3D <0 0x14f19000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>; + }; + + display@14f1a000 { + compatible =3D "mediatek,mt8195-mdp3-merge"; + reg =3D <0 0x14f1a000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f1b000 { + compatible =3D "mediatek,mt8195-mdp3-merge"; + reg =3D <0 0x14f1b000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f1c000 { + compatible =3D "mediatek,mt8195-mdp3-color"; + reg =3D <0 0x14f1c000 0 0x1000>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0xc000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_COLOR>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f1d000 { + compatible =3D "mediatek,mt8195-mdp3-color"; + reg =3D <0 0x14f1d000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>; + interrupts =3D ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f1e000 { + compatible =3D "mediatek,mt8195-mdp3-color"; + reg =3D <0 0x14f1e000 0 0x1000>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f1f000 { + compatible =3D "mediatek,mt8195-mdp3-ovl"; + reg =3D <0 0x14f1f000 0 0x1000>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0xf000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_OVL>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + iommus =3D <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_OVL>; + }; + + display@14f20000 { + compatible =3D "mediatek,mt8195-mdp3-pad"; + reg =3D <0 0x14f20000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f2XXXX 0 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_VPP_PAD>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f21000 { + compatible =3D "mediatek,mt8195-mdp3-pad"; + reg =3D <0 0x14f21000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f22000 { + compatible =3D "mediatek,mt8195-mdp3-pad"; + reg =3D <0 0x14f22000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + dma-controller@14f23000 { + compatible =3D "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; + reg =3D <0 0x14f23000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f2XXXX 0x3000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_WROT>; + iommus =3D <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_WROT>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + #dma-cells =3D <1>; + }; + + dma-controller@14f24000 { + compatible =3D "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; + reg =3D <0 0x14f24000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>; + iommus =3D <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_WROT>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + #dma-cells =3D <1>; + }; + + dma-controller@14f25000 { + compatible =3D "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; + reg =3D <0 0x14f25000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>; + iommus =3D <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_WROT>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + #dma-cells =3D <1>; + }; + imgsys: clock-controller@15000000 { compatible =3D "mediatek,mt8195-imgsys"; reg =3D <0 0x15000000 0 0x1000>; --=20 2.18.0