From nobody Fri Sep 20 09:46:36 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5576BCD98EB for ; Wed, 11 Oct 2023 03:43:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229623AbjJKDna (ORCPT ); Tue, 10 Oct 2023 23:43:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34736 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229534AbjJKDnV (ORCPT ); Tue, 10 Oct 2023 23:43:21 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4CBC99B; Tue, 10 Oct 2023 20:43:19 -0700 (PDT) X-UUID: 4d50273c67e811eea33bb35ae8d461a2-20231011 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=C/TZq45qMi1fAaW0J3bBvSw/zlaucQX1tj2/vJ5eZ/o=; b=nrR8y4x2yzKPA7O1wbedUD/rM/nBVcrFfzPiyKj52VSzrQVuKQHnCQ5EEXfIjNdNmvvLxrq2qzAO78MfEsmoaE5qaHBNYk/mLimcLSDz7bwZz73Rd12xZXrJxIejSdASwwFDpHeVK/5ra4uhUPBayf+Qyl+bOcrU6ERSa43ckXY=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:ed009396-7188-409f-be54-eeb38b9d054b,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5f78ec9,CLOUDID:f4cafac3-1e57-4345-9d31-31ad9818b39f,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 4d50273c67e811eea33bb35ae8d461a2-20231011 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 288930346; Wed, 11 Oct 2023 11:43:12 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 11 Oct 2023 11:43:08 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 11 Oct 2023 11:43:08 +0800 From: Mark Tseng To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Philipp Zabel , Roger Lu , Kevin Hilman CC: , , , , , Subject: [PATCH v1 1/3] soc: mediatek: svs: Add support for MT8195 SoC Date: Wed, 11 Oct 2023 11:43:05 +0800 Message-ID: <20231011034307.24641-2-chun-jen.tseng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231011034307.24641-1-chun-jen.tseng@mediatek.com> References: <20231011034307.24641-1-chun-jen.tseng@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--9.945800-8.000000 X-TMASE-MatchedRID: GwmKcylEtt8Z+je+8a5/a38c8oKMbgYY0pVrZbbfikgTF8tEGMn0ovlY oV6p/cSxdlrF5BK8CswKDee6oJ8ihU9dh3PRYVY14RtSDjG+z7ChQhstwJ9G4DJDf04iwTcYs4M sNWdvFuhxEVHIJfjMK7pxDH0YWH+Inh05MEIv7Ndxa2BHu4P5OPls1Rj4kmPIFLXUWU5hGiFynC +RoYX/O+LzNWBegCW2xl8lw85EaVQLbigRnpKlKSPzRlrdFGDwKpWjy9i97MkNsLUak+gzyThXU ECyNQn3/l6Q7UmgcfyYLFAxByvC/w== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--9.945800-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 3F5B34051C6126FA34E494D2EE20E98D7390F45A91A910DE3EC9DD557F3329A92000:8 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MT8195 svs gpu uses 2-line high bank and low bank to optimize the voltage of opp table for higher and lower frequency respectively. Signed-off-by: Mark Tseng Reviewed-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 136 +++++++++++++++++++++++++++++++++ 1 file changed, 136 insertions(+) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index f31e3bedff50..317c402e673a 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -1792,6 +1792,75 @@ static int svs_get_efuse_data(struct svs_platform *s= vsp, return 0; } =20 +static bool svs_mt8195_efuse_parsing(struct svs_platform *svsp) +{ + struct svs_bank *svsb; + u32 idx, i, ft_pgm, vmin, golden_temp; + int ret; + + for (i =3D 0; i < svsp->efuse_max; i++) + if (svsp->efuse[i]) + dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", + i, svsp->efuse[i]); + + if (!svsp->efuse[10]) { + dev_notice(svsp->dev, "svs_efuse[10] =3D 0x0?\n"); + return false; + } + + /* Svs efuse parsing */ + ft_pgm =3D svsp->efuse[0] & GENMASK(7, 0); + vmin =3D (svsp->efuse[19] >> 4) & GENMASK(1, 0); + + for (idx =3D 0; idx < svsp->bank_max; idx++) { + svsb =3D &svsp->banks[idx]; + + if (vmin =3D=3D 0x1) + svsb->vmin =3D 0x1e; + + if (ft_pgm =3D=3D 0) + svsb->volt_flags |=3D SVSB_INIT01_VOLT_IGNORE; + + if (svsb->type =3D=3D SVSB_LOW) { + svsb->mtdes =3D svsp->efuse[10] & GENMASK(7, 0); + svsb->bdes =3D (svsp->efuse[10] >> 16) & GENMASK(7, 0); + svsb->mdes =3D (svsp->efuse[10] >> 24) & GENMASK(7, 0); + svsb->dcbdet =3D (svsp->efuse[8]) & GENMASK(7, 0); + svsb->dcmdet =3D (svsp->efuse[8] >> 8) & GENMASK(7, 0); + } else if (svsb->type =3D=3D SVSB_HIGH) { + svsb->mtdes =3D svsp->efuse[9] & GENMASK(7, 0); + svsb->bdes =3D (svsp->efuse[9] >> 16) & GENMASK(7, 0); + svsb->mdes =3D (svsp->efuse[9] >> 24) & GENMASK(7, 0); + svsb->dcbdet =3D (svsp->efuse[8]) & GENMASK(7, 0); + svsb->dcmdet =3D (svsp->efuse[8] >> 8) & GENMASK(7, 0); + } + + svsb->vmax +=3D svsb->dvt_fixed; + } + + ret =3D svs_get_efuse_data(svsp, "t-calibration-data", + &svsp->tefuse, &svsp->tefuse_max); + if (ret) + return false; + + for (i =3D 0; i < svsp->tefuse_max; i++) + if (svsp->tefuse[i] !=3D 0) + break; + + if (i =3D=3D svsp->tefuse_max) + golden_temp =3D 50; /* All thermal efuse data are 0 */ + else + golden_temp =3D (svsp->tefuse[0] >> 24) & GENMASK(7, 0); + + for (idx =3D 0; idx < svsp->bank_max; idx++) { + svsb =3D &svsp->banks[idx]; + svsb->mts =3D 500; + svsb->bts =3D (((500 * golden_temp + 250460) / 1000) - 25) * 4; + } + + return true; +} + static bool svs_mt8192_efuse_parsing(struct svs_platform *svsp) { struct svs_bank *svsb; @@ -2222,6 +2291,61 @@ static int svs_mt8183_platform_probe(struct svs_plat= form *svsp) return 0; } =20 +static struct svs_bank svs_mt8195_banks[] =3D { + { + .sw_id =3D SVSB_GPU, + .type =3D SVSB_LOW, + .set_freq_pct =3D svs_set_bank_freq_pct_v3, + .get_volts =3D svs_get_bank_volts_v3, + .volt_flags =3D SVSB_REMOVE_DVTFIXED_VOLT, + .mode_support =3D SVSB_MODE_INIT02, + .opp_count =3D MAX_OPP_ENTRIES, + .freq_base =3D 640000000, + .turn_freq_base =3D 640000000, + .volt_step =3D 6250, + .volt_base =3D 400000, + .vmax =3D 0x38, + .vmin =3D 0x14, + .age_config =3D 0x555555, + .dc_config =3D 0x1, + .dvt_fixed =3D 0x1, + .vco =3D 0x18, + .chk_shift =3D 0x87, + .core_sel =3D 0x0fff0100, + .int_st =3D BIT(0), + .ctl0 =3D 0x00540003, + }, + { + .sw_id =3D SVSB_GPU, + .type =3D SVSB_HIGH, + .set_freq_pct =3D svs_set_bank_freq_pct_v3, + .get_volts =3D svs_get_bank_volts_v3, + .tzone_name =3D "gpu1", + .volt_flags =3D SVSB_REMOVE_DVTFIXED_VOLT | + SVSB_MON_VOLT_IGNORE, + .mode_support =3D SVSB_MODE_INIT02 | SVSB_MODE_MON, + .opp_count =3D MAX_OPP_ENTRIES, + .freq_base =3D 880000000, + .turn_freq_base =3D 640000000, + .volt_step =3D 6250, + .volt_base =3D 400000, + .vmax =3D 0x38, + .vmin =3D 0x14, + .age_config =3D 0x555555, + .dc_config =3D 0x1, + .dvt_fixed =3D 0x6, + .vco =3D 0x18, + .chk_shift =3D 0x87, + .core_sel =3D 0x0fff0101, + .int_st =3D BIT(1), + .ctl0 =3D 0x00540003, + .tzone_htemp =3D 85000, + .tzone_htemp_voffset =3D 0, + .tzone_ltemp =3D 25000, + .tzone_ltemp_voffset =3D 7, + }, +}; + static struct svs_bank svs_mt8192_banks[] =3D { { .sw_id =3D SVSB_GPU, @@ -2441,6 +2565,15 @@ static struct svs_bank svs_mt8183_banks[] =3D { }, }; =20 +static const struct svs_platform_data svs_mt8195_platform_data =3D { + .name =3D "mt8195-svs", + .banks =3D svs_mt8195_banks, + .efuse_parsing =3D svs_mt8195_efuse_parsing, + .probe =3D svs_mt8192_platform_probe, + .regs =3D svs_regs_v2, + .bank_max =3D ARRAY_SIZE(svs_mt8195_banks), +}; + static const struct svs_platform_data svs_mt8192_platform_data =3D { .name =3D "mt8192-svs", .banks =3D svs_mt8192_banks, @@ -2470,6 +2603,9 @@ static const struct svs_platform_data svs_mt8183_plat= form_data =3D { =20 static const struct of_device_id svs_of_match[] =3D { { + .compatible =3D "mediatek,mt8195-svs", + .data =3D &svs_mt8195_platform_data, + }, { .compatible =3D "mediatek,mt8192-svs", .data =3D &svs_mt8192_platform_data, }, { --=20 2.18.0 From nobody Fri Sep 20 09:46:36 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0108FCD98E6 for ; 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Wed, 11 Oct 2023 11:43:10 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 11 Oct 2023 11:43:08 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 11 Oct 2023 11:43:08 +0800 From: Mark Tseng To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Philipp Zabel , Roger Lu , Kevin Hilman CC: , , , , , Subject: [PATCH v1 2/3] soc: mediatek: svs: Add support for MT8186 SoC Date: Wed, 11 Oct 2023 11:43:06 +0800 Message-ID: <20231011034307.24641-3-chun-jen.tseng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231011034307.24641-1-chun-jen.tseng@mediatek.com> References: <20231011034307.24641-1-chun-jen.tseng@mediatek.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MT8186 svs has a number of banks which used as optimization of opp voltage table for corresponding dvfs drivers. MT8186 svs big core uses 2-line high bank and low bank to optimize the voltage of opp table for higher and lower frequency respectively. Signed-off-by: Mark Tseng Reviewed-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 282 +++++++++++++++++++++++++++++++++ 1 file changed, 282 insertions(+) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 317c402e673a..0f7cfbe5630b 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -1986,6 +1986,89 @@ static bool svs_mt8188_efuse_parsing(struct svs_plat= form *svsp) return true; } =20 +static bool svs_mt8186_efuse_parsing(struct svs_platform *svsp) +{ + struct svs_bank *svsb; + u32 idx, i, golden_temp; + int ret; + + for (i =3D 0; i < svsp->efuse_max; i++) + if (svsp->efuse[i]) + dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", + i, svsp->efuse[i]); + + if (!svsp->efuse[0]) { + dev_notice(svsp->dev, "svs_efuse[0] =3D 0x0?\n"); + return false; + } + + /* Svs efuse parsing */ + for (idx =3D 0; idx < svsp->bank_max; idx++) { + svsb =3D &svsp->banks[idx]; + + switch (svsb->sw_id) { + case SVSB_CPU_BIG: + if (svsb->type =3D=3D SVSB_HIGH) { + svsb->mdes =3D (svsp->efuse[2] >> 24) & GENMASK(7, 0); + svsb->bdes =3D (svsp->efuse[2] >> 16) & GENMASK(7, 0); + svsb->mtdes =3D svsp->efuse[2] & GENMASK(7, 0); + svsb->dcmdet =3D (svsp->efuse[13] >> 8) & GENMASK(7, 0); + svsb->dcbdet =3D svsp->efuse[13] & GENMASK(7, 0); + } else if (svsb->type =3D=3D SVSB_LOW) { + svsb->mdes =3D (svsp->efuse[3] >> 24) & GENMASK(7, 0); + svsb->bdes =3D (svsp->efuse[3] >> 16) & GENMASK(7, 0); + svsb->mtdes =3D svsp->efuse[3] & GENMASK(7, 0); + svsb->dcmdet =3D (svsp->efuse[14] >> 24) & GENMASK(7, 0); + svsb->dcbdet =3D (svsp->efuse[14] >> 16) & GENMASK(7, 0); + } + break; + case SVSB_CPU_LITTLE: + svsb->mdes =3D (svsp->efuse[4] >> 24) & GENMASK(7, 0); + svsb->bdes =3D (svsp->efuse[4] >> 16) & GENMASK(7, 0); + svsb->mtdes =3D svsp->efuse[4] & GENMASK(7, 0); + svsb->dcmdet =3D (svsp->efuse[14] >> 8) & GENMASK(7, 0); + svsb->dcbdet =3D svsp->efuse[14] & GENMASK(7, 0); + break; + case SVSB_CCI: + svsb->mdes =3D (svsp->efuse[5] >> 24) & GENMASK(7, 0); + svsb->bdes =3D (svsp->efuse[5] >> 16) & GENMASK(7, 0); + svsb->mtdes =3D svsp->efuse[5] & GENMASK(7, 0); + svsb->dcmdet =3D (svsp->efuse[15] >> 24) & GENMASK(7, 0); + svsb->dcbdet =3D (svsp->efuse[15] >> 16) & GENMASK(7, 0); + break; + case SVSB_GPU: + svsb->mdes =3D (svsp->efuse[6] >> 24) & GENMASK(7, 0); + svsb->bdes =3D (svsp->efuse[6] >> 16) & GENMASK(7, 0); + svsb->mtdes =3D svsp->efuse[6] & GENMASK(7, 0); + svsb->dcmdet =3D (svsp->efuse[15] >> 8) & GENMASK(7, 0); + svsb->dcbdet =3D svsp->efuse[15] & GENMASK(7, 0); + break; + default: + dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); + return false; + } + + svsb->vmax +=3D svsb->dvt_fixed; + } + + ret =3D svs_get_efuse_data(svsp, "t-calibration-data", + &svsp->tefuse, &svsp->tefuse_max); + if (ret) + return false; + + golden_temp =3D (svsp->tefuse[0] >> 24) & GENMASK(7, 0); + if (!golden_temp) + golden_temp =3D 50; + + for (idx =3D 0; idx < svsp->bank_max; idx++) { + svsb =3D &svsp->banks[idx]; + svsb->mts =3D 409; + svsb->bts =3D (((500 * golden_temp + 204650) / 1000) - 25) * 4; + } + + return true; +} + static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp) { struct svs_bank *svsb; @@ -2252,6 +2335,50 @@ static int svs_mt8192_platform_probe(struct svs_plat= form *svsp) return 0; } =20 +static int svs_mt8186_platform_probe(struct svs_platform *svsp) +{ + struct device *dev; + struct svs_bank *svsb; + u32 idx; + + svsp->rst =3D devm_reset_control_get_optional(svsp->dev, "svs_rst"); + if (IS_ERR(svsp->rst)) + return dev_err_probe(svsp->dev, PTR_ERR(svsp->rst), + "cannot get svs reset control\n"); + + dev =3D svs_add_device_link(svsp, "lvts"); + if (IS_ERR(dev)) + return dev_err_probe(svsp->dev, PTR_ERR(dev), + "failed to get lvts device\n"); + + for (idx =3D 0; idx < svsp->bank_max; idx++) { + svsb =3D &svsp->banks[idx]; + + switch (svsb->sw_id) { + case SVSB_CPU_LITTLE: + case SVSB_CPU_BIG: + svsb->opp_dev =3D get_cpu_device(svsb->cpu_id); + break; + case SVSB_CCI: + svsb->opp_dev =3D svs_add_device_link(svsp, "cci"); + break; + case SVSB_GPU: + svsb->opp_dev =3D svs_add_device_link(svsp, "gpu"); + break; + default: + dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); + return -EINVAL; + } + + if (IS_ERR(svsb->opp_dev)) + return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev), + "failed to get OPP device for bank %d\n", + idx); + } + + return 0; +} + static int svs_mt8183_platform_probe(struct svs_platform *svsp) { struct device *dev; @@ -2461,6 +2588,149 @@ static struct svs_bank svs_mt8188_banks[] =3D { }, }; =20 +static struct svs_bank svs_mt8186_banks[] =3D { + { + .sw_id =3D SVSB_CPU_BIG, + .type =3D SVSB_LOW, + .set_freq_pct =3D svs_set_bank_freq_pct_v3, + .get_volts =3D svs_get_bank_volts_v3, + .cpu_id =3D 6, + .volt_flags =3D SVSB_REMOVE_DVTFIXED_VOLT, + .mode_support =3D SVSB_MODE_INIT02, + .opp_count =3D MAX_OPP_ENTRIES, + .freq_base =3D 1670000000, + .turn_freq_base =3D 1670000000, + .volt_step =3D 6250, + .volt_base =3D 400000, + .volt_od =3D 4, + .vmax =3D 0x59, + .vmin =3D 0x20, + .age_config =3D 0x1, + .dc_config =3D 0x1, + .dvt_fixed =3D 0x3, + .vco =3D 0x10, + .chk_shift =3D 0x87, + .core_sel =3D 0x0fff0100, + .int_st =3D BIT(0), + .ctl0 =3D 0x00540003, + }, + { + .sw_id =3D SVSB_CPU_BIG, + .type =3D SVSB_HIGH, + .set_freq_pct =3D svs_set_bank_freq_pct_v3, + .get_volts =3D svs_get_bank_volts_v3, + .cpu_id =3D 6, + .tzone_name =3D "cpu_big0", + .volt_flags =3D SVSB_REMOVE_DVTFIXED_VOLT | + SVSB_MON_VOLT_IGNORE, + .mode_support =3D SVSB_MODE_INIT02 | SVSB_MODE_MON, + .opp_count =3D MAX_OPP_ENTRIES, + .freq_base =3D 2050000000, + .turn_freq_base =3D 1670000000, + .volt_step =3D 6250, + .volt_base =3D 400000, + .volt_od =3D 4, + .vmax =3D 0x73, + .vmin =3D 0x20, + .age_config =3D 0x1, + .dc_config =3D 0x1, + .dvt_fixed =3D 0x6, + .vco =3D 0x10, + .chk_shift =3D 0x87, + .core_sel =3D 0x0fff0101, + .int_st =3D BIT(1), + .ctl0 =3D 0x00540003, + .tzone_htemp =3D 85000, + .tzone_htemp_voffset =3D 8, + .tzone_ltemp =3D 25000, + .tzone_ltemp_voffset =3D 8, + }, + { + .sw_id =3D SVSB_CPU_LITTLE, + .set_freq_pct =3D svs_set_bank_freq_pct_v2, + .get_volts =3D svs_get_bank_volts_v2, + .cpu_id =3D 0, + .tzone_name =3D "cpu_zone0", + .volt_flags =3D SVSB_REMOVE_DVTFIXED_VOLT | + SVSB_MON_VOLT_IGNORE, + .mode_support =3D SVSB_MODE_INIT02 | SVSB_MODE_MON, + .opp_count =3D MAX_OPP_ENTRIES, + .freq_base =3D 2000000000, + .volt_step =3D 6250, + .volt_base =3D 400000, + .volt_od =3D 3, + .vmax =3D 0x65, + .vmin =3D 0x20, + .age_config =3D 0x1, + .dc_config =3D 0x1, + .dvt_fixed =3D 0x6, + .vco =3D 0x10, + .chk_shift =3D 0x87, + .core_sel =3D 0x0fff0102, + .int_st =3D BIT(2), + .ctl0 =3D 0x3210000f, + .tzone_htemp =3D 85000, + .tzone_htemp_voffset =3D 8, + .tzone_ltemp =3D 25000, + .tzone_ltemp_voffset =3D 8, + }, + { + .sw_id =3D SVSB_CCI, + .set_freq_pct =3D svs_set_bank_freq_pct_v2, + .get_volts =3D svs_get_bank_volts_v2, + .tzone_name =3D "cpu_zone0", + .volt_flags =3D SVSB_REMOVE_DVTFIXED_VOLT | + SVSB_MON_VOLT_IGNORE, + .mode_support =3D SVSB_MODE_INIT02 | SVSB_MODE_MON, + .opp_count =3D MAX_OPP_ENTRIES, + .freq_base =3D 1400000000, + .volt_step =3D 6250, + .volt_base =3D 400000, + .volt_od =3D 3, + .vmax =3D 0x65, + .vmin =3D 0x20, + .age_config =3D 0x1, + .dc_config =3D 0x1, + .dvt_fixed =3D 0x6, + .vco =3D 0x10, + .chk_shift =3D 0x87, + .core_sel =3D 0x0fff0103, + .int_st =3D BIT(3), + .ctl0 =3D 0x3210000f, + .tzone_htemp =3D 85000, + .tzone_htemp_voffset =3D 8, + .tzone_ltemp =3D 25000, + .tzone_ltemp_voffset =3D 8, + }, + { + .sw_id =3D SVSB_GPU, + .set_freq_pct =3D svs_set_bank_freq_pct_v2, + .get_volts =3D svs_get_bank_volts_v2, + .tzone_name =3D "mfg", + .volt_flags =3D SVSB_REMOVE_DVTFIXED_VOLT | + SVSB_MON_VOLT_IGNORE, + .mode_support =3D SVSB_MODE_INIT02 | SVSB_MODE_MON, + .opp_count =3D MAX_OPP_ENTRIES, + .freq_base =3D 850000000, + .volt_step =3D 6250, + .volt_base =3D 400000, + .vmax =3D 0x58, + .vmin =3D 0x20, + .age_config =3D 0x555555, + .dc_config =3D 0x1, + .dvt_fixed =3D 0x4, + .vco =3D 0x10, + .chk_shift =3D 0x87, + .core_sel =3D 0x0fff0104, + .int_st =3D BIT(4), + .ctl0 =3D 0x00100003, + .tzone_htemp =3D 85000, + .tzone_htemp_voffset =3D 8, + .tzone_ltemp =3D 25000, + .tzone_ltemp_voffset =3D 7, + }, +}; + static struct svs_bank svs_mt8183_banks[] =3D { { .sw_id =3D SVSB_CPU_LITTLE, @@ -2592,6 +2862,15 @@ static const struct svs_platform_data svs_mt8188_pla= tform_data =3D { .bank_max =3D ARRAY_SIZE(svs_mt8188_banks), }; =20 +static const struct svs_platform_data svs_mt8186_platform_data =3D { + .name =3D "mt8186-svs", + .banks =3D svs_mt8186_banks, + .efuse_parsing =3D svs_mt8186_efuse_parsing, + .probe =3D svs_mt8186_platform_probe, + .regs =3D svs_regs_v2, + .bank_max =3D ARRAY_SIZE(svs_mt8186_banks), +}; + static const struct svs_platform_data svs_mt8183_platform_data =3D { .name =3D "mt8183-svs", .banks =3D svs_mt8183_banks, @@ -2611,6 +2890,9 @@ static const struct of_device_id svs_of_match[] =3D { }, { .compatible =3D "mediatek,mt8188-svs", .data =3D &svs_mt8188_platform_data, + }, { + .compatible =3D "mediatek,mt8186-svs", + .data =3D &svs_mt8186_platform_data, }, { .compatible =3D "mediatek,mt8183-svs", .data =3D &svs_mt8183_platform_data, --=20 2.18.0 From nobody Fri Sep 20 09:46:36 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 858AACD98E6 for ; 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charset="utf-8" Add mt8186 and mt8195 svs compatible in dt-bindings. Signed-off-by: Mark Tseng --- Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml b/= Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml index 7eda63d5682f..742b91d1d28e 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml @@ -22,8 +22,10 @@ properties: compatible: enum: - mediatek,mt8183-svs + - mediatek,mt8186-svs - mediatek,mt8188-svs - mediatek,mt8192-svs + - mediatek,mt8195-svs =20 reg: maxItems: 1 --=20 2.18.0