From nobody Fri Jan 2 15:47:34 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B6D9CD98E9 for ; Wed, 11 Oct 2023 03:15:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345029AbjJKDPu (ORCPT ); Tue, 10 Oct 2023 23:15:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55222 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345011AbjJKDPe (ORCPT ); Tue, 10 Oct 2023 23:15:34 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 04DF2D9; Tue, 10 Oct 2023 20:15:32 -0700 (PDT) Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39B2ZT1K028191; Wed, 11 Oct 2023 03:15:14 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=PWOq3jmRIiq+uiTPsHXaiaeOPpH/u4Efbtd5jc4OIgE=; b=GiRwefaLqvE10sgANHibutVOEIk9aYE+nw6FabCkgfcw/zwqu1gnmuxJcvCTgq5/Glox yKHIj/UUJ2RAxBXXNKCNqRUl2MCGUFu4wnu44PNjTOWOLcizbkp+xLnism20+PQi3lsG QkTvf4H6m5s46umdkg7eFeFxViP0ud5U945gTXDTB4ibfbO3G05/aZd3Bi9XmJS36V1I BedGuNno4X9wZ3Sn8cbk5Mq4oxRt9o3HoYXTaSEcjqGzKJ/Rj5UJOnh3/wecgcvOQu7p ZU7zgCQxVLCMNDRDQ0OzkoJoDsiAtbLEzgmUexXl6kgIqC+qoSNCzp4IlPkJLyy88I4r pA== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3tmxjpjq5a-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 11 Oct 2023 03:15:14 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 39B3FCOi007865 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 11 Oct 2023 03:15:12 GMT Received: from tengfan2-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Tue, 10 Oct 2023 20:15:04 -0700 From: Tengfei Fan To: , , , , , , , CC: , , , , , , , , , , , , , , , , Tengfei Fan Subject: [PATCH v5 RESEND 4/7] arm64: dts: qcom: add uart console support for SM4450 Date: Wed, 11 Oct 2023 11:14:12 +0800 Message-ID: <20231011031415.3360-5-quic_tengfan@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231011031415.3360-1-quic_tengfan@quicinc.com> References: <20231011031415.3360-1-quic_tengfan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: -kHfsE31EuEzgo6_q2U832SXUvWFaXu5 X-Proofpoint-ORIG-GUID: -kHfsE31EuEzgo6_q2U832SXUvWFaXu5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-10_19,2023-10-10_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 phishscore=0 priorityscore=1501 suspectscore=0 clxscore=1015 impostorscore=0 spamscore=0 lowpriorityscore=0 mlxscore=0 mlxlogscore=873 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2309180000 definitions=main-2310110028 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add base description of UART and TLMM nodes which helps SM4450 boot to shell with console on boards with this SoC. Signed-off-by: Tengfei Fan --- arch/arm64/boot/dts/qcom/sm4450.dtsi | 49 ++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qco= m/sm4450.dtsi index 5a8a54b0f6c1..3e7ae3bebbe0 100644 --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi @@ -364,6 +364,29 @@ <0>; }; =20 + qupv3_id_0: geniqup@ac0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x00ac0000 0x0 0x2000>; + ranges; + clocks =3D <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names =3D "m-ahb", "s-ahb"; + #address-cells =3D <2>; + #size-cells =3D <2>; + status =3D "disabled"; + + uart7: serial@a88000 { + compatible =3D "qcom,geni-debug-uart"; + reg =3D <0x0 0x00a88000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names =3D "se"; + interrupts =3D ; + pinctrl-0 =3D <&qup_uart7_tx>, <&qup_uart7_rx>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + tcsr_mutex: hwlock@1f40000 { compatible =3D "qcom,tcsr-mutex"; reg =3D <0x0 0x01f40000 0x0 0x40000>; @@ -380,6 +403,32 @@ interrupt-controller; }; =20 + tlmm: pinctrl@f100000 { + compatible =3D "qcom,sm4450-tlmm"; + reg =3D <0x0 0x0f100000 0x0 0x300000>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 137>; + wakeup-parent =3D <&pdc>; + + qup_uart7_rx: qup-uart7-rx-state { + pins =3D "gpio23"; + function =3D "qup1_se2_l2"; + drive-strength =3D <2>; + bias-disable; + }; + + qup_uart7_tx: qup-uart7-tx-state { + pins =3D "gpio22"; + function =3D "qup1_se2_l2"; + drive-strength =3D <2>; + bias-disable; + }; + }; + intc: interrupt-controller@17200000 { compatible =3D "arm,gic-v3"; reg =3D <0x0 0x17200000 0x0 0x10000>, /* GICD */ --=20 2.17.1