From nobody Fri Jan 2 16:42:47 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 886CECD8CAD for ; Tue, 10 Oct 2023 17:05:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233819AbjJJRFY (ORCPT ); Tue, 10 Oct 2023 13:05:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57482 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230236AbjJJRFW (ORCPT ); Tue, 10 Oct 2023 13:05:22 -0400 Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA93B93 for ; Tue, 10 Oct 2023 10:05:19 -0700 (PDT) Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1c724577e1fso46632535ad.0 for ; Tue, 10 Oct 2023 10:05:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1696957519; x=1697562319; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=B8bTrDTugOefVQ1gZ31VUL3xKHXyC/9v3hCQTi2FF0M=; b=jU5kqW5+yNfWXyrCBivpJvC6WFn8kuATscsBROojMz/mRH5v2/fAXFwz8y12CccoWJ Jf9kUJVveLhhjTZIhIGmzhi2PIHmqcU0yey+PIzlutgigyxExtvao35qm2vVKBHlj0M5 80OItPZNkpj1AOWEtJNrhHi2/IOld306mc2QXADitvQQij7EcYmrVMsuTKiWy8/IwyRF +jF/FpsrO6boZuWHZ4Hp2HIcoT2fU1RGd8mLrl/mxlF6M7G52GTSCS7MxQtYzWhmSq2r g4rsQxODxOtVoFgX8GNihTrb/BCzJDZqzSMVUarbirZT5uVPB2+gZabqxBaiLqhYtD8J 3ZOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696957519; x=1697562319; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B8bTrDTugOefVQ1gZ31VUL3xKHXyC/9v3hCQTi2FF0M=; b=cf/7Fg8jJrcImn0o75EZa6hB4EV/3oBWRosgAocioG765qV6l8kZysGr0fsVyMmKiP nNOZd8t7OxTyiAHRT9lwldqbh31Telldm9n8pmuUFfzCjxgLtI0BrNgoHtUwA2GsZSSu ub5sVDYzJJYpmYos8xFh4YpY3LodDdxZppC9CzQRY/ojDdx4VQy/GfCGIRa8EKR0khaH rWDPrBN+YUJ54WHAq5KHYhfE6gi2ecOG8xqTBFjDLDLCEwCdJfSenJVTMj1b6hL9d74B IAtw4JHDaT+Kdrr4GlQNSakHmwgWTHw24v34hMJLMrMC0ypdtRTMQpouBuST8xeW2rj9 vMwA== X-Gm-Message-State: AOJu0YzBlu9x/Nt8jKpRjBLuPOVeqwnDj3508uZhqgDWy7LeiDmST2X8 zzY6ZdMZKRYoGLTDNOMaLdjdzQ== X-Google-Smtp-Source: AGHT+IFL7+0d+NQPD7h5kg3nJxB/J3VP1OkPOJXtOKdl/WfOH7Q9zbTJf6UkIcSLTxobmxIUYWGImA== X-Received: by 2002:a17:902:ea0a:b0:1bb:598a:14e5 with SMTP id s10-20020a170902ea0a00b001bb598a14e5mr24227444plg.43.1696957519183; Tue, 10 Oct 2023 10:05:19 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id w19-20020a1709027b9300b001b89536974bsm11979868pll.202.2023.10.10.10.05.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Oct 2023 10:05:18 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Greg Kroah-Hartman , Jiri Slaby Cc: Conor Dooley , Andrew Jones , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH 1/6] RISC-V: Add defines for SBI debug console extension Date: Tue, 10 Oct 2023 22:34:58 +0530 Message-Id: <20231010170503.657189-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231010170503.657189-1-apatel@ventanamicro.com> References: <20231010170503.657189-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We add SBI debug console extension related defines/enum to the asm/sbi.h header. Signed-off-by: Anup Patel --- arch/riscv/include/asm/sbi.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 5b4a1bf5f439..12dfda6bb924 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -30,6 +30,7 @@ enum sbi_ext_id { SBI_EXT_HSM =3D 0x48534D, SBI_EXT_SRST =3D 0x53525354, SBI_EXT_PMU =3D 0x504D55, + SBI_EXT_DBCN =3D 0x4442434E, =20 /* Experimentals extensions must lie within this range */ SBI_EXT_EXPERIMENTAL_START =3D 0x08000000, @@ -236,6 +237,12 @@ enum sbi_pmu_ctr_type { /* Flags defined for counter stop function */ #define SBI_PMU_STOP_FLAG_RESET (1 << 0) =20 +enum sbi_ext_dbcn_fid { + SBI_EXT_DBCN_CONSOLE_WRITE =3D 0, + SBI_EXT_DBCN_CONSOLE_READ =3D 1, + SBI_EXT_DBCN_CONSOLE_WRITE_BYTE =3D 2, +}; + #define SBI_SPEC_VERSION_DEFAULT 0x1 #define SBI_SPEC_VERSION_MAJOR_SHIFT 24 #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f --=20 2.34.1