From nobody Fri Jan 2 15:17:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 886CECD8CAD for ; Tue, 10 Oct 2023 17:05:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233819AbjJJRFY (ORCPT ); Tue, 10 Oct 2023 13:05:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57482 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230236AbjJJRFW (ORCPT ); Tue, 10 Oct 2023 13:05:22 -0400 Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA93B93 for ; Tue, 10 Oct 2023 10:05:19 -0700 (PDT) Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1c724577e1fso46632535ad.0 for ; Tue, 10 Oct 2023 10:05:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1696957519; x=1697562319; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=B8bTrDTugOefVQ1gZ31VUL3xKHXyC/9v3hCQTi2FF0M=; b=jU5kqW5+yNfWXyrCBivpJvC6WFn8kuATscsBROojMz/mRH5v2/fAXFwz8y12CccoWJ Jf9kUJVveLhhjTZIhIGmzhi2PIHmqcU0yey+PIzlutgigyxExtvao35qm2vVKBHlj0M5 80OItPZNkpj1AOWEtJNrhHi2/IOld306mc2QXADitvQQij7EcYmrVMsuTKiWy8/IwyRF +jF/FpsrO6boZuWHZ4Hp2HIcoT2fU1RGd8mLrl/mxlF6M7G52GTSCS7MxQtYzWhmSq2r g4rsQxODxOtVoFgX8GNihTrb/BCzJDZqzSMVUarbirZT5uVPB2+gZabqxBaiLqhYtD8J 3ZOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696957519; x=1697562319; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B8bTrDTugOefVQ1gZ31VUL3xKHXyC/9v3hCQTi2FF0M=; b=cf/7Fg8jJrcImn0o75EZa6hB4EV/3oBWRosgAocioG765qV6l8kZysGr0fsVyMmKiP nNOZd8t7OxTyiAHRT9lwldqbh31Telldm9n8pmuUFfzCjxgLtI0BrNgoHtUwA2GsZSSu ub5sVDYzJJYpmYos8xFh4YpY3LodDdxZppC9CzQRY/ojDdx4VQy/GfCGIRa8EKR0khaH rWDPrBN+YUJ54WHAq5KHYhfE6gi2ecOG8xqTBFjDLDLCEwCdJfSenJVTMj1b6hL9d74B IAtw4JHDaT+Kdrr4GlQNSakHmwgWTHw24v34hMJLMrMC0ypdtRTMQpouBuST8xeW2rj9 vMwA== X-Gm-Message-State: AOJu0YzBlu9x/Nt8jKpRjBLuPOVeqwnDj3508uZhqgDWy7LeiDmST2X8 zzY6ZdMZKRYoGLTDNOMaLdjdzQ== X-Google-Smtp-Source: AGHT+IFL7+0d+NQPD7h5kg3nJxB/J3VP1OkPOJXtOKdl/WfOH7Q9zbTJf6UkIcSLTxobmxIUYWGImA== X-Received: by 2002:a17:902:ea0a:b0:1bb:598a:14e5 with SMTP id s10-20020a170902ea0a00b001bb598a14e5mr24227444plg.43.1696957519183; Tue, 10 Oct 2023 10:05:19 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id w19-20020a1709027b9300b001b89536974bsm11979868pll.202.2023.10.10.10.05.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Oct 2023 10:05:18 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Greg Kroah-Hartman , Jiri Slaby Cc: Conor Dooley , Andrew Jones , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH 1/6] RISC-V: Add defines for SBI debug console extension Date: Tue, 10 Oct 2023 22:34:58 +0530 Message-Id: <20231010170503.657189-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231010170503.657189-1-apatel@ventanamicro.com> References: <20231010170503.657189-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We add SBI debug console extension related defines/enum to the asm/sbi.h header. Signed-off-by: Anup Patel --- arch/riscv/include/asm/sbi.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 5b4a1bf5f439..12dfda6bb924 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -30,6 +30,7 @@ enum sbi_ext_id { SBI_EXT_HSM =3D 0x48534D, SBI_EXT_SRST =3D 0x53525354, SBI_EXT_PMU =3D 0x504D55, + SBI_EXT_DBCN =3D 0x4442434E, =20 /* Experimentals extensions must lie within this range */ SBI_EXT_EXPERIMENTAL_START =3D 0x08000000, @@ -236,6 +237,12 @@ enum sbi_pmu_ctr_type { /* Flags defined for counter stop function */ #define SBI_PMU_STOP_FLAG_RESET (1 << 0) =20 +enum sbi_ext_dbcn_fid { + SBI_EXT_DBCN_CONSOLE_WRITE =3D 0, + SBI_EXT_DBCN_CONSOLE_READ =3D 1, + SBI_EXT_DBCN_CONSOLE_WRITE_BYTE =3D 2, +}; + #define SBI_SPEC_VERSION_DEFAULT 0x1 #define SBI_SPEC_VERSION_MAJOR_SHIFT 24 #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f --=20 2.34.1 From nobody Fri Jan 2 15:17:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DA7BCD8CAE for ; Tue, 10 Oct 2023 17:05:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234017AbjJJRFg (ORCPT ); Tue, 10 Oct 2023 13:05:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233927AbjJJRFc (ORCPT ); Tue, 10 Oct 2023 13:05:32 -0400 Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4593BDA for ; Tue, 10 Oct 2023 10:05:25 -0700 (PDT) Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-1c60f1a2652so418585ad.0 for ; Tue, 10 Oct 2023 10:05:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1696957525; x=1697562325; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=l3lhlJZP7U6sfVX0rlDY0S8d2x8DhhVnWXy5WEJL0wg=; b=Q1nvnrQhx6Vs8g9wOc7yiACALxYiSSrf2LksIxSwvXbWbC6UNECEQcClYhPtrb2p4D zMhL03nuhtA+w/QwK0+6WWFgwJJTeDB5VQ5Z1DRG78TEEd+dPGo196k6nZVzUAE9igOU RGaJDl9jfGZVKlZ5BJMl2E8ViLpZmMrFKKantddS21R5VNXvSHxuGPHNpa6iW7ICODA+ ZM0YEFQS/+M3tWpHZ1RKnQxpmHF6ICK8mkm3vPzR8aQiFT+ZXnEz7G+q3KZxoaVRlkRi wGS16TLD+YV6fZmrGM+HGbZC1GFivZ90lyTo5977Gdwvr4ESBvxvgf9mgoSHxTujZIp4 0fTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696957525; x=1697562325; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=l3lhlJZP7U6sfVX0rlDY0S8d2x8DhhVnWXy5WEJL0wg=; b=f0dp0Y+BR2eax41NVVE5wAFWAP6pCGFFYq2SVtLIDQsN2UtRw8v+lRce5R28hdVExz EDJrXW+5hd9xnYTTWj356PYDAX2ixOG8TU5YVp4uV8MZKkngPdtIOgfk96/9X1nTsYWq R6grhXTWdye4MMRLOucjVXuqX5Lh4Gb8t2lRGpO+xm9ANX6ADatfffDZLwrDgDU2rOAP ENIWKlo178utEv1LEsDBuEO0ZAl4LFHyX8fRv37CwaC9ZGpJNHbbOiZ2mLkDyXMtRGJw /DUHvQEA8+H0JgC1fy+VNJQyzeKbAu+1zJvuKeIdoaO97nEWx9BfnKwDohZIYtYOWAlU I+BA== X-Gm-Message-State: AOJu0Yw3hW7eC7qvYc+OjWVsub76APmwQDD3a6xMBnzmASjurk5HUTll HiJ0GeltNKVnFq0jyKZzID/ZHA== X-Google-Smtp-Source: AGHT+IG+mbNrQmt2GEYzZRkORnAD/EBo6KEPWJykcTVHm9mjjc11kbkmKKhIYwMGoWp8ra4yRmdzoQ== X-Received: by 2002:a17:902:d352:b0:1c6:de6:5eb4 with SMTP id l18-20020a170902d35200b001c60de65eb4mr18397397plk.13.1696957524587; Tue, 10 Oct 2023 10:05:24 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id w19-20020a1709027b9300b001b89536974bsm11979868pll.202.2023.10.10.10.05.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Oct 2023 10:05:24 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Greg Kroah-Hartman , Jiri Slaby Cc: Conor Dooley , Andrew Jones , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH 2/6] RISC-V: KVM: Change the SBI specification version to v2.0 Date: Tue, 10 Oct 2023 22:34:59 +0530 Message-Id: <20231010170503.657189-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231010170503.657189-1-apatel@ventanamicro.com> References: <20231010170503.657189-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We will be implementing SBI DBCN extension for KVM RISC-V so let us change the KVM RISC-V SBI specification version to v2.0. Signed-off-by: Anup Patel --- arch/riscv/include/asm/kvm_vcpu_sbi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm= /kvm_vcpu_sbi.h index cdcf0ff07be7..8d6d4dce8a5e 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h @@ -11,7 +11,7 @@ =20 #define KVM_SBI_IMPID 3 =20 -#define KVM_SBI_VERSION_MAJOR 1 +#define KVM_SBI_VERSION_MAJOR 2 #define KVM_SBI_VERSION_MINOR 0 =20 enum kvm_riscv_sbi_ext_status { --=20 2.34.1 From nobody Fri Jan 2 15:17:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8AABCD8CA9 for ; Tue, 10 Oct 2023 17:05:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233998AbjJJRFj (ORCPT ); Tue, 10 Oct 2023 13:05:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53828 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233978AbjJJRFd (ORCPT ); Tue, 10 Oct 2023 13:05:33 -0400 Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D14638E for ; Tue, 10 Oct 2023 10:05:30 -0700 (PDT) Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-1c9bf22fe05so5061575ad.2 for ; Tue, 10 Oct 2023 10:05:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1696957530; x=1697562330; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4smwE6VqfYxKvfF0tqu7jNc/7OXpVUXHc/+OAD0MBRk=; b=FhwWGb5Xse7nvJyYxyIZeHfhdiov1sPmpAIyzOeoCGEf39LOxkt7wfJ2Z0P8A/m678 rZFtelP2j0l+cFV4L9Fd5cfVSWv91bpzgvCS53XnUBi1zh9W1Xz36U8+NoWS9joAjSbI PIzEhCDhs/CTR2GXh1mg5mra4y83r13ciVymQInsYDZrGiCQZaGGVuYTeY9T7kjMtIJK aeud+i6Sr7MfTROpnE4KzDCOMsNYMbUUKOD2aJVn1Xog8btOol7bejKOotidRPs3u8N9 cT7AmZcOJCLaEJ70+JIuVaq/Iqpb+vIlh89lPryRr+V5veLBho8HplAufaN1fMW6m+Ks 6RwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696957530; x=1697562330; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4smwE6VqfYxKvfF0tqu7jNc/7OXpVUXHc/+OAD0MBRk=; b=rb4pnaGoL0sXjsxvP0Hw6SOJU/N/137Pv2g3OrjfHQYI3I31UrCOY5Lif/8oE+ui+q wdm/7IalD4p5Qsvitwtu9ct95QQdbbABdFVfXUMzlUj1nMY+BFLTKIi8epRwwQHUuIC0 8VTdMB4pNmOWqc79QxRAekI5K8ZtDSSCLqiNPF6+Pf4nKLgufKXwu0J/MsseZI/f4QmR wlXCrH0OD8VVH6ybk/ERlp97wIBuBOyhBW43B3poLguRSeF1timjqq/U8i+pcaIhF5XH gw1OCH2WuQzJrVpneqe6T4Nlq6zwa5niCQoKqwZAKIV29+lOks9X+NP6UPSlRWzzg0Eb mpPw== X-Gm-Message-State: AOJu0YwfL1iqKXaslnlcJ0Y8bxagtnT8FbLnfY4Y2thgmsBW4HX3way4 eFHA9Lh8AIgMn4hVQFr3TeANpg== X-Google-Smtp-Source: AGHT+IFYY1cb953bXOW6ABKFWxZoUNl8/jrL5sgqvn5jtayOnZj/D//5h5O6D4FNJ+IJsn/Z4jFWDA== X-Received: by 2002:a17:902:a402:b0:1c7:7e00:809e with SMTP id p2-20020a170902a40200b001c77e00809emr15730697plq.67.1696957529924; Tue, 10 Oct 2023 10:05:29 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id w19-20020a1709027b9300b001b89536974bsm11979868pll.202.2023.10.10.10.05.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Oct 2023 10:05:29 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Greg Kroah-Hartman , Jiri Slaby Cc: Conor Dooley , Andrew Jones , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH 3/6] RISC-V: KVM: Forward SBI DBCN extension to user-space Date: Tue, 10 Oct 2023 22:35:00 +0530 Message-Id: <20231010170503.657189-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231010170503.657189-1-apatel@ventanamicro.com> References: <20231010170503.657189-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The SBI DBCN extension needs to be emulated in user-space so let us forward console_puts() call to user-space. Signed-off-by: Anup Patel --- arch/riscv/include/asm/kvm_vcpu_sbi.h | 1 + arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu_sbi.c | 4 ++++ arch/riscv/kvm/vcpu_sbi_replace.c | 31 +++++++++++++++++++++++++++ 4 files changed, 37 insertions(+) diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm= /kvm_vcpu_sbi.h index 8d6d4dce8a5e..a85f95eb6e85 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h @@ -69,6 +69,7 @@ extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_i= pi; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_rfence; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_srst; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_hsm; +extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_dbcn; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_experimental; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_vendor; =20 diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index 917d8cc2489e..60d3b21dead7 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -156,6 +156,7 @@ enum KVM_RISCV_SBI_EXT_ID { KVM_RISCV_SBI_EXT_PMU, KVM_RISCV_SBI_EXT_EXPERIMENTAL, KVM_RISCV_SBI_EXT_VENDOR, + KVM_RISCV_SBI_EXT_DBCN, KVM_RISCV_SBI_EXT_MAX, }; =20 diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c index 9cd97091c723..b54fe52c915a 100644 --- a/arch/riscv/kvm/vcpu_sbi.c +++ b/arch/riscv/kvm/vcpu_sbi.c @@ -66,6 +66,10 @@ static const struct kvm_riscv_sbi_extension_entry sbi_ex= t[] =3D { .ext_idx =3D KVM_RISCV_SBI_EXT_PMU, .ext_ptr =3D &vcpu_sbi_ext_pmu, }, + { + .ext_idx =3D KVM_RISCV_SBI_EXT_DBCN, + .ext_ptr =3D &vcpu_sbi_ext_dbcn, + }, { .ext_idx =3D KVM_RISCV_SBI_EXT_EXPERIMENTAL, .ext_ptr =3D &vcpu_sbi_ext_experimental, diff --git a/arch/riscv/kvm/vcpu_sbi_replace.c b/arch/riscv/kvm/vcpu_sbi_re= place.c index 7c4d5d38a339..347c5856347e 100644 --- a/arch/riscv/kvm/vcpu_sbi_replace.c +++ b/arch/riscv/kvm/vcpu_sbi_replace.c @@ -175,3 +175,34 @@ const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_srst = =3D { .extid_end =3D SBI_EXT_SRST, .handler =3D kvm_sbi_ext_srst_handler, }; + +static int kvm_sbi_ext_dbcn_handler(struct kvm_vcpu *vcpu, + struct kvm_run *run, + struct kvm_vcpu_sbi_return *retdata) +{ + struct kvm_cpu_context *cp =3D &vcpu->arch.guest_context; + unsigned long funcid =3D cp->a6; + + switch (funcid) { + case SBI_EXT_DBCN_CONSOLE_WRITE: + case SBI_EXT_DBCN_CONSOLE_READ: + case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: + /* + * The SBI debug console functions are unconditionally + * forwarded to the userspace. + */ + kvm_riscv_vcpu_sbi_forward(vcpu, run); + retdata->uexit =3D true; + break; + default: + retdata->err_val =3D SBI_ERR_NOT_SUPPORTED; + } + + return 0; +} + +const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_dbcn =3D { + .extid_start =3D SBI_EXT_DBCN, + .extid_end =3D SBI_EXT_DBCN, + .handler =3D kvm_sbi_ext_dbcn_handler, +}; --=20 2.34.1 From nobody Fri Jan 2 15:17:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5FFF3CD8CA9 for ; Tue, 10 Oct 2023 17:06:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234245AbjJJRGB (ORCPT ); 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Tue, 10 Oct 2023 10:05:34 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Greg Kroah-Hartman , Jiri Slaby Cc: Conor Dooley , Andrew Jones , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH 4/6] tty/serial: Add RISC-V SBI debug console based earlycon Date: Tue, 10 Oct 2023 22:35:01 +0530 Message-Id: <20231010170503.657189-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231010170503.657189-1-apatel@ventanamicro.com> References: <20231010170503.657189-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We extend the existing RISC-V SBI earlycon support to use the new RISC-V SBI debug console extension. Signed-off-by: Anup Patel --- drivers/tty/serial/Kconfig | 2 +- drivers/tty/serial/earlycon-riscv-sbi.c | 35 ++++++++++++++++++++++--- 2 files changed, 32 insertions(+), 5 deletions(-) diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index bdc568a4ab66..cec46091a716 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -87,7 +87,7 @@ config SERIAL_EARLYCON_SEMIHOST =20 config SERIAL_EARLYCON_RISCV_SBI bool "Early console using RISC-V SBI" - depends on RISCV_SBI_V01 + depends on RISCV_SBI select SERIAL_CORE select SERIAL_CORE_CONSOLE select SERIAL_EARLYCON diff --git a/drivers/tty/serial/earlycon-riscv-sbi.c b/drivers/tty/serial/e= arlycon-riscv-sbi.c index 27afb0b74ea7..b1da34e8d8cd 100644 --- a/drivers/tty/serial/earlycon-riscv-sbi.c +++ b/drivers/tty/serial/earlycon-riscv-sbi.c @@ -10,22 +10,49 @@ #include #include =20 +#ifdef CONFIG_RISCV_SBI_V01 static void sbi_putc(struct uart_port *port, unsigned char c) { sbi_console_putchar(c); } =20 -static void sbi_console_write(struct console *con, - const char *s, unsigned n) +static void sbi_0_1_console_write(struct console *con, + const char *s, unsigned int n) { struct earlycon_device *dev =3D con->data; uart_console_write(&dev->port, s, n, sbi_putc); } +#endif + +static void sbi_dbcn_console_write(struct console *con, + const char *s, unsigned int n) +{ + phys_addr_t pa =3D __pa(s); + + sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE, +#ifdef CONFIG_32BIT + n, pa, (u64)pa >> 32, +#else + n, pa, 0, +#endif + 0, 0, 0); +} =20 static int __init early_sbi_setup(struct earlycon_device *device, const char *opt) { - device->con->write =3D sbi_console_write; - return 0; + int ret =3D 0; + + if ((sbi_spec_version >=3D sbi_mk_version(2, 0)) && + (sbi_probe_extension(SBI_EXT_DBCN) > 0)) + device->con->write =3D sbi_dbcn_console_write; + else +#ifdef CONFIG_RISCV_SBI_V01 + device->con->write =3D sbi_0_1_console_write; +#else + ret =3D -ENODEV; +#endif + + return ret; } EARLYCON_DECLARE(sbi, early_sbi_setup); --=20 2.34.1 From nobody Fri Jan 2 15:17:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 543A4CD8CA9 for ; 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Tue, 10 Oct 2023 10:05:41 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id w19-20020a1709027b9300b001b89536974bsm11979868pll.202.2023.10.10.10.05.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Oct 2023 10:05:40 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Greg Kroah-Hartman , Jiri Slaby Cc: Conor Dooley , Andrew Jones , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Atish Patra , Anup Patel Subject: [PATCH 5/6] tty: Add SBI debug console support to HVC SBI driver Date: Tue, 10 Oct 2023 22:35:02 +0530 Message-Id: <20231010170503.657189-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231010170503.657189-1-apatel@ventanamicro.com> References: <20231010170503.657189-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Atish Patra RISC-V SBI specification supports advanced debug console support via SBI DBCN extension. Extend the HVC SBI driver to support it. Signed-off-by: Atish Patra Signed-off-by: Anup Patel --- drivers/tty/hvc/Kconfig | 2 +- drivers/tty/hvc/hvc_riscv_sbi.c | 80 ++++++++++++++++++++++++++++++--- 2 files changed, 74 insertions(+), 8 deletions(-) diff --git a/drivers/tty/hvc/Kconfig b/drivers/tty/hvc/Kconfig index 4f9264d005c0..6e05c5c7bca1 100644 --- a/drivers/tty/hvc/Kconfig +++ b/drivers/tty/hvc/Kconfig @@ -108,7 +108,7 @@ config HVC_DCC_SERIALIZE_SMP =20 config HVC_RISCV_SBI bool "RISC-V SBI console support" - depends on RISCV_SBI_V01 + depends on RISCV_SBI select HVC_DRIVER help This enables support for console output via RISC-V SBI calls, which diff --git a/drivers/tty/hvc/hvc_riscv_sbi.c b/drivers/tty/hvc/hvc_riscv_sb= i.c index 31f53fa77e4a..be8b7e351840 100644 --- a/drivers/tty/hvc/hvc_riscv_sbi.c +++ b/drivers/tty/hvc/hvc_riscv_sbi.c @@ -15,6 +15,7 @@ =20 #include "hvc_console.h" =20 +#ifdef CONFIG_RISCV_SBI_V01 static int hvc_sbi_tty_put(uint32_t vtermno, const char *buf, int count) { int i; @@ -39,21 +40,86 @@ static int hvc_sbi_tty_get(uint32_t vtermno, char *buf,= int count) return i; } =20 -static const struct hv_ops hvc_sbi_ops =3D { +static const struct hv_ops hvc_sbi_v01_ops =3D { .get_chars =3D hvc_sbi_tty_get, .put_chars =3D hvc_sbi_tty_put, }; +#endif =20 -static int __init hvc_sbi_init(void) +static int hvc_sbi_dbcn_tty_put(uint32_t vtermno, const char *buf, int cou= nt) { - return PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_ops, 16)); + phys_addr_t pa; + struct sbiret ret; + + if (is_vmalloc_addr(buf)) + pa =3D page_to_phys(vmalloc_to_page(buf)) + offset_in_page(buf); + else + pa =3D __pa(buf); + + ret =3D sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE, +#ifdef CONFIG_32BIT + count, pa, (u64)pa >> 32, +#else + count, pa, 0, +#endif + 0, 0, 0); + + if (ret.error) + return 0; + + return count; } -device_initcall(hvc_sbi_init); =20 -static int __init hvc_sbi_console_init(void) +static int hvc_sbi_dbcn_tty_get(uint32_t vtermno, char *buf, int count) { - hvc_instantiate(0, 0, &hvc_sbi_ops); + phys_addr_t pa; + struct sbiret ret; + + if (is_vmalloc_addr(buf)) + pa =3D page_to_phys(vmalloc_to_page(buf)) + offset_in_page(buf); + else + pa =3D __pa(buf); + + ret =3D sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_READ, +#ifdef CONFIG_32BIT + count, pa, (u64)pa >> 32, +#else + count, pa, 0, +#endif + 0, 0, 0); + + if (ret.error) + return 0; + + return ret.value; +} + +static const struct hv_ops hvc_sbi_dbcn_ops =3D { + .put_chars =3D hvc_sbi_dbcn_tty_put, + .get_chars =3D hvc_sbi_dbcn_tty_get, +}; + +static int __init hvc_sbi_init(void) +{ + int err; + + if ((sbi_spec_version >=3D sbi_mk_version(2, 0)) && + (sbi_probe_extension(SBI_EXT_DBCN) > 0)) { + err =3D PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_dbcn_ops, 16)); + if (err) + return err; + hvc_instantiate(0, 0, &hvc_sbi_dbcn_ops); + } else { +#ifdef CONFIG_RISCV_SBI_V01 + err =3D PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_v01_ops, 16)); + if (err) + return err; + hvc_instantiate(0, 0, &hvc_sbi_v01_ops); +#else + return -ENODEV; +#endif + } =20 return 0; } -console_initcall(hvc_sbi_console_init); +device_initcall(hvc_sbi_init); --=20 2.34.1 From nobody Fri Jan 2 15:17:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 920C4CD8CAD for ; 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Tue, 10 Oct 2023 10:05:46 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id w19-20020a1709027b9300b001b89536974bsm11979868pll.202.2023.10.10.10.05.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Oct 2023 10:05:45 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Greg Kroah-Hartman , Jiri Slaby Cc: Conor Dooley , Andrew Jones , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH 6/6] RISC-V: Enable SBI based earlycon support Date: Tue, 10 Oct 2023 22:35:03 +0530 Message-Id: <20231010170503.657189-7-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231010170503.657189-1-apatel@ventanamicro.com> References: <20231010170503.657189-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Let us enable SBI based earlycon support in defconfigs for both RV32 and RV64 so that "earlycon=3Dsbi" can be used again. Signed-off-by: Anup Patel --- arch/riscv/configs/defconfig | 1 + arch/riscv/configs/rv32_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index ab86ec3b9eab..f82700da0056 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -132,6 +132,7 @@ CONFIG_SERIAL_8250_CONSOLE=3Dy CONFIG_SERIAL_8250_DW=3Dy CONFIG_SERIAL_OF_PLATFORM=3Dy CONFIG_SERIAL_SH_SCI=3Dy +CONFIG_SERIAL_EARLYCON_RISCV_SBI=3Dy CONFIG_VIRTIO_CONSOLE=3Dy CONFIG_HW_RANDOM=3Dy CONFIG_HW_RANDOM_VIRTIO=3Dy diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_de= fconfig index 89b601e253a6..5721af39afd1 100644 --- a/arch/riscv/configs/rv32_defconfig +++ b/arch/riscv/configs/rv32_defconfig @@ -66,6 +66,7 @@ CONFIG_INPUT_MOUSEDEV=3Dy CONFIG_SERIAL_8250=3Dy CONFIG_SERIAL_8250_CONSOLE=3Dy CONFIG_SERIAL_OF_PLATFORM=3Dy +CONFIG_SERIAL_EARLYCON_RISCV_SBI=3Dy CONFIG_VIRTIO_CONSOLE=3Dy CONFIG_HW_RANDOM=3Dy CONFIG_HW_RANDOM_VIRTIO=3Dy --=20 2.34.1