From nobody Fri Jan 2 17:10:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 561AACD80C1 for ; Tue, 10 Oct 2023 12:33:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231853AbjJJMd3 (ORCPT ); Tue, 10 Oct 2023 08:33:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53370 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231371AbjJJMdZ (ORCPT ); Tue, 10 Oct 2023 08:33:25 -0400 Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C2C54B0 for ; Tue, 10 Oct 2023 05:33:23 -0700 (PDT) Received: from canpemm500009.china.huawei.com (unknown [172.30.72.57]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4S4Zw61yY1zNnx2; Tue, 10 Oct 2023 20:29:26 +0800 (CST) Received: from localhost.localdomain (10.50.163.32) by canpemm500009.china.huawei.com (7.192.105.203) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.31; Tue, 10 Oct 2023 20:33:21 +0800 From: Yicong Yang To: , , , CC: , , , , , , , , Subject: [RFC PATCH 1/3] clocksource/drivers/arm_arch_timer: Split the function of __arch_timer_setup() Date: Tue, 10 Oct 2023 20:30:31 +0800 Message-ID: <20231010123033.23258-2-yangyicong@huawei.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20231010123033.23258-1-yangyicong@huawei.com> References: <20231010123033.23258-1-yangyicong@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.50.163.32] X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To canpemm500009.china.huawei.com (7.192.105.203) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yicong Yang Currently we use __arch_timer_setup() to setup and register clockevents device for both cp15 and memory-mapped timer. However there's not too much in common of the setups for cp15 and memory-mapped timer. So split the setup function for cp15 and memory-mapped timer into separate functions. This will also allows future extension for platform timers. Signed-off-by: Yicong Yang --- drivers/clocksource/arm_arch_timer.c | 105 ++++++++++++++------------- 1 file changed, 54 insertions(+), 51 deletions(-) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm= _arch_timer.c index 7dd2c615bce2..2e20a8ec50ca 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -849,65 +849,68 @@ static u64 __arch_timer_check_delta(void) return CLOCKSOURCE_MASK(arch_counter_get_width()); } =20 -static void __arch_timer_setup(unsigned type, - struct clock_event_device *clk) +static void __arch_timer_setup_cp15(struct clock_event_device *clk) { + typeof(clk->set_next_event) sne; u64 max_delta; =20 clk->features =3D CLOCK_EVT_FEAT_ONESHOT; =20 - if (type =3D=3D ARCH_TIMER_TYPE_CP15) { - typeof(clk->set_next_event) sne; - - arch_timer_check_ool_workaround(ate_match_local_cap_id, NULL); - - if (arch_timer_c3stop) - clk->features |=3D CLOCK_EVT_FEAT_C3STOP; - clk->name =3D "arch_sys_timer"; - clk->rating =3D 450; - clk->cpumask =3D cpumask_of(smp_processor_id()); - clk->irq =3D arch_timer_ppi[arch_timer_uses_ppi]; - switch (arch_timer_uses_ppi) { - case ARCH_TIMER_VIRT_PPI: - clk->set_state_shutdown =3D arch_timer_shutdown_virt; - clk->set_state_oneshot_stopped =3D arch_timer_shutdown_virt; - sne =3D erratum_handler(set_next_event_virt); - break; - case ARCH_TIMER_PHYS_SECURE_PPI: - case ARCH_TIMER_PHYS_NONSECURE_PPI: - case ARCH_TIMER_HYP_PPI: - clk->set_state_shutdown =3D arch_timer_shutdown_phys; - clk->set_state_oneshot_stopped =3D arch_timer_shutdown_phys; - sne =3D erratum_handler(set_next_event_phys); - break; - default: - BUG(); - } - - clk->set_next_event =3D sne; - max_delta =3D __arch_timer_check_delta(); - } else { - clk->features |=3D CLOCK_EVT_FEAT_DYNIRQ; - clk->name =3D "arch_mem_timer"; - clk->rating =3D 400; - clk->cpumask =3D cpu_possible_mask; - if (arch_timer_mem_use_virtual) { - clk->set_state_shutdown =3D arch_timer_shutdown_virt_mem; - clk->set_state_oneshot_stopped =3D arch_timer_shutdown_virt_mem; - clk->set_next_event =3D - arch_timer_set_next_event_virt_mem; - } else { - clk->set_state_shutdown =3D arch_timer_shutdown_phys_mem; - clk->set_state_oneshot_stopped =3D arch_timer_shutdown_phys_mem; - clk->set_next_event =3D - arch_timer_set_next_event_phys_mem; - } + arch_timer_check_ool_workaround(ate_match_local_cap_id, NULL); =20 - max_delta =3D CLOCKSOURCE_MASK(56); + if (arch_timer_c3stop) + clk->features |=3D CLOCK_EVT_FEAT_C3STOP; + clk->name =3D "arch_sys_timer"; + clk->rating =3D 450; + clk->cpumask =3D cpumask_of(smp_processor_id()); + clk->irq =3D arch_timer_ppi[arch_timer_uses_ppi]; + switch (arch_timer_uses_ppi) { + case ARCH_TIMER_VIRT_PPI: + clk->set_state_shutdown =3D arch_timer_shutdown_virt; + clk->set_state_oneshot_stopped =3D arch_timer_shutdown_virt; + sne =3D erratum_handler(set_next_event_virt); + break; + case ARCH_TIMER_PHYS_SECURE_PPI: + case ARCH_TIMER_PHYS_NONSECURE_PPI: + case ARCH_TIMER_HYP_PPI: + clk->set_state_shutdown =3D arch_timer_shutdown_phys; + clk->set_state_oneshot_stopped =3D arch_timer_shutdown_phys; + sne =3D erratum_handler(set_next_event_phys); + break; + default: + BUG(); } =20 + clk->set_next_event =3D sne; + max_delta =3D __arch_timer_check_delta(); + clk->set_state_shutdown(clk); + clockevents_config_and_register(clk, arch_timer_rate, 0xf, max_delta); +} + +static void __arch_timer_setup_mem(struct clock_event_device *clk) +{ + u64 max_delta; =20 + clk->features =3D CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ; + clk->name =3D "arch_mem_timer"; + clk->rating =3D 400; + clk->cpumask =3D cpu_possible_mask; + if (arch_timer_mem_use_virtual) { + clk->set_state_shutdown =3D arch_timer_shutdown_virt_mem; + clk->set_state_oneshot_stopped =3D arch_timer_shutdown_virt_mem; + clk->set_next_event =3D + arch_timer_set_next_event_virt_mem; + } else { + clk->set_state_shutdown =3D arch_timer_shutdown_phys_mem; + clk->set_state_oneshot_stopped =3D arch_timer_shutdown_phys_mem; + clk->set_next_event =3D + arch_timer_set_next_event_phys_mem; + } + + max_delta =3D CLOCKSOURCE_MASK(56); + + clk->set_state_shutdown(clk); clockevents_config_and_register(clk, arch_timer_rate, 0xf, max_delta); } =20 @@ -1004,7 +1007,7 @@ static int arch_timer_starting_cpu(unsigned int cpu) struct clock_event_device *clk =3D this_cpu_ptr(arch_timer_evt); u32 flags; =20 - __arch_timer_setup(ARCH_TIMER_TYPE_CP15, clk); + __arch_timer_setup_cp15(clk); =20 flags =3D check_ppi_trigger(arch_timer_ppi[arch_timer_uses_ppi]); enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], flags); @@ -1294,7 +1297,7 @@ static int __init arch_timer_mem_register(void __iome= m *base, unsigned int irq) =20 arch_timer_mem->base =3D base; arch_timer_mem->evt.irq =3D irq; - __arch_timer_setup(ARCH_TIMER_TYPE_MEM, &arch_timer_mem->evt); + __arch_timer_setup_mem(&arch_timer_mem->evt); =20 if (arch_timer_mem_use_virtual) func =3D arch_timer_handler_virt_mem; --=20 2.24.0