From nobody Sat Feb 7 16:15:36 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20C8EE81E18 for ; Mon, 9 Oct 2023 23:10:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379067AbjJIXKW (ORCPT ); Mon, 9 Oct 2023 19:10:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60022 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1379053AbjJIXKD (ORCPT ); Mon, 9 Oct 2023 19:10:03 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36D6E199B for ; Mon, 9 Oct 2023 16:09:09 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-d9a3a38b96cso1026324276.0 for ; Mon, 09 Oct 2023 16:09:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1696892949; x=1697497749; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=cXPuzl6uaVFzYoq9buwIVqk8xkxt/D9RaR/u9SrhOvY=; b=iHJXjLmXJRU/fhWhS/pN08YDqXqvAYihtia64ATrb/X+AhbfMXbpfXneicTkum1wgU UxqHnjs1+pFnxpARYTf3aIbM1GzIzXPwm9SDAyaX/efQpGT2LVh6Ob6dS3Yr7e1dQ9UA MaD/UrJsAhg/cqy4Qk/1FozGVvkgZ1aUBlFiEZMMGgMkbvBhIGUKgVv2yKThovSsIiI/ Y7UP2wiKrDplRzrbIYU+a19YoajYcPDopvQgLR3K0Jah1S9tZa9Kyl1r/GXsENh+A5LI JFqgo63m3jAkyTl/Ssl2QV0JS9MktNsOeZ5tYS50/z2uh59fGU4s6dW/GUeRIltGqAok 5gxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696892949; x=1697497749; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=cXPuzl6uaVFzYoq9buwIVqk8xkxt/D9RaR/u9SrhOvY=; b=r+uzeEz1SRLJtr8BfwAtCmqssjhy/g1Fs9RZV0zBPCmNy24PZ3epoFl15L1DnZ0Nha vFd7jJhoWVl2wThWXlvuaoeQg0k9pzGn9sSxKPkMIl5gnA06SpyG0E9ZeZJt6l/qpKIe 8Nq6IhqjvJGf6xpfaZd48AXibIORcO4mxZYeEU1X2ta4HpFq4UEqAlngRmpJNFKY2LsV aw/jxgoedh2vPmVGjtxfiGz+XqdpfOybPxiwDNVUFz4Mm+xkHsqfFmbRrzLwtmZRHh2u gDevjlzS+NdvshWARMRcxkRT0UedhWar74I4Sw17VyvfuJwGryDhSUGA4Awpbd9pRYUc qtMg== X-Gm-Message-State: AOJu0YweCIyBWbEgD5Lf1FSrDmrlOgVWYpJIl55uqbnUHipXb9rV5VuF LJW4bm+oMMuui8gqZo09rc5TJ4V9EQIB X-Google-Smtp-Source: AGHT+IG4uRulO8JptMPCQ4DX/9b0/rpuNBezzxOn6tjqyRoJZpeMXHChmkbZ2aiMwc0/drTQ5DDqedDUYX2y X-Received: from rananta-linux.c.googlers.com ([fda3:e722:ac3:cc00:2b:ff92:c0a8:20a1]) (user=rananta job=sendgmr) by 2002:a5b:584:0:b0:d7b:94f5:1301 with SMTP id l4-20020a5b0584000000b00d7b94f51301mr272090ybp.9.1696892949104; Mon, 09 Oct 2023 16:09:09 -0700 (PDT) Date: Mon, 9 Oct 2023 23:08:51 +0000 In-Reply-To: <20231009230858.3444834-1-rananta@google.com> Mime-Version: 1.0 References: <20231009230858.3444834-1-rananta@google.com> X-Mailer: git-send-email 2.42.0.609.gbb76f46606-goog Message-ID: <20231009230858.3444834-6-rananta@google.com> Subject: [PATCH v7 05/12] KVM: arm64: PMU: Add a helper to read a vCPU's PMCR_EL0 From: Raghavendra Rao Ananta To: Oliver Upton , Marc Zyngier Cc: Alexandru Elisei , James Morse , Suzuki K Poulose , Paolo Bonzini , Zenghui Yu , Shaoqin Huang , Jing Zhang , Reiji Watanabe , Colton Lewis , Raghavendra Rao Anata , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Reiji Watanabe Add a helper to read a vCPU's PMCR_EL0, and use it when KVM reads a vCPU's PMCR_EL0. The PMCR_EL0 value is tracked by a sysreg file per each vCPU. The following patches will make (only) PMCR_EL0.N track per guest. Having the new helper will be useful to combine the PMCR_EL0.N field (tracked per guest) and the other fields (tracked per vCPU) to provide the value of PMCR_EL0. No functional change intended. Signed-off-by: Reiji Watanabe Signed-off-by: Raghavendra Rao Ananta Reviewed-by: Eric Auger --- arch/arm64/kvm/arm.c | 3 +-- arch/arm64/kvm/pmu-emul.c | 21 +++++++++++++++------ arch/arm64/kvm/sys_regs.c | 6 +++--- include/kvm/arm_pmu.h | 6 ++++++ 4 files changed, 25 insertions(+), 11 deletions(-) diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 708a53b70a7b..0af4d6bbe3d3 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -854,8 +854,7 @@ static int check_vcpu_requests(struct kvm_vcpu *vcpu) } =20 if (kvm_check_request(KVM_REQ_RELOAD_PMU, vcpu)) - kvm_pmu_handle_pmcr(vcpu, - __vcpu_sys_reg(vcpu, PMCR_EL0)); + kvm_pmu_handle_pmcr(vcpu, kvm_vcpu_read_pmcr(vcpu)); =20 if (kvm_check_request(KVM_REQ_RESYNC_PMU_EL0, vcpu)) kvm_vcpu_pmu_restore_guest(vcpu); diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index cc30c246c010..a161d6266a5c 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -72,7 +72,7 @@ static bool kvm_pmc_is_64bit(struct kvm_pmc *pmc) =20 static bool kvm_pmc_has_64bit_overflow(struct kvm_pmc *pmc) { - u64 val =3D __vcpu_sys_reg(kvm_pmc_to_vcpu(pmc), PMCR_EL0); + u64 val =3D kvm_vcpu_read_pmcr(kvm_pmc_to_vcpu(pmc)); =20 return (pmc->idx < ARMV8_PMU_CYCLE_IDX && (val & ARMV8_PMU_PMCR_LP)) || (pmc->idx =3D=3D ARMV8_PMU_CYCLE_IDX && (val & ARMV8_PMU_PMCR_LC)); @@ -250,7 +250,7 @@ void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu) =20 u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu) { - u64 val =3D __vcpu_sys_reg(vcpu, PMCR_EL0) >> ARMV8_PMU_PMCR_N_SHIFT; + u64 val =3D kvm_vcpu_read_pmcr(vcpu) >> ARMV8_PMU_PMCR_N_SHIFT; =20 val &=3D ARMV8_PMU_PMCR_N_MASK; if (val =3D=3D 0) @@ -272,7 +272,7 @@ void kvm_pmu_enable_counter_mask(struct kvm_vcpu *vcpu,= u64 val) if (!kvm_vcpu_has_pmu(vcpu)) return; =20 - if (!(__vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E) || !val) + if (!(kvm_vcpu_read_pmcr(vcpu) & ARMV8_PMU_PMCR_E) || !val) return; =20 for (i =3D 0; i < ARMV8_PMU_MAX_COUNTERS; i++) { @@ -324,7 +324,7 @@ static u64 kvm_pmu_overflow_status(struct kvm_vcpu *vcp= u) { u64 reg =3D 0; =20 - if ((__vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E)) { + if ((kvm_vcpu_read_pmcr(vcpu) & ARMV8_PMU_PMCR_E)) { reg =3D __vcpu_sys_reg(vcpu, PMOVSSET_EL0); reg &=3D __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); reg &=3D __vcpu_sys_reg(vcpu, PMINTENSET_EL1); @@ -426,7 +426,7 @@ static void kvm_pmu_counter_increment(struct kvm_vcpu *= vcpu, { int i; =20 - if (!(__vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E)) + if (!(kvm_vcpu_read_pmcr(vcpu) & ARMV8_PMU_PMCR_E)) return; =20 /* Weed out disabled counters */ @@ -569,7 +569,7 @@ void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) static bool kvm_pmu_counter_is_enabled(struct kvm_pmc *pmc) { struct kvm_vcpu *vcpu =3D kvm_pmc_to_vcpu(pmc); - return (__vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E) && + return (kvm_vcpu_read_pmcr(vcpu) & ARMV8_PMU_PMCR_E) && (__vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & BIT(pmc->idx)); } =20 @@ -1084,3 +1084,12 @@ u8 kvm_arm_pmu_get_pmuver_limit(void) ID_AA64DFR0_EL1_PMUVer_V3P5); return FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), tmp); } + +/** + * kvm_vcpu_read_pmcr - Read PMCR_EL0 register for the vCPU + * @vcpu: The vcpu pointer + */ +u64 kvm_vcpu_read_pmcr(struct kvm_vcpu *vcpu) +{ + return __vcpu_sys_reg(vcpu, PMCR_EL0); +} diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 08af7824e9d8..ff0f7095eaca 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -803,7 +803,7 @@ static bool access_pmcr(struct kvm_vcpu *vcpu, struct s= ys_reg_params *p, * Only update writeable bits of PMCR (continuing into * kvm_pmu_handle_pmcr() as well) */ - val =3D __vcpu_sys_reg(vcpu, PMCR_EL0); + val =3D kvm_vcpu_read_pmcr(vcpu); val &=3D ~ARMV8_PMU_PMCR_MASK; val |=3D p->regval & ARMV8_PMU_PMCR_MASK; if (!kvm_supports_32bit_el0()) @@ -811,7 +811,7 @@ static bool access_pmcr(struct kvm_vcpu *vcpu, struct s= ys_reg_params *p, kvm_pmu_handle_pmcr(vcpu, val); } else { /* PMCR.P & PMCR.C are RAZ */ - val =3D __vcpu_sys_reg(vcpu, PMCR_EL0) + val =3D kvm_vcpu_read_pmcr(vcpu) & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); p->regval =3D val; } @@ -860,7 +860,7 @@ static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu= , u64 idx) { u64 pmcr, val; =20 - pmcr =3D __vcpu_sys_reg(vcpu, PMCR_EL0); + pmcr =3D kvm_vcpu_read_pmcr(vcpu); val =3D (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK; if (idx >=3D val && idx !=3D ARMV8_PMU_CYCLE_IDX) { kvm_inject_undefined(vcpu); diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index 858ed9ce828a..cd980d78b86b 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -103,6 +103,7 @@ void kvm_vcpu_pmu_resync_el0(void); u8 kvm_arm_pmu_get_pmuver_limit(void); int kvm_arm_set_default_pmu(struct kvm *kvm); =20 +u64 kvm_vcpu_read_pmcr(struct kvm_vcpu *vcpu); #else struct kvm_pmu { }; @@ -180,6 +181,11 @@ static inline int kvm_arm_set_default_pmu(struct kvm *= kvm) return -ENODEV; } =20 +static inline u64 kvm_vcpu_read_pmcr(struct kvm_vcpu *vcpu) +{ + return 0; +} + #endif =20 #endif --=20 2.42.0.609.gbb76f46606-goog