From nobody Sun Feb 8 13:07:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8794E95A67 for ; Sun, 8 Oct 2023 13:06:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344793AbjJHNGT (ORCPT ); Sun, 8 Oct 2023 09:06:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33956 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344746AbjJHNGM (ORCPT ); Sun, 8 Oct 2023 09:06:12 -0400 Received: from vps.xff.cz (vps.xff.cz [195.181.215.36]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4B994B6 for ; Sun, 8 Oct 2023 06:06:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xff.cz; s=mail; t=1696770367; bh=lCxrvJiIvXZ0HfTe8LyeC4TXQ7SH+n5WoJvO6bicxbg=; h=From:To:Cc:Subject:Date:References:From; b=yvwRmuIGJN9AkL4zeoVM34YZ6YaTTNIT8x9MWtLKCPgnrrJ67rNJrLlK4mi4ndEf9 FLXR6rdD3YxsuxVSaNhw4V5kzR1IgkVRzqq7yYUyg0XwH4nSpROYAfd3oJa8Q1zh0h 7AXIA4bV3O4z9oSXxWyD0MqQ7EeU9iFBFKnh4RLs= From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Ondrej Jirman , Jagan Teki , Jonas Karlman , Chris Morgan , Sebastian Reichel , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] arm64: dts: rockchip: rk3588s-pinctrl: Add I2S2 M0 pin definitions Date: Sun, 8 Oct 2023 15:04:59 +0200 Message-ID: <20231008130515.1155664-2-megi@xff.cz> In-Reply-To: <20231008130515.1155664-1-megi@xff.cz> References: <20231008130515.1155664-1-megi@xff.cz> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Ondrej Jirman This is used on Orange Pi 5 Plus. Signed-off-by: Ondrej Jirman --- .../boot/dts/rockchip/rk3588s-pinctrl.dtsi | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi b/arch/arm64= /boot/dts/rockchip/rk3588s-pinctrl.dtsi index 48181671eacb..72708b1d8036 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi @@ -1349,6 +1349,41 @@ i2s1m1_sdo3: i2s1m1-sdo3 { }; =20 i2s2 { + /omit-if-no-ref/ + i2s2m0_lrck: i2s2m0-lrck { + rockchip,pins =3D + /* i2s2m0_lrck */ + <2 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_mclk: i2s2m0-mclk { + rockchip,pins =3D + /* i2s2m0_mclk */ + <2 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sclk: i2s2m0-sclk { + rockchip,pins =3D + /* i2s2m0_sclk */ + <2 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdi: i2s2m0-sdi { + rockchip,pins =3D + /* i2s2m0_sdi */ + <2 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdo: i2s2m0-sdo { + rockchip,pins =3D + /* i2s2m0_sdo */ + <4 RK_PC3 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ i2s2m1_lrck: i2s2m1-lrck { rockchip,pins =3D --=20 2.42.0 From nobody Sun Feb 8 13:07:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8662E95A67 for ; Sun, 8 Oct 2023 13:06:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344781AbjJHNGO (ORCPT ); Sun, 8 Oct 2023 09:06:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33978 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344755AbjJHNGM (ORCPT ); Sun, 8 Oct 2023 09:06:12 -0400 Received: from vps.xff.cz (vps.xff.cz [195.181.215.36]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 51B63C6 for ; Sun, 8 Oct 2023 06:06:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xff.cz; s=mail; t=1696770368; bh=RR80q5tjzziqB2LGjQvlUWzbTeLf/Y2/TnpugtEscbc=; h=From:To:Cc:Subject:Date:References:From; b=BlWThhwOsaTCvKljn7BTZAw3iQakA826UlbM0OoCmagHD1bjxNlrI/LdEPjaC0svc hCCiteZ8MDBBTSkdHs1J77QARJsXNT+rT9VfKmSswPSf3F6ioYauMPhO2Byk5q6sVm dzyWp43+9iaxS5Epft3trtmtQk0aATP2WW3NB6UY= From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Ondrej Jirman , Jagan Teki , Jonas Karlman , Chris Morgan , Sebastian Reichel , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/4] arm64: dts: rockchip: rk3588s-pinctrl: Add UART9 M0 pin definitions Date: Sun, 8 Oct 2023 15:05:00 +0200 Message-ID: <20231008130515.1155664-3-megi@xff.cz> In-Reply-To: <20231008130515.1155664-1-megi@xff.cz> References: <20231008130515.1155664-1-megi@xff.cz> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Ondrej Jirman This is used on Orange Pi 5 Plus. Signed-off-by: Ondrej Jirman --- arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi b/arch/arm64= /boot/dts/rockchip/rk3588s-pinctrl.dtsi index 72708b1d8036..63151d9d2377 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi @@ -3342,6 +3342,15 @@ uart8_xfer: uart8-xfer { }; =20 uart9 { + /omit-if-no-ref/ + uart9m0_xfer: uart9m0-xfer { + rockchip,pins =3D + /* uart9_rx_m0 */ + <2 RK_PC4 10 &pcfg_pull_up>, + /* uart9_tx_m0 */ + <2 RK_PC2 10 &pcfg_pull_up>; + }; + /omit-if-no-ref/ uart9m1_xfer: uart9m1-xfer { rockchip,pins =3D --=20 2.42.0 From nobody Sun Feb 8 13:07:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33056E95A82 for ; Sun, 8 Oct 2023 13:06:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344789AbjJHNGR (ORCPT ); Sun, 8 Oct 2023 09:06:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33962 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344772AbjJHNGM (ORCPT ); Sun, 8 Oct 2023 09:06:12 -0400 Received: from vps.xff.cz (vps.xff.cz [195.181.215.36]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4BAB6B9 for ; Sun, 8 Oct 2023 06:06:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xff.cz; s=mail; t=1696770368; bh=SGueJWzRUgwjjh8gQok9lNmS9RZL18PVUdYVO6wswxM=; h=From:To:Cc:Subject:Date:References:From; b=Vl/UOEyQifLbMzsnIH/o3Z1kNXYmYAFI3U2C/EsSJuQw4AI3Liq5r4meui1nAJjzf /8FqZzIDVgsQMf+yb4SmCEymsNLDY64FI3KMgvodwOOrXQ3zLVcRSJVI+HCdiIPetv bqT2bBngbwCTcodtYrI9d58zzTWbAwnfZPNqeR8k= From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Ondrej Jirman , Jagan Teki , Jonas Karlman , Chris Morgan , Sebastian Reichel , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/4] dt-bindings: arm: rockchip: Add Orange Pi 5 Plus Date: Sun, 8 Oct 2023 15:05:01 +0200 Message-ID: <20231008130515.1155664-4-megi@xff.cz> In-Reply-To: <20231008130515.1155664-1-megi@xff.cz> References: <20231008130515.1155664-1-megi@xff.cz> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Ondrej Jirman Add devicetree binding documentation for Orange Pi 5 Plus SBC made by Xunlong. Signed-off-by: Ondrej Jirman Acked-by: Conor Dooley --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index ca5389862887..1a636ad540ce 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -870,6 +870,11 @@ properties: - const: tronsmart,orion-r68-meta - const: rockchip,rk3368 =20 + - description: Xunlong Orange Pi 5 Plus + items: + - const: xunlong,orangepi-5-plus + - const: rockchip,rk3588 + - description: Xunlong Orange Pi R1 Plus / LTS items: - enum: --=20 2.42.0 From nobody Sun Feb 8 13:07:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D2A7E95A67 for ; Sun, 8 Oct 2023 13:06:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344803AbjJHNGW (ORCPT ); Sun, 8 Oct 2023 09:06:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34010 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344780AbjJHNGO (ORCPT ); Sun, 8 Oct 2023 09:06:14 -0400 Received: from vps.xff.cz (vps.xff.cz [195.181.215.36]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 66042CA for ; Sun, 8 Oct 2023 06:06:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xff.cz; s=mail; t=1696770368; bh=UtLcuHUKsPeXalAFx6dSWwhiurGc+Cnx/2tluFulNXQ=; h=From:To:Cc:Subject:Date:References:From; b=138Mbo4iuOg60/RnXaB92WtbNoHMM6V6VH29yvg7jGfkzQUcpz4o2ZCROD4HU2McX YIE7YWjU5Z/++sS7R5K4pwu5NygqvVhwkREiYRhkEPPg5Wc1+XbA99Wbv5PwSU+g4S GWLJk9BBI37zLdYWQjo0ztoq3XDzWaQd6UhOTK8E= From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Ondrej Jirman , Jagan Teki , Jonas Karlman , Chris Morgan , Sebastian Reichel , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/4] arm64: dts: rk3588-orangepi-5-plus: Add board device tree Date: Sun, 8 Oct 2023 15:05:02 +0200 Message-ID: <20231008130515.1155664-5-megi@xff.cz> In-Reply-To: <20231008130515.1155664-1-megi@xff.cz> References: <20231008130515.1155664-1-megi@xff.cz> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ondrej Jirman Orange Pi 5 Plus is RK3588 based SBC featuring: - 2x 2.5G ethernet ports =E2=80=93 onboard NIC hooked to PCIe 2.0 interface - 2x USB 2.0 host ports - 2x USB 3.0 host ports (exposed over USB 3.0 hub) - Type-C port featuring USB 2.0/3.0 and Alt-DP mode - PCIe 2.0/USB 2.0/I2S/I2C/UART on E.KEY socket - RTC - ES8388 on-board sound codec =E2=80=93 jack in/out, onboard mic, speaker a= mplifier - SPI NOR flash - RGB LED (R is always on) - IR receiver - PCIe 3.0 on the bottom for NVMe, etc. - 40pin GPIO header (with gpio, I2C, SPI, PWM, UART) - Power, recovery and Mask ROM buttons - 2x HDMI out, 1x HDMI in - Slots/connectors for eMMC, uSD card, fan, MIPI CSI/DSI Signed-off-by: Ondrej Jirman --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3588-orangepi-5-plus.dts | 857 ++++++++++++++++++ 2 files changed, 858 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index e7728007fd1b..7f340e2a4875 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -101,6 +101,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-edgeble-neu6a-i= o.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-edgeble-neu6b-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-nanopc-t6.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-orangepi-5-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-rock-5b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-indiedroid-nova.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-khadas-edge2.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts b/arch= /arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts new file mode 100644 index 000000000000..b74c4f96c60a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts @@ -0,0 +1,857 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Ond=C5=99ej Jirman + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "rk3588.dtsi" + +/ { + model =3D "Xunlong Orange Pi 5 Plus"; + compatible =3D "xunlong,orangepi-5-plus", "rockchip,rk3588"; + + aliases { + mmc0 =3D &sdhci; + mmc1 =3D &sdmmc; + serial2 =3D &uart2; + }; + + chosen { + stdout-path =3D "serial2:1500000n8"; + }; + + adc-keys-0 { + compatible =3D "adc-keys"; + io-channels =3D <&saradc 0>; + io-channel-names =3D "buttons"; + keyup-threshold-microvolt =3D <1800000>; + poll-interval =3D <100>; + + button-maskrom { + linux,code =3D ; + label =3D "Mask Rom"; + press-threshold-microvolt =3D <2000>; + }; + }; + + adc-keys-1 { + compatible =3D "adc-keys"; + io-channels =3D <&saradc 1>; + io-channel-names =3D "buttons"; + keyup-threshold-microvolt =3D <1800000>; + poll-interval =3D <100>; + + button-recovery { + linux,code =3D ; + label =3D "Recovery"; + press-threshold-microvolt =3D <2000>; + }; + }; + + speaker_amp: speaker-audio-amplifier { + compatible =3D "simple-audio-amplifier"; + enable-gpios =3D <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + sound-name-prefix =3D "Speaker Amp"; + }; + + headphone_amp: headphones-audio-amplifier { + compatible =3D "simple-audio-amplifier"; + enable-gpios =3D <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + sound-name-prefix =3D "Headphones Amp"; + }; + + ir-receiver { + compatible =3D "gpio-ir-receiver"; + gpios =3D <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ir_receiver_pin>; + }; + + gpio-leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&blue_led_pin>; + + led { + color =3D ; + function =3D LED_FUNCTION_INDICATOR; + function-enumerator =3D <1>; + gpios =3D <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + }; + }; + + fan: pwm-fan { + compatible =3D "pwm-fan"; + cooling-levels =3D <0 70 75 80 100>; + fan-supply =3D <&vcc5v0_sys>; + pwms =3D <&pwm3 0 50000 0>; + #cooling-cells =3D <2>; + }; + + pwm-leds { + compatible =3D "pwm-leds"; + + led { + color =3D ; + function =3D LED_FUNCTION_INDICATOR; + function-enumerator =3D <2>; + max-brightness =3D <255>; + pwms =3D <&pwm2 0 25000 0>; + }; + }; + + sound { + compatible =3D "simple-audio-card"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hp_detect>; + simple-audio-card,name =3D "Analog"; + simple-audio-card,aux-devs =3D <&speaker_amp>, <&headphone_amp>; + simple-audio-card,format =3D "i2s"; + simple-audio-card,mclk-fs =3D <256>; + simple-audio-card,hp-det-gpio =3D <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>; + simple-audio-card,bitclock-master =3D <&daicpu>; + simple-audio-card,frame-master =3D <&daicpu>; + /*TODO: SARADC_IN3 is used as MIC detection / key input */ + + simple-audio-card,widgets =3D + "Microphone", "Onboard Microphone", + "Microphone", "Microphone Jack", + "Speaker", "Speaker", + "Headphone", "Headphones"; + + simple-audio-card,routing =3D + "Headphones", "LOUT1", + "Headphones", "ROUT1", + "Speaker", "LOUT2", + "Speaker", "ROUT2", + + "Headphones", "Headphones Amp OUTL", + "Headphones", "Headphones Amp OUTR", + "Headphones Amp INL", "LOUT1", + "Headphones Amp INR", "ROUT1", + + "Speaker", "Speaker Amp OUTL", + "Speaker", "Speaker Amp OUTR", + "Speaker Amp INL", "LOUT2", + "Speaker Amp INR", "ROUT2", + + /* single ended signal to LINPUT1 */ + "LINPUT1", "Microphone Jack", + "RINPUT1", "Microphone Jack", + /* differential signal */ + "LINPUT2", "Onboard Microphone", + "RINPUT2", "Onboard Microphone"; + + daicpu: simple-audio-card,cpu { + sound-dai =3D <&i2s0_8ch>; + system-clock-frequency =3D <12288000>; + }; + + daicodec: simple-audio-card,codec { + sound-dai =3D <&es8388>; + system-clock-frequency =3D <12288000>; + }; + }; + + vcc3v3_pcie30: vcc3v3-pcie30-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_pcie30"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + enable-active-high; + gpios =3D <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; + startup-delay-us =3D <5000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc3v3_pcie_eth: vcc3v3-pcie-eth-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_pcie_eth"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpios =3D <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; + startup-delay-us =3D <50000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc3v3_wf: vcc3v3-wf-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_wf"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + enable-active-high; + gpios =3D <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + startup-delay-us =3D <50000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + }; + + vcc5v0_usb20: vcc5v0-usb20-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_usb20"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc5v0_usb20_en>; + vin-supply =3D <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status =3D "okay"; +}; + +&combphy1_ps { + status =3D "okay"; +}; + +&combphy2_psu { + status =3D "okay"; +}; + +&cpu_b0 { + cpu-supply =3D <&vdd_cpu_big0_s0>; + mem-supply =3D <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b1 { + cpu-supply =3D <&vdd_cpu_big0_s0>; + mem-supply =3D <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply =3D <&vdd_cpu_big1_s0>; + mem-supply =3D <&vdd_cpu_big1_mem_s0>; +}; + +&cpu_b3 { + cpu-supply =3D <&vdd_cpu_big1_s0>; + mem-supply =3D <&vdd_cpu_big1_mem_s0>; +}; + +&cpu_l0 { + cpu-supply =3D <&vdd_cpu_lit_s0>; + mem-supply =3D <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l1 { + cpu-supply =3D <&vdd_cpu_lit_s0>; + mem-supply =3D <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l2 { + cpu-supply =3D <&vdd_cpu_lit_s0>; + mem-supply =3D <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l3 { + cpu-supply =3D <&vdd_cpu_lit_s0>; + mem-supply =3D <&vdd_cpu_lit_mem_s0>; +}; + +&i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0m2_xfer>; + status =3D "okay"; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: regulator@42 { + compatible =3D "rockchip,rk8602"; + reg =3D <0x42>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <1050000>; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: regulator@43 { + compatible =3D "rockchip,rk8603", "rockchip,rk8602"; + reg =3D <0x43>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <1050000>; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + clock-frequency =3D <400000>; + status =3D "okay"; + + hym8563: rtc@51 { + compatible =3D "haoyu,hym8563"; + reg =3D <0x51>; + #clock-cells =3D <0>; + clock-output-names =3D "hym8563"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hym8563_int>; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + wakeup-source; + }; +}; + +&i2c7 { + status =3D "okay"; + + /* PLDO2 vcca 1.8V, BUCK8 gated by PLDO2 being enabled */ + es8388: audio-codec@11 { + compatible =3D "everest,es8388"; + reg =3D <0x11>; + clocks =3D <&cru I2S0_8CH_MCLKOUT>; + clock-names =3D "mclk"; + AVDD-supply =3D <&vcc_1v8_s0>; + DVDD-supply =3D <&vcc_1v8_s0>; + HPVDD-supply =3D <&vcc_3v3_s0>; + PVDD-supply =3D <&vcc_3v3_s0>; + assigned-clocks =3D <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates =3D <12288000>; + #sound-dai-cells =3D <0>; + }; +}; + +&i2s0_8ch { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status =3D "okay"; +}; + +&i2s2_2ch { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2s2m0_lrck + &i2s2m0_sclk + &i2s2m0_sdi + &i2s2m0_sdo>; + status =3D "okay"; +}; + +/* phy1 - M.KEY socket */ +&pcie2x1l0 { + reset-gpios =3D <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_wf>; + status =3D "okay"; +}; + +/* phy2 - right ethernet port */ +&pcie2x1l1 { + reset-gpios =3D <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_pcie_eth>; + status =3D "okay"; +}; + +/* phy0 - left ethernet port */ +&pcie2x1l2 { + reset-gpios =3D <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_pcie_eth>; + status =3D "okay"; +}; + +&pcie30phy { + status =3D "okay"; +}; + +&pcie3x4 { + reset-gpios =3D <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_pcie30>; + status =3D "okay"; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins =3D <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + blue_led_pin: blue-led { + rockchip,pins =3D <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + ir-receiver { + ir_receiver_pin: ir-receiver-pin { + rockchip,pins =3D <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sound { + hp_detect: hp-detect { + rockchip,pins =3D <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_usb20_en: vcc5v0-usb20-en { + rockchip,pins =3D <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm2 { + status =3D "okay"; + pinctrl-0 =3D <&pwm2m1_pins>; + pinctrl-names =3D "default"; +}; + +&pwm3 { + status =3D "okay"; + pinctrl-0 =3D <&pwm3m1_pins>; +}; + +&saradc { + status =3D "okay"; + vref-supply =3D <&vcc_1v8_s0>; +}; + +&sdhci { + bus-width =3D <8>; + no-sdio; + no-sd; + non-removable; + max-frequency =3D <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status =3D "okay"; +}; + +&sdmmc { + bus-width =3D <4>; + cap-sd-highspeed; + cd-gpios =3D <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency =3D <150000000>; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply =3D <&vcc_3v3_s3>; + vqmmc-supply =3D <&vccio_sd_s0>; + status =3D "okay"; +}; + +&sfc { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&fspim1_pins>; + status =3D "okay"; + + spi_flash: flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0x0>; + spi-max-frequency =3D <100000000>; + spi-rx-bus-width =3D <4>; + spi-tx-bus-width =3D <1>; + }; +}; + +&spi2 { + assigned-clocks =3D <&cru CLK_SPI2>; + assigned-clock-rates =3D <200000000>; + num-cs =3D <1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi2m2_cs0 &spi2m2_pins>; + status =3D "okay"; + + pmic@0 { + compatible =3D "rockchip,rk806"; + reg =3D <0x0>; + interrupt-parent =3D <&gpio0>; + interrupts =3D <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + rockchip,system-power-controller; + spi-max-frequency =3D <1000000>; + + vcc1-supply =3D <&vcc5v0_sys>; + vcc2-supply =3D <&vcc5v0_sys>; + vcc3-supply =3D <&vcc5v0_sys>; + vcc4-supply =3D <&vcc5v0_sys>; + vcc5-supply =3D <&vcc5v0_sys>; + vcc6-supply =3D <&vcc5v0_sys>; + vcc7-supply =3D <&vcc5v0_sys>; + vcc8-supply =3D <&vcc5v0_sys>; + vcc9-supply =3D <&vcc5v0_sys>; + vcc10-supply =3D <&vcc5v0_sys>; + vcc11-supply =3D <&vcc_2v0_pldo_s3>; + vcc12-supply =3D <&vcc5v0_sys>; + vcc13-supply =3D <&vdd2_ddr_s3>; + vcc14-supply =3D <&vdd2_ddr_s3>; + vcca-supply =3D <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells =3D <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-enable-ramp-delay =3D <400>; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-name =3D "vdd_gpu_s0"; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-name =3D "vdd_cpu_lit_s0"; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <825000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <825000>; + regulator-name =3D "vdd_vdenc_s0"; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <900000>; + regulator-name =3D "vdd_ddr_s0"; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <2000000>; + regulator-max-microvolt =3D <2000000>; + regulator-name =3D "vdd_2v0_pldo_s3"; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + /* shorted to avcc_1v8_s0 on the board */ + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-name =3D "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc_3v3_s0"; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vccio_sd_s0"; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-name =3D "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + /* + * The schematic mentions that actual setting + * should be 0.8375V. RK3588 datasheet specifies + * maximum as 0.825V. So we set datasheet max + * here. + */ + regulator-min-microvolt =3D <825000>; + regulator-max-microvolt =3D <825000>; + regulator-name =3D "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-name =3D "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status =3D "okay"; +}; + +&u2phy2 { + status =3D "okay"; +}; + +&u2phy3 { + status =3D "okay"; +}; + +&u2phy2_host { + phy-supply =3D <&vcc5v0_usb20>; + status =3D "okay"; +}; + +&u2phy3_host { + phy-supply =3D <&vcc5v0_usb20>; + status =3D "okay"; +}; + +&uart2 { + pinctrl-0 =3D <&uart2m0_xfer>; + status =3D "okay"; +}; + +&uart9 { + pinctrl-0 =3D <&uart9m0_xfer>; + status =3D "okay"; +}; + +&usb_host0_ehci { + status =3D "okay"; +}; + +&usb_host0_ohci { + status =3D "okay"; +}; + +&usb_host1_ehci { + status =3D "okay"; +}; + +&usb_host1_ohci { + status =3D "okay"; +}; --=20 2.42.0