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[92.34.211.33]) by smtp.gmail.com with ESMTPSA id c9-20020a2e9d89000000b002b6ffa50896sm1144130ljj.128.2023.10.07.05.32.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Oct 2023 05:32:43 -0700 (PDT) From: Linus Walleij Date: Sat, 07 Oct 2023 14:32:40 +0200 Subject: [PATCH] ARM: dts: ixp4xx: Add USRobotics USR8200 device tree MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231007-ixp4xx-usr8200-v1-1-aded3d6ff6f1@linaro.org> X-B4-Tracking: v=1; b=H4sIAOdPIWUC/x3MQQqAIBBA0avErBMms7CuEi0sx5qNhVII4t2Tl m/xf4ZIgSnC3GQI9HLky1d0bQP7afxBgm01SJQ9Tt0kON0qJfHEoCWi2KRCbUe3GztAje5AjtM /XNZSPmPN2/lgAAAA To: Howard Harte , Linus Walleij , Krzysztof Halasa Cc: Imre Kaloz , Ted Hess , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Linus Walleij X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This is a USRobotics NAS/Firewall/router that has been supported by OpenWrt in the past. It had dedicated users so let's get it properly supported. Some debugging and fixing was provided by Howard Harte. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/intel/ixp/Makefile | 3 +- .../intel/ixp/intel-ixp42x-usrobotics-usr8200.dts | 229 +++++++++++++++++= ++++ 2 files changed, 231 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/intel/ixp/Makefile b/arch/arm/boot/dts/intel= /ixp/Makefile index 1a25ce3cf84f..ab8525f1ea1d 100644 --- a/arch/arm/boot/dts/intel/ixp/Makefile +++ b/arch/arm/boot/dts/intel/ixp/Makefile @@ -16,4 +16,5 @@ dtb-$(CONFIG_ARCH_IXP4XX) +=3D \ intel-ixp43x-gateworks-gw2358.dtb \ intel-ixp42x-netgear-wg302v1.dtb \ intel-ixp42x-arcom-vulcan.dtb \ - intel-ixp42x-gateway-7001.dtb + intel-ixp42x-gateway-7001.dtb \ + intel-ixp42x-usrobotics-usr8200.dtb diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dt= s b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts new file mode 100644 index 000000000000..90fd51b36e7d --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for the USRobotics USR8200 firewall + * VPN and NAS. Based on know-how from Peter Denison. + * + * This machine is based on IXP422, the USR internal codename + * is "Jeeves". + */ + +/dts-v1/; + +#include "intel-ixp42x.dtsi" +#include + +/ { + model =3D "USRobotics USR8200"; + compatible =3D "usr,usr8200", "intel,ixp42x"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + memory@0 { + device_type =3D "memory"; + reg =3D <0x00000000 0x4000000>; + }; + + chosen { + bootargs =3D "console=3DttyS0,115200n8"; + stdout-path =3D "uart1:115200n8"; + }; + + aliases { + /* These are switched around */ + serial0 =3D &uart1; + serial1 =3D &uart0; + }; + + leds { + compatible =3D "gpio-leds"; + ieee1394_led: led-1394 { + label =3D "usr8200:green:1394"; + gpios =3D <&gpio0 0 GPIO_ACTIVE_LOW>; + default-state =3D "off"; + }; + usb1_led: led-usb1 { + label =3D "usr8200:green:usb1"; + gpios =3D <&gpio0 1 GPIO_ACTIVE_LOW>; + default-state =3D "off"; + }; + usb2_led: led-usb2 { + label =3D "usr8200:green:usb2"; + gpios =3D <&gpio0 2 GPIO_ACTIVE_LOW>; + default-state =3D "off"; + }; + wireless_led: led-wireless { + /* + * This LED is mounted inside the case but cannot be + * seen from the outside: probably USR planned at one + * point for the device to have a wireless card, then + * changed their mind and didn't mount it, leaving the + * LED in place. + */ + label =3D "usr8200:green:wireless"; + gpios =3D <&gpio0 3 GPIO_ACTIVE_LOW>; + default-state =3D "off"; + }; + pwr_led: led-pwr { + label =3D "usr8200:green:pwr"; + gpios =3D <&gpio0 14 GPIO_ACTIVE_HIGH>; + default-state =3D "on"; + linux,default-trigger =3D "heartbeat"; + }; + }; + + gpio_keys { + compatible =3D "gpio-keys"; + + button-reset { + wakeup-source; + linux,code =3D ; + label =3D "reset"; + gpios =3D <&gpio0 12 GPIO_ACTIVE_LOW>; + }; + }; + + soc { + bus@c4000000 { + flash@0,0 { + compatible =3D "intel,ixp4xx-flash", "cfi-flash"; + bank-width =3D <2>; + /* Enable writes on the expansion bus */ + intel,ixp4xx-eb-write-enable =3D <1>; + /* 16 MB of Flash mapped in at CS0 */ + reg =3D <0 0x00000000 0x1000000>; + + partitions { + compatible =3D "redboot-fis"; + /* Eraseblock at 0x0fe0000 */ + fis-index-block =3D <0x7f>; + }; + }; + rtc@2,0 { + /* EPSON RTC7301 DG DIL-capsule */ + compatible =3D "epson,rtc7301dg"; + /* + * These timing settings were found in the boardfile patch: + * IXP4XX_EXP_CS2 =3D 0x3fff000 | IXP4XX_EXP_BUS_SIZE(0) | IXP4XX_EXP_= BUS_WR_EN | + * IXP4XX_EXP_BUS_CS_EN | IXP4XX_EXP_BUS_BYTE_EN; + */ + intel,ixp4xx-eb-t1 =3D <0>; // no cycles extra address phase + intel,ixp4xx-eb-t2 =3D <0>; // no cycles extra setup phase + intel,ixp4xx-eb-t3 =3D <15>; // 15 cycles extra strobe phase + intel,ixp4xx-eb-t4 =3D <3>; // 3 cycles extra hold phase + intel,ixp4xx-eb-t5 =3D <15>; // 15 cycles extra recovery phase + intel,ixp4xx-eb-cycle-type =3D <0>; // Intel cycle + intel,ixp4xx-eb-byte-access-on-halfword =3D <0>; + intel,ixp4xx-eb-mux-address-and-data =3D <0>; + intel,ixp4xx-eb-ahb-split-transfers =3D <0>; + intel,ixp4xx-eb-write-enable =3D <1>; + intel,ixp4xx-eb-byte-access =3D <1>; + /* 512 bytes at CS2 */ + reg =3D <2 0x00000000 0x0000200>; + reg-io-width =3D <1>; + native-endian; + /* FIXME: try to check if there is an IRQ for the RTC? */ + }; + }; + + pci@c0000000 { + status =3D "okay"; + + /* + * Taken from USR8200 boardfile from OpenWrt + * + * We have 3 slots (IDSEL) with partly swizzled IRQs on slot 16. + * We assume the same IRQ for all pins on the remaining slots, that + * is what the boardfile was doing. + */ + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0xf800 0 0 7>; + interrupt-map =3D + /* IDSEL 14 used for "Wireless" in the board file */ + <0x7000 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq= 7 */ + /* IDSEL 15 used for VIA VT6307 IEEE 1394 Firewire */ + <0x7800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 15 is irq= 8 */ + /* IDSEL 16 used for VIA VT6202 USB 2.0 4+1 */ + <0x8000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 16 is irq= 11 */ + <0x8000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 16 is irq= 10 */ + <0x8000 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT C on slot 16 is irq= 9 */ + }; + + gpio@c8004000 { + /* Enable clock out on GPIO 15 */ + intel,ixp4xx-gpio15-clkout; + }; + + /* EthB WAN */ + ethernet@c8009000 { + status =3D "okay"; + queue-rx =3D <&qmgr 3>; + queue-txready =3D <&qmgr 20>; + phy-mode =3D "rgmii"; + phy-handle =3D <&phy9>; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + phy9: ethernet-phy@9 { + reg =3D <9>; + }; + + /* The switch uses MDIO addresses 16 thru 31 */ + switch@16 { + compatible =3D "marvell,mv88e6060"; + reg =3D <16>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + label =3D "lan1"; + }; + + port@1 { + reg =3D <1>; + label =3D "lan2"; + }; + + port@2 { + reg =3D <2>; + label =3D "lan3"; + }; + + port@3 { + reg =3D <3>; + label =3D "lan4"; + }; + + port@5 { + /* Port 5 is the CPU port according to the MV88E6060 datasheet */ + reg =3D <5>; + phy-mode =3D "rgmii-id"; + ethernet =3D <ðc>; + label =3D "cpu"; + fixed-link { + speed =3D <100>; + full-duplex; + }; + }; + }; + }; + }; + }; + + /* EthC LAN connected to the Marvell DSA Switch */ + ethc: ethernet@c800a000 { + status =3D "okay"; + queue-rx =3D <&qmgr 4>; + queue-txready =3D <&qmgr 21>; + phy-mode =3D "rgmii"; + fixed-link { + speed =3D <100>; + full-duplex; + }; + }; + }; +}; --- base-commit: 0bb80ecc33a8fb5a682236443c1e740d5c917d1d change-id: 20230919-ixp4xx-usr8200-b2408d6fcad5 Best regards, --=20 Linus Walleij