From nobody Sun Dec 14 13:52:33 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6512AE81DED for ; Fri, 6 Oct 2023 12:27:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232282AbjJFM1T (ORCPT ); Fri, 6 Oct 2023 08:27:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53396 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232253AbjJFM1O (ORCPT ); Fri, 6 Oct 2023 08:27:14 -0400 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4B619FF for ; Fri, 6 Oct 2023 05:27:10 -0700 (PDT) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 41D96C433AD; Fri, 6 Oct 2023 12:27:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1696595229; bh=bOf8w7XnCc16OPMA+e95RqpCtIBPs/nM95W8FKx64k0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NP80/FAHyJhx3j01yWIu134p/m29xD1K3Ijk8Or65OIPy+/vZg3qqkLuqI06ZtSa3 siQewwfwxXxIUr7ls+Z3ldqvWMoknqNIx/FWvcKpvh9MhN2eD3khDwWpi1o307/zyk JhQx9m3LJN2HRuxoxQqPyiUCu5UEes+e3K+dMPGxLESsclqnPeKvvPoV5XpZ2RI2Ni Ntw9A7qIFcvlL/0tfQw+3PCQg7eBrYZTnyS/7uUK8vSvP9Ht9t8lsa9GsN0Gyd4TMz 1r2VnN+YKlOIkzQ8MpwyuGpKdzKwWbi7dCPctPJGtcMteKfR7TOvH2FT466OQ3YmZn lr3nvfYLaEPTg== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Inochi Amaoto Subject: [PATCH v2 4/5] riscv: dts: sophgo: add initial CV1800B SoC device tree Date: Fri, 6 Oct 2023 20:14:48 +0800 Message-Id: <20231006121449.721-5-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20231006121449.721-1-jszhang@kernel.org> References: <20231006121449.721-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add initial device tree for the CV1800B RISC-V SoC by SOPHGO. Signed-off-by: Jisheng Zhang Acked-by: Chen Wang --- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 123 ++++++++++++++++++++++++ 1 file changed, 123 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/cv1800b.dtsi diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/= sophgo/cv1800b.dtsi new file mode 100644 index 000000000000..df40e87ee063 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 Jisheng Zhang + */ + +#include + +/ { + compatible =3D "sophgo,cv1800b"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + cpus: cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + timebase-frequency =3D <25000000>; + + cpu0: cpu@0 { + compatible =3D "thead,c906", "riscv"; + device_type =3D "cpu"; + reg =3D <0>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <512>; + d-cache-size =3D <65536>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <128>; + i-cache-size =3D <32768>; + mmu-type =3D "riscv,sv39"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr= ", + "zifencei", "zihpm"; + + cpu0_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + }; + }; + + osc: oscillator { + compatible =3D "fixed-clock"; + clock-output-names =3D "osc_25m"; + #clock-cells =3D <0>; + }; + + soc { + compatible =3D "simple-bus"; + interrupt-parent =3D <&plic>; + #address-cells =3D <1>; + #size-cells =3D <1>; + dma-noncoherent; + ranges; + + uart0: serial@4140000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x04140000 0x100>; + interrupts =3D <44 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&osc>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart1: serial@4150000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x04150000 0x100>; + interrupts =3D <45 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&osc>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart2: serial@4160000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x04160000 0x100>; + interrupts =3D <46 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&osc>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart3: serial@4170000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x04170000 0x100>; + interrupts =3D <47 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&osc>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart4: serial@41c0000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x041c0000 0x100>; + interrupts =3D <48 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&osc>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + plic: interrupt-controller@70000000 { + compatible =3D "sophgo,cv1800b-plic", "thead,c900-plic"; + reg =3D <0x70000000 0x4000000>; + interrupts-extended =3D <&cpu0_intc 11>, <&cpu0_intc 9>; + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <2>; + riscv,ndev =3D <101>; + }; + + clint: timer@74000000 { + compatible =3D "sophgo,cv1800b-clint", "thead,c900-clint"; + reg =3D <0x74000000 0x10000>; + interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>; + }; + }; +}; --=20 2.40.1