From nobody Sun Nov 10 11:16:02 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 260F3E92FF4 for ; Fri, 6 Oct 2023 07:40:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231262AbjJFHkB (ORCPT ); Fri, 6 Oct 2023 03:40:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58670 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230439AbjJFHjA (ORCPT ); Fri, 6 Oct 2023 03:39:00 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C9BBEED; Fri, 6 Oct 2023 00:38:49 -0700 (PDT) X-UUID: 6025e944641b11eea33bb35ae8d461a2-20231006 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=93orfpqZDdf36gAkqWIQODvWhDa0xsK8NTO91hVC3Mg=; b=gBfkQ0vukrIp1fR6jrvJ8S72u3QlBYZPOJeMpVMLpRiRAbgEc+UWMRPZcKQ2fz0qS2UU2RcoQjpqgFeEbFwG+OJB1TW8oUfcDQ9/irgjYLgpS2hSDEoTzg4ckWsQRnphaVirgQhxLVFSjCwY3mPA2fJSrru8pk7JtVuGzP6+Hnc=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:734278b8-25fa-4f96-8bce-d59aa5b8f9a6,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5f78ec9,CLOUDID:036ba6bf-14cc-44ca-b657-2d2783296e72,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 6025e944641b11eea33bb35ae8d461a2-20231006 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 2108080839; Fri, 06 Oct 2023 15:38:43 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS14N2.mediatek.inc (172.21.101.76) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 6 Oct 2023 15:38:40 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 6 Oct 2023 15:38:40 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , "CK Hu" , Krzysztof Kozlowski , Matthias Brugger , Rob Herring CC: Conor Dooley , Philipp Zabel , David Airlie , Daniel Vetter , Chun-Kuang Hu , "Mauro Carvalho Chehab" , , , , , , Singo Chang , "Nancy . Lin" , "Jason-JH . Lin" , "Hsiao Chien Sung" Subject: [PATCH v7 21/23] drm/mediatek: Fix underrun in VDO1 when switches off the layer Date: Fri, 6 Oct 2023 15:38:29 +0800 Message-ID: <20231006073831.10402-22-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231006073831.10402-1-shawn.sung@mediatek.com> References: <20231006073831.10402-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--1.397400-8.000000 X-TMASE-MatchedRID: r15/GZU7YAxQlz7zzALRPqKa0xB73sAA7yWPaQc4INS0rcU5V/oSe8Ht HEmxq9+Y8G/bfvdFXyUnOAFYLaUTjVm72EsAF82QA9lly13c/gGSiza26cvwNH5h6y4KCSJcje0 jgce+svLi8zVgXoAltsYlDcGKIsCCC24oEZ6SpSmb4wHqRpnaDhEa9sDDkr22LbG6i7W98dbd1i 4KTSE2f89R4TWA696sOygFfwAQBHQ1pTQn8aCaylDADnj2lwwmQemDxUAjl6nn/SfPR3Dh3Ema3 zYT97IFAYfQIAUhBayZvmCbKVb49sZL6x5U/HridGByp+zdaDg= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--1.397400-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 873682982834D8809BE0F82F0A91BE21551E3F3F614D78253E6819C916A67B552000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Do not reset Merge while using CMDQ because it doesn't wait for frame done event as CMDQ does and could lead to underrun when the layer is switching off. Fixes: aaf94f7c3ae6 ("drm/mediatek: Add display merge async reset control") Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_merge.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/me= diatek/mtk_disp_merge.c index e525a6b9e5b0..22f768d923d5 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c @@ -103,7 +103,7 @@ void mtk_merge_stop_cmdq(struct device *dev, struct cmd= q_pkt *cmdq_pkt) mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CTRL); =20 - if (priv->async_clk) + if (!cmdq_pkt && priv->async_clk) reset_control_reset(priv->reset_ctl); } =20 --=20 2.18.0