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Lin" , "Jason-JH . Lin" , "Hsiao Chien Sung" Subject: [PATCH v7 15/23] drm/mediatek: Manage component's clock with function pointers Date: Fri, 6 Oct 2023 15:38:23 +0800 Message-ID: <20231006073831.10402-16-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231006073831.10402-1-shawn.sung@mediatek.com> References: <20231006073831.10402-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--3.901800-8.000000 X-TMASE-MatchedRID: uYOEf1I6Oo0b7D0aLEL5Ob2xWbKjBfWPy1y/jIuoZZ4x3z93vsEFGlaP 6AhhdqyDkPk8oBU71Swz42d4hTjtM6h+3Rlbev+JkDpLRKO9xhSZ2scyRQcer19eTSR8I6du4uR 3pP7Rlrc+1MUqk5HN+7u2F2cs3EHUIkzJoP2DD5eeAiCmPx4NwBnUJ0Ek6yhjxEHRux+uk8hxKp vEGAbTDud4SwFYISTISMMJHxYBUh/wFqjjvz1R1GIjnmkTMSStkmemp0mkTw3rTT0Iiifzbmccc uOL7tzOK8TLV5jhmHIRwPjwyc1QjHmVKZusLp922v9OjYWA2uMMswg45VMfPXY3pGDmoik6 X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--3.901800-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 1F53102C682366CFD9DEC59423D77EBD05D637BFB6549CA0DA4562085E9BC4F52000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" By registering component related functions to the pointers, we can easily manage them within a for-loop and simplify the logic of clock control significantly. Reviewed-by: CK Hu Signed-off-by: Hsiao Chien Sung --- .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 111 +++++++----------- 1 file changed, 44 insertions(+), 67 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index 8a52d1301e04..84133303a6ec 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -54,6 +54,7 @@ struct ovl_adaptor_comp_match { enum mtk_ovl_adaptor_comp_type type; enum mtk_ddp_comp_id comp_id; int alias_id; + const struct mtk_ddp_comp_funcs *funcs; }; =20 struct mtk_disp_ovl_adaptor { @@ -68,20 +69,35 @@ static const char * const private_comp_stem[OVL_ADAPTOR= _TYPE_NUM] =3D { [OVL_ADAPTOR_TYPE_MERGE] =3D "merge", }; =20 +static const struct mtk_ddp_comp_funcs _ethdr =3D { + .clk_enable =3D mtk_ethdr_clk_enable, + .clk_disable =3D mtk_ethdr_clk_disable, +}; + +static const struct mtk_ddp_comp_funcs _merge =3D { + .clk_enable =3D mtk_merge_clk_enable, + .clk_disable =3D mtk_merge_clk_disable, +}; + +static const struct mtk_ddp_comp_funcs _rdma =3D { + .clk_enable =3D mtk_mdp_rdma_clk_enable, + .clk_disable =3D mtk_mdp_rdma_clk_disable, +}; + static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX= ] =3D { - [OVL_ADAPTOR_ETHDR0] =3D { OVL_ADAPTOR_TYPE_ETHDR, DDP_COMPONENT_ETHDR_MI= XER, 0 }, - [OVL_ADAPTOR_MDP_RDMA0] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA0, 0 }, - [OVL_ADAPTOR_MDP_RDMA1] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA1, 1 }, - [OVL_ADAPTOR_MDP_RDMA2] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA2, 2 }, - [OVL_ADAPTOR_MDP_RDMA3] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA3, 3 }, - [OVL_ADAPTOR_MDP_RDMA4] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA4, 4 }, - [OVL_ADAPTOR_MDP_RDMA5] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA5, 5 }, - [OVL_ADAPTOR_MDP_RDMA6] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA6, 6 }, - [OVL_ADAPTOR_MDP_RDMA7] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA7, 7 }, - [OVL_ADAPTOR_MERGE0] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, = 1 }, - [OVL_ADAPTOR_MERGE1] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, = 2 }, - [OVL_ADAPTOR_MERGE2] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, = 3 }, - [OVL_ADAPTOR_MERGE3] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, = 4 }, + [OVL_ADAPTOR_ETHDR0] =3D { OVL_ADAPTOR_TYPE_ETHDR, DDP_COMPONENT_ETHDR_MI= XER, 0, &_ethdr }, + [OVL_ADAPTOR_MDP_RDMA0] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA0, 0, &_rdma }, + [OVL_ADAPTOR_MDP_RDMA1] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA1, 1, &_rdma }, + [OVL_ADAPTOR_MDP_RDMA2] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA2, 2, &_rdma }, + [OVL_ADAPTOR_MDP_RDMA3] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA3, 3, &_rdma }, + [OVL_ADAPTOR_MDP_RDMA4] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA4, 4, &_rdma }, + [OVL_ADAPTOR_MDP_RDMA5] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA5, 5, &_rdma }, + [OVL_ADAPTOR_MDP_RDMA6] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA6, 6, &_rdma }, + [OVL_ADAPTOR_MDP_RDMA7] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA7, 7, &_rdma }, + [OVL_ADAPTOR_MERGE0] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, = 1, &_merge }, + [OVL_ADAPTOR_MERGE1] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, = 2, &_merge }, + [OVL_ADAPTOR_MERGE2] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, = 3, &_merge }, + [OVL_ADAPTOR_MERGE3] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, = 4, &_merge }, }; =20 void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx, @@ -187,73 +203,34 @@ void mtk_ovl_adaptor_stop(struct device *dev) =20 int mtk_ovl_adaptor_clk_enable(struct device *dev) { - struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); - struct device *comp; - int ret; int i; - - for (i =3D 0; i < OVL_ADAPTOR_MERGE0; i++) { - comp =3D ovl_adaptor->ovl_adaptor_comp[i]; - ret =3D pm_runtime_get_sync(comp); - if (ret < 0) { - dev_err(dev, "Failed to enable power domain %d, err %d\n", i, ret); - goto pwr_err; - } - } + int ret; + struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); =20 for (i =3D 0; i < OVL_ADAPTOR_ID_MAX; i++) { - comp =3D ovl_adaptor->ovl_adaptor_comp[i]; - - if (i < OVL_ADAPTOR_MERGE0) - ret =3D mtk_mdp_rdma_clk_enable(comp); - else if (i < OVL_ADAPTOR_ETHDR0) - ret =3D mtk_merge_clk_enable(comp); - else - ret =3D mtk_ethdr_clk_enable(comp); + dev =3D ovl_adaptor->ovl_adaptor_comp[i]; + if (!dev) + continue; + ret =3D comp_matches[i].funcs->clk_enable(dev); if (ret) { - dev_err(dev, "Failed to enable clock %d, err %d\n", i, ret); - goto clk_err; + while (--i >=3D 0) + comp_matches[i].funcs->clk_disable(dev); + return ret; } } - - return ret; - -clk_err: - while (--i >=3D 0) { - comp =3D ovl_adaptor->ovl_adaptor_comp[i]; - if (i < OVL_ADAPTOR_MERGE0) - mtk_mdp_rdma_clk_disable(comp); - else if (i < OVL_ADAPTOR_ETHDR0) - mtk_merge_clk_disable(comp); - else - mtk_ethdr_clk_disable(comp); - } - i =3D OVL_ADAPTOR_MERGE0; - -pwr_err: - while (--i >=3D 0) - pm_runtime_put(ovl_adaptor->ovl_adaptor_comp[i]); - - return ret; + return 0; } =20 void mtk_ovl_adaptor_clk_disable(struct device *dev) { - struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); - struct device *comp; int i; + struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); =20 for (i =3D 0; i < OVL_ADAPTOR_ID_MAX; i++) { - comp =3D ovl_adaptor->ovl_adaptor_comp[i]; - - if (i < OVL_ADAPTOR_MERGE0) { - mtk_mdp_rdma_clk_disable(comp); - pm_runtime_put(comp); - } else if (i < OVL_ADAPTOR_ETHDR0) { - mtk_merge_clk_disable(comp); - } else { - mtk_ethdr_clk_disable(comp); - } + dev =3D ovl_adaptor->ovl_adaptor_comp[i]; + if (!dev) + continue; + comp_matches[i].funcs->clk_disable(dev); } } =20 --=20 2.18.0