From nobody Fri Jan 2 22:39:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCE77E9413D for ; Sat, 7 Oct 2023 00:41:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233980AbjJGAlc (ORCPT ); Fri, 6 Oct 2023 20:41:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56810 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233972AbjJGAl1 (ORCPT ); Fri, 6 Oct 2023 20:41:27 -0400 Received: from mail-pf1-x434.google.com (mail-pf1-x434.google.com [IPv6:2607:f8b0:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F3E02BF for ; Fri, 6 Oct 2023 17:41:19 -0700 (PDT) Received: by mail-pf1-x434.google.com with SMTP id d2e1a72fcca58-690bc3f82a7so2392687b3a.0 for ; Fri, 06 Oct 2023 17:41:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1696639279; x=1697244079; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=y5ObyqDOjztoDhC5t8E2lz3oLVXfFznkcrpNtj4QO6o=; b=TRcFK3deXiDmpw8bhKTyyRPn6RMskkTfg9TQzbQI4yeB5lJ504+1dsKR/Yx1+lEzto oiUFuXf82NRasYyZ2PpkrMU4+GpxvCR40bJ1tLxxSRAfgVcxcFcQeUs6c7Tr3nRVNT80 l+WpVwgZ8q10aEpFzK0+WZJiznzJcM5SyQF2Mr8ad/sj4DssP5+iqXxrTu0CaIj0Nkpc JYHfSyprTDKQWlBFVZhZqrdCmQ/xpLP28LpaSayiQCpFkTmuf7rAuyR1kwh7+TOyVQ3x uemiUmDlWAoOu1nYABE4xjAHZ+rC4OxppMcQZpcVG2eJh3uA4xDFUac6Oiw+1I9jIFOx ke7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696639279; x=1697244079; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=y5ObyqDOjztoDhC5t8E2lz3oLVXfFznkcrpNtj4QO6o=; b=Tqq+Pc/RLy8JFCk7uRVGsTKtFLhpdMsrtGh0ui16glt7qP39RgBp/UOweAsLc6NhRe P4wtqYzlbfrzWf7H02pLkP1QIMzbFiBNuqGPCIxok0Gvt5HmAVCHxU5jkpHER1ByBJZx dW3ffqYxzRepU4E9CEOrtzM1b+/vM5eylqRe2sqzlqdiEQHcA0GRTQUAr+LSdxKijNqE +yBwGZiiNfzpkUb4qMHiFlvyeu6GQX3bPjjWz5zbyL/f0UW3HJlP8MwauKkgDeKLO7he gDwXoquNvSq/pus0fuWxryiylume+Fh1mjA9Upr+T13Sa2SxEi5NsqxuQUn/ENsxRgvo G3Xg== X-Gm-Message-State: AOJu0YzJ4eAwx3sj9q/azfp9hcvqEwOoXUdk3nRX8Zd17iisBVC/hYqZ 251NU/3ArgXcBrXhh/q57/iOEA== X-Google-Smtp-Source: AGHT+IHky70QBVvPzgEDItk7mYVORVvgukP/9hhiMTEl2hvCRW/wMJj0Xsi46NbUX0pwqScluqGBnA== X-Received: by 2002:a05:6a20:144c:b0:14e:a1f0:a8ea with SMTP id a12-20020a056a20144c00b0014ea1f0a8eamr9888603pzi.3.1696639279458; Fri, 06 Oct 2023 17:41:19 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id x16-20020a170902ec9000b001c582de968dsm4534540plg.72.2023.10.06.17.41.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Oct 2023 17:41:19 -0700 (PDT) From: Charlie Jenkins Date: Fri, 06 Oct 2023 17:41:06 -0700 Subject: [PATCH v2 1/2] riscv: Add remaining module relocations MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231006-module_relocations-v2-1-47566453fedc@rivosinc.com> References: <20231006-module_relocations-v2-0-47566453fedc@rivosinc.com> In-Reply-To: <20231006-module_relocations-v2-0-47566453fedc@rivosinc.com> To: linux-riscv@lists.infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Cc: Eric Biederman , Kees Cook , Paul Walmsley , Palmer Dabbelt , Albert Ou , Charlie Jenkins X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add all final module relocations and add error logs explaining the ones that are not supported. Signed-off-by: Charlie Jenkins --- arch/riscv/include/uapi/asm/elf.h | 6 +- arch/riscv/kernel/module.c | 247 ++++++++++++++++++++++++++++++++++= ---- 2 files changed, 227 insertions(+), 26 deletions(-) diff --git a/arch/riscv/include/uapi/asm/elf.h b/arch/riscv/include/uapi/as= m/elf.h index d696d6610231..a9307a1c9ceb 100644 --- a/arch/riscv/include/uapi/asm/elf.h +++ b/arch/riscv/include/uapi/asm/elf.h @@ -49,6 +49,7 @@ typedef union __riscv_fp_state elf_fpregset_t; #define R_RISCV_TLS_DTPREL64 9 #define R_RISCV_TLS_TPREL32 10 #define R_RISCV_TLS_TPREL64 11 +#define R_RISCV_IRELATIVE 58 =20 /* Relocation types not used by the dynamic linker */ #define R_RISCV_BRANCH 16 @@ -81,7 +82,7 @@ typedef union __riscv_fp_state elf_fpregset_t; #define R_RISCV_ALIGN 43 #define R_RISCV_RVC_BRANCH 44 #define R_RISCV_RVC_JUMP 45 -#define R_RISCV_LUI 46 +#define R_RISCV_RVC_LUI 46 #define R_RISCV_GPREL_I 47 #define R_RISCV_GPREL_S 48 #define R_RISCV_TPREL_I 49 @@ -93,6 +94,9 @@ typedef union __riscv_fp_state elf_fpregset_t; #define R_RISCV_SET16 55 #define R_RISCV_SET32 56 #define R_RISCV_32_PCREL 57 +#define R_RISCV_PLT32 59 +#define R_RISCV_SET_ULEB128 60 +#define R_RISCV_SUB_ULEB128 61 =20 =20 #endif /* _UAPI_ASM_RISCV_ELF_H */ diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 7c651d55fcbd..61d5cdbe609d 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/module.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -253,6 +254,30 @@ static int apply_r_riscv_call_rela(struct module *me, = u32 *location, return 0; } =20 +static int apply_r_riscv_rvc_lui_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + // Get high 6 bits of 18 bit absolute address + s32 imm =3D ((s32)v + 0x800) >> 12; + + if (v !=3D sign_extend32(v, 6)) { + pr_err("%s: target %016llx can not be addressed by the 6-bit offset from= PC =3D %p\n", + me->name, (long long)v, location); + return -EINVAL; + } + + if (imm =3D=3D 0) { + // imm =3D 0 is invalid for c.lui, convert to c.li + *location =3D (*location & 0x0F83) | 0x4000; + } else { + u16 imm17 =3D ((((s32)v + 0x800) & 0x20000) >> (17 - 12)); + u16 imm16_12 =3D ((((s32)v + 0x800) & 0x1f000) >> (12 - 2)); + *location =3D (*location & 0xef83) | imm17 | imm16_12; + } + + return 0; +} + static int apply_r_riscv_relax_rela(struct module *me, u32 *location, Elf_Addr v) { @@ -268,6 +293,12 @@ static int apply_r_riscv_align_rela(struct module *me,= u32 *location, return -EINVAL; } =20 +static int apply_r_riscv_add8_rela(struct module *me, u32 *location, Elf_A= ddr v) +{ + *(u8 *)location +=3D (u8)v; + return 0; +} + static int apply_r_riscv_add16_rela(struct module *me, u32 *location, Elf_Addr v) { @@ -289,6 +320,12 @@ static int apply_r_riscv_add64_rela(struct module *me,= u32 *location, return 0; } =20 +static int apply_r_riscv_sub8_rela(struct module *me, u32 *location, Elf_A= ddr v) +{ + *(u8 *)location -=3D (u8)v; + return 0; +} + static int apply_r_riscv_sub16_rela(struct module *me, u32 *location, Elf_Addr v) { @@ -310,31 +347,150 @@ static int apply_r_riscv_sub64_rela(struct module *m= e, u32 *location, return 0; } =20 -static int (*reloc_handlers_rela[]) (struct module *me, u32 *location, - Elf_Addr v) =3D { - [R_RISCV_32] =3D apply_r_riscv_32_rela, - [R_RISCV_64] =3D apply_r_riscv_64_rela, - [R_RISCV_BRANCH] =3D apply_r_riscv_branch_rela, - [R_RISCV_JAL] =3D apply_r_riscv_jal_rela, - [R_RISCV_RVC_BRANCH] =3D apply_r_riscv_rvc_branch_rela, - [R_RISCV_RVC_JUMP] =3D apply_r_riscv_rvc_jump_rela, - [R_RISCV_PCREL_HI20] =3D apply_r_riscv_pcrel_hi20_rela, - [R_RISCV_PCREL_LO12_I] =3D apply_r_riscv_pcrel_lo12_i_rela, - [R_RISCV_PCREL_LO12_S] =3D apply_r_riscv_pcrel_lo12_s_rela, - [R_RISCV_HI20] =3D apply_r_riscv_hi20_rela, - [R_RISCV_LO12_I] =3D apply_r_riscv_lo12_i_rela, - [R_RISCV_LO12_S] =3D apply_r_riscv_lo12_s_rela, - [R_RISCV_GOT_HI20] =3D apply_r_riscv_got_hi20_rela, - [R_RISCV_CALL_PLT] =3D apply_r_riscv_call_plt_rela, - [R_RISCV_CALL] =3D apply_r_riscv_call_rela, - [R_RISCV_RELAX] =3D apply_r_riscv_relax_rela, - [R_RISCV_ALIGN] =3D apply_r_riscv_align_rela, - [R_RISCV_ADD16] =3D apply_r_riscv_add16_rela, - [R_RISCV_ADD32] =3D apply_r_riscv_add32_rela, - [R_RISCV_ADD64] =3D apply_r_riscv_add64_rela, - [R_RISCV_SUB16] =3D apply_r_riscv_sub16_rela, - [R_RISCV_SUB32] =3D apply_r_riscv_sub32_rela, - [R_RISCV_SUB64] =3D apply_r_riscv_sub64_rela, +static int dynamic_linking_not_supported(struct module *me, u32 *location, + Elf_Addr v) +{ + pr_err("%s: Dynamic linking not supported in kernel modules PC =3D %p\n", + me->name, location); + return -EINVAL; +} + +static int tls_not_supported(struct module *me, u32 *location, Elf_Addr v) +{ + pr_err("%s: Thread local storage not supported in kernel modules PC =3D %= p\n", + me->name, location); + return -EINVAL; +} + +static int apply_r_riscv_sub6_rela(struct module *me, u32 *location, Elf_A= ddr v) +{ + *(u8 *)location -=3D (u8)v & 0x3F; + return 0; +} + +static int apply_r_riscv_set6_rela(struct module *me, u32 *location, Elf_A= ddr v) +{ + *(u8 *)location =3D (*(u8 *)location & 0xc0) | ((u8)v & 0x3F); + return 0; +} + +static int apply_r_riscv_set8_rela(struct module *me, u32 *location, Elf_A= ddr v) +{ + *(u8 *)location =3D (u8)v; + return 0; +} + +static int apply_r_riscv_set16_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + *(u16 *)location =3D (u16)v; + return 0; +} + +static int apply_r_riscv_set32_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + *(u32 *)location =3D (u32)v; + return 0; +} + +static int apply_r_riscv_32_pcrel_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + *(u32 *)location =3D (u32)v; + return 0; +} + +static int apply_r_riscv_plt32_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + *(u32 *)location =3D (u32)v; + return 0; +} + +static int apply_r_riscv_set_uleb128(struct module *me, u32 *location, Elf= _Addr v) +{ + /* + * Relocation is only performed if R_RISCV_SET_ULEB128 is followed by + * R_RISCV_SUB_ULEB128 so do computation there + */ + return 0; +} + +static int apply_r_riscv_sub_uleb128(struct module *me, u32 *location, Elf= _Addr v) +{ + if (v >=3D 128) { + pr_err("%s: uleb128 must be in [0, 127] (not %ld) at PC =3D %p\n", + me->name, (unsigned long)v, location); + return -EINVAL; + } + + *location =3D v; + return 0; +} + +/* + * Relocations defined in the riscv-elf-psabi-doc. + * This handles static linking only. + */ +static int (*reloc_handlers_rela[])(struct module *me, u32 *location, + Elf_Addr v) =3D { + [R_RISCV_32] =3D apply_r_riscv_32_rela, + [R_RISCV_64] =3D apply_r_riscv_64_rela, + [R_RISCV_RELATIVE] =3D dynamic_linking_not_supported, + [R_RISCV_COPY] =3D dynamic_linking_not_supported, + [R_RISCV_JUMP_SLOT] =3D dynamic_linking_not_supported, + [R_RISCV_TLS_DTPMOD32] =3D dynamic_linking_not_supported, + [R_RISCV_TLS_DTPMOD64] =3D dynamic_linking_not_supported, + [R_RISCV_TLS_DTPREL32] =3D dynamic_linking_not_supported, + [R_RISCV_TLS_DTPREL64] =3D dynamic_linking_not_supported, + [R_RISCV_TLS_TPREL32] =3D dynamic_linking_not_supported, + [R_RISCV_TLS_TPREL64] =3D dynamic_linking_not_supported, + /* 12-15 undefined */ + [R_RISCV_BRANCH] =3D apply_r_riscv_branch_rela, + [R_RISCV_JAL] =3D apply_r_riscv_jal_rela, + [R_RISCV_CALL] =3D apply_r_riscv_call_rela, + [R_RISCV_CALL_PLT] =3D apply_r_riscv_call_plt_rela, + [R_RISCV_GOT_HI20] =3D apply_r_riscv_got_hi20_rela, + [R_RISCV_TLS_GOT_HI20] =3D tls_not_supported, + [R_RISCV_TLS_GD_HI20] =3D tls_not_supported, + [R_RISCV_PCREL_HI20] =3D apply_r_riscv_pcrel_hi20_rela, + [R_RISCV_PCREL_LO12_I] =3D apply_r_riscv_pcrel_lo12_i_rela, + [R_RISCV_PCREL_LO12_S] =3D apply_r_riscv_pcrel_lo12_s_rela, + [R_RISCV_HI20] =3D apply_r_riscv_hi20_rela, + [R_RISCV_LO12_I] =3D apply_r_riscv_lo12_i_rela, + [R_RISCV_LO12_S] =3D apply_r_riscv_lo12_s_rela, + [R_RISCV_TPREL_HI20] =3D tls_not_supported, + [R_RISCV_TPREL_LO12_I] =3D tls_not_supported, + [R_RISCV_TPREL_LO12_S] =3D tls_not_supported, + [R_RISCV_TPREL_ADD] =3D tls_not_supported, + [R_RISCV_ADD8] =3D apply_r_riscv_add8_rela, + [R_RISCV_ADD16] =3D apply_r_riscv_add16_rela, + [R_RISCV_ADD32] =3D apply_r_riscv_add32_rela, + [R_RISCV_ADD64] =3D apply_r_riscv_add64_rela, + [R_RISCV_SUB8] =3D apply_r_riscv_sub8_rela, + [R_RISCV_SUB16] =3D apply_r_riscv_sub16_rela, + [R_RISCV_SUB32] =3D apply_r_riscv_sub32_rela, + [R_RISCV_SUB64] =3D apply_r_riscv_sub64_rela, + /* 41-42 reserved for future standard use */ + [R_RISCV_ALIGN] =3D apply_r_riscv_align_rela, + [R_RISCV_RVC_BRANCH] =3D apply_r_riscv_rvc_branch_rela, + [R_RISCV_RVC_JUMP] =3D apply_r_riscv_rvc_jump_rela, + [R_RISCV_RVC_LUI] =3D apply_r_riscv_rvc_lui_rela, + /* 47-50 reserved for future standard use */ + [R_RISCV_RELAX] =3D apply_r_riscv_relax_rela, + [R_RISCV_SUB6] =3D apply_r_riscv_sub6_rela, + [R_RISCV_SET6] =3D apply_r_riscv_set6_rela, + [R_RISCV_SET8] =3D apply_r_riscv_set8_rela, + [R_RISCV_SET16] =3D apply_r_riscv_set16_rela, + [R_RISCV_SET32] =3D apply_r_riscv_set32_rela, + [R_RISCV_32_PCREL] =3D apply_r_riscv_32_pcrel_rela, + [R_RISCV_IRELATIVE] =3D dynamic_linking_not_supported, + [R_RISCV_PLT32] =3D apply_r_riscv_plt32_rela, + [R_RISCV_SET_ULEB128] =3D apply_r_riscv_set_uleb128, + [R_RISCV_SUB_ULEB128] =3D apply_r_riscv_sub_uleb128, + /* 62-191 reserved for future standard use */ + /* 192-255 nonstandard ABI extensions */ }; =20 int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, @@ -425,6 +581,47 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *= strtab, me->name); return -EINVAL; } + } else if (type =3D=3D R_RISCV_SUB_ULEB128) { + unsigned long set_loc; + u32 set_type; + unsigned long set_sym_val; + + bool has_corresponding_relocation =3D false; + + /* R_RISCV_SET_ULEB128 must appear before the SUB */ + for (unsigned int j =3D i; j >=3D 0; j--) { + set_loc =3D sechdrs[sechdrs[relsec].sh_info] + .sh_addr + + rel[j].r_offset; + set_type =3D ELF_RISCV_R_TYPE(rel[j].r_info); + + /* + * Find the SET relocation that is targeting the + * same position as the SUB + */ + if (set_type =3D=3D R_RISCV_SET_ULEB128 && + set_loc =3D=3D (unsigned long)location) { + Elf_Sym *corresponding_sym =3D + (Elf_Sym *)sechdrs[symindex] + .sh_addr + + ELF_RISCV_R_SYM(rel[j].r_info); + + set_sym_val =3D + corresponding_sym->st_value + + rel[j].r_addend; + has_corresponding_relocation =3D true; + break; + } + } + + if (has_corresponding_relocation) { + /* Calculate set and subtraction */ + v =3D set_sym_val - v; + } else { + pr_err("%s: R_RISCV_SUB_ULEB128 must always be paired with a R_RISCV_S= ET_ULEB128 that comes before it. PC =3D %p\n", + me->name, location); + return -EINVAL; + } } =20 res =3D handler(me, location, v); --=20 2.34.1 From nobody Fri Jan 2 22:39:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2598FE9413E for ; Sat, 7 Oct 2023 00:41:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233983AbjJGAle (ORCPT ); Fri, 6 Oct 2023 20:41:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56812 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233971AbjJGAl1 (ORCPT ); Fri, 6 Oct 2023 20:41:27 -0400 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33127C2 for ; Fri, 6 Oct 2023 17:41:21 -0700 (PDT) Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-1c5bf7871dcso22513065ad.1 for ; Fri, 06 Oct 2023 17:41:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1696639280; x=1697244080; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=quPiij4Hl/2QN709N3Bb2iU2ZbtHkZ/YhK8HJoao894=; b=wBjGtJMS1p6aB8ewvpSLeWtiH4A+j2XjLmvFFQ+zcH4IPIJ9/i4gtBg/PyhCoI8yfI 6AP2JEjNUrkK0tRDigkPjMqWXGyQW7MR6q21a2sW56UAQZbwiI9HNjo+cJ3pAMBgWQCN NFu5JscSQi9AuQo14a2EbsxB7hbsKqJ0buPQ1hpC/meoyAEYWXYcvQAjYjC+8k03IL/f owE/GT0pMPAGRJzTnmDUeuY/H1ucKnfySJrP7tRmSEjjPWE+Nt14xcSD3RPZMvuk482K xl5twldlsNGTcfGKRdHV8OT8tNMRHdDrPsWlIxU1AH2/cDt7663iaUtEQVuA/xYk0Z8g hMFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696639280; x=1697244080; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=quPiij4Hl/2QN709N3Bb2iU2ZbtHkZ/YhK8HJoao894=; b=jdv5IG5yDNwIsEizDSrhbWjs8x7QLjcHPu24ebZXHsFR/B7yozK5TR9Y9z9JT7aqPq 6xzRfFWi3PHSBH6uycwlqmxMjP+4wrFhYs+pN+BdfL35PaoPxR8CcicCc7rmTRfFQHjz VwXUqGEVQjgq/vM2ElpPC+VtKwHYFAv6cFIsoz+OE/2uWCB/mQUiO6VWkJll+IPsaacv p6kU+xWyElh8glC+FuFWPuuTSbuoYiW24VOYpH9t6zWtkNteaJgyQbaYnzYsaCzBUnmA uPciZ26ADZ7W3GV5L97Zi9KqCLeOT8qETVP3Z5OY7MZKxB74iVWhfaqbN63sLeQRwwuL AZYw== X-Gm-Message-State: AOJu0Yyv1Uzge1rfGU7TsXkABDaD0CYo6xAN7xDc3wWyAr+WxGKz7oni N7UivK84cHvyhJ4ajoGu2nHfZg== X-Google-Smtp-Source: AGHT+IEEUABMKZY8ptm1CgPE5q3EicYYQrAkQEiO6mXlX1KJyrzOPhZei1nxELWEjkIlLANGsJfdgA== X-Received: by 2002:a17:902:cecb:b0:1c3:411c:9b7d with SMTP id d11-20020a170902cecb00b001c3411c9b7dmr11238500plg.57.1696639280637; Fri, 06 Oct 2023 17:41:20 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id x16-20020a170902ec9000b001c582de968dsm4534540plg.72.2023.10.06.17.41.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Oct 2023 17:41:20 -0700 (PDT) From: Charlie Jenkins Date: Fri, 06 Oct 2023 17:41:07 -0700 Subject: [PATCH v2 2/2] riscv: Add tests for riscv module loading MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231006-module_relocations-v2-2-47566453fedc@rivosinc.com> References: <20231006-module_relocations-v2-0-47566453fedc@rivosinc.com> In-Reply-To: <20231006-module_relocations-v2-0-47566453fedc@rivosinc.com> To: linux-riscv@lists.infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Cc: Eric Biederman , Kees Cook , Paul Walmsley , Palmer Dabbelt , Albert Ou , Charlie Jenkins X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add test cases for the two main groups of relocations added: SUB and SET, along with uleb128 which is a bit different because SUB and SET are required to happen together. Signed-off-by: Charlie Jenkins --- arch/riscv/Kconfig.debug | 1 + arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/tests/Kconfig.debug | 32 ++++++++++ arch/riscv/kernel/tests/Makefile | 1 + arch/riscv/kernel/tests/module_test/Makefile | 15 +++++ .../tests/module_test/test_module_linking_main.c | 73 ++++++++++++++++++= ++++ arch/riscv/kernel/tests/module_test/test_set16.S | 23 +++++++ arch/riscv/kernel/tests/module_test/test_set32.S | 20 ++++++ arch/riscv/kernel/tests/module_test/test_set6.S | 23 +++++++ arch/riscv/kernel/tests/module_test/test_set8.S | 23 +++++++ arch/riscv/kernel/tests/module_test/test_sub16.S | 22 +++++++ arch/riscv/kernel/tests/module_test/test_sub32.S | 22 +++++++ arch/riscv/kernel/tests/module_test/test_sub6.S | 22 +++++++ arch/riscv/kernel/tests/module_test/test_sub64.S | 27 ++++++++ arch/riscv/kernel/tests/module_test/test_sub8.S | 22 +++++++ arch/riscv/kernel/tests/module_test/test_uleb128.S | 20 ++++++ 16 files changed, 347 insertions(+) diff --git a/arch/riscv/Kconfig.debug b/arch/riscv/Kconfig.debug index e69de29bb2d1..eafe17ebf710 100644 --- a/arch/riscv/Kconfig.debug +++ b/arch/riscv/Kconfig.debug @@ -0,0 +1 @@ +source "arch/riscv/kernel/tests/Kconfig.debug" diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 95cf25d48405..bb99657252f4 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -57,6 +57,7 @@ obj-y +=3D stacktrace.o obj-y +=3D cacheinfo.o obj-y +=3D patch.o obj-y +=3D probes/ +obj-y +=3D tests/ obj-$(CONFIG_MMU) +=3D vdso.o vdso/ =20 obj-$(CONFIG_RISCV_M_MODE) +=3D traps_misaligned.o diff --git a/arch/riscv/kernel/tests/Kconfig.debug b/arch/riscv/kernel/test= s/Kconfig.debug new file mode 100644 index 000000000000..05ca55fb4645 --- /dev/null +++ b/arch/riscv/kernel/tests/Kconfig.debug @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-only +menu "arch/riscv/kernel Testing and Coverage" + +menuconfig RUNTIME_KERNEL_TESTING_MENU + bool "arch/riscv/kernel runtime Testing" + def_bool y + help + Enable riscv kernel runtime testing. + +if RUNTIME_KERNEL_TESTING_MENU + +config RISCV_MODULE_LINKING_KUNIT + bool "KUnit test riscv module linking at runtime" if !KUNIT_ALL_TES= TS + depends on KUNIT + default KUNIT_ALL_TESTS + help + Enable this option to test riscv module linking at boot. This will + enable a module called "test_module_linking". + + KUnit tests run during boot and output the results to the debug l= og + in TAP format (http://testanything.org/). Only useful for kernel = devs + running the KUnit test harness, and not intended for inclusion in= to a + production build. + + For more information on KUnit and unit tests in general please re= fer + to the KUnit documentation in Documentation/dev-tools/kunit/. + + If unsure, say N. + +endif # RUNTIME_TESTING_MENU + +endmenu # "arch/riscv/kernel runtime Testing" diff --git a/arch/riscv/kernel/tests/Makefile b/arch/riscv/kernel/tests/Mak= efile new file mode 100644 index 000000000000..7d6c76cffe20 --- /dev/null +++ b/arch/riscv/kernel/tests/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_RISCV_MODULE_LINKING_KUNIT) +=3D module_test/ diff --git a/arch/riscv/kernel/tests/module_test/Makefile b/arch/riscv/kern= el/tests/module_test/Makefile new file mode 100644 index 000000000000..cacd50cd1127 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/Makefile @@ -0,0 +1,15 @@ +obj-m +=3D test_module_linking.o + +test_sub :=3D test_sub6.o test_sub8.o test_sub16.o test_sub32.o test_sub64= .o + +test_set :=3D test_set6.o test_set8.o test_set16.o test_set32.o + +test_uleb :=3D test_uleb128.o + +test_module_linking-objs +=3D $(test_sub) + +test_module_linking-objs +=3D $(test_set) + +test_module_linking-objs +=3D $(test_uleb) + +test_module_linking-objs +=3D test_module_linking_main.o diff --git a/arch/riscv/kernel/tests/module_test/test_module_linking_main.c= b/arch/riscv/kernel/tests/module_test/test_module_linking_main.c new file mode 100644 index 000000000000..c142c2657d0c --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_module_linking_main.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Rivos Inc. + */ + +#include +#include +#include +#include + +MODULE_LICENSE("GPL"); + +extern int test_set32(void); +extern int test_set16(void); +extern int test_set8(void); +extern int test_set6(void); +extern long test_sub64(void); +extern int test_sub32(void); +extern int test_sub16(void); +extern int test_sub8(void); +extern int test_sub6(void); +extern int test_uleb(void); + +#define CHECK_EQ(lhs, rhs) KUNIT_ASSERT_EQ(test, lhs, rhs) + +void run_test_set(struct kunit *test) +{ + int val32 =3D test_set32(); + int val16 =3D test_set16(); + int val8 =3D test_set8(); + int val6 =3D test_set6(); + + CHECK_EQ(val32, 0); + CHECK_EQ(val16, 0); + CHECK_EQ(val8, 0); + CHECK_EQ(val6, 0); +} + +void run_test_sub(struct kunit *test) +{ + int val64 =3D test_sub64(); + int val32 =3D test_sub32(); + int val16 =3D test_sub16(); + int val8 =3D test_sub8(); + int val6 =3D test_sub6(); + + CHECK_EQ(val64, 0); + CHECK_EQ(val32, 0); + CHECK_EQ(val16, 0); + CHECK_EQ(val8, 0); + CHECK_EQ(val6, 0); +} + +void run_test_uleb(struct kunit *test) +{ + int valuleb =3D test_uleb(); + + CHECK_EQ(valuleb, 0); +} + +static struct kunit_case __refdata riscv_module_linking_test_cases[] =3D { + KUNIT_CASE(run_test_set), + KUNIT_CASE(run_test_sub), + KUNIT_CASE(run_test_uleb), + {} +}; + +static struct kunit_suite riscv_module_linking_test_suite =3D { + .name =3D "riscv_checksum", + .test_cases =3D riscv_module_linking_test_cases, +}; + +kunit_test_suites(&riscv_module_linking_test_suite); diff --git a/arch/riscv/kernel/tests/module_test/test_set16.S b/arch/riscv/= kernel/tests/module_test/test_set16.S new file mode 100644 index 000000000000..2be0e441a12e --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_set16.S @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_set16 +test_set16: + lw a0, set16 + la t0, set16 +#ifdef CONFIG_32BIT + slli t0, t0, 16 + srli t0, t0, 16 +#else + slli t0, t0, 48 + srli t0, t0, 48 +#endif + sub a0, a0, t0 + ret +.data +set16: + .reloc set16, R_RISCV_SET16, set16 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_set32.S b/arch/riscv/= kernel/tests/module_test/test_set32.S new file mode 100644 index 000000000000..de0444537e67 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_set32.S @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_set32 +test_set32: + lw a0, set32 + la t0, set32 +#ifndef CONFIG_32BIT + slli t0, t0, 32 + srli t0, t0, 32 +#endif + sub a0, a0, t0 + ret +.data +set32: + .reloc set32, R_RISCV_SET32, set32 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_set6.S b/arch/riscv/k= ernel/tests/module_test/test_set6.S new file mode 100644 index 000000000000..c39ce4c219eb --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_set6.S @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_set6 +test_set6: + lw a0, set6 + la t0, set6 +#ifdef CONFIG_32BIT + slli t0, t0, 26 + srli t0, t0, 26 +#else + slli t0, t0, 58 + srli t0, t0, 58 +#endif + sub a0, a0, t0 + ret +.data +set6: + .reloc set6, R_RISCV_SET6, set6 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_set8.S b/arch/riscv/k= ernel/tests/module_test/test_set8.S new file mode 100644 index 000000000000..a656173f6f99 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_set8.S @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_set8 +test_set8: + lw a0, set8 + la t0, set8 +#ifdef CONFIG_32BIT + slli t0, t0, 24 + srli t0, t0, 24 +#else + slli t0, t0, 56 + srli t0, t0, 56 +#endif + sub a0, a0, t0 + ret +.data +set8: + .reloc set8, R_RISCV_SET8, set8 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub16.S b/arch/riscv/= kernel/tests/module_test/test_sub16.S new file mode 100644 index 000000000000..c561e155d1db --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub16.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub16 +test_sub16: + lh a0, sub16 + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub16: + .reloc sub16, R_RISCV_ADD16, second + .reloc sub16, R_RISCV_SUB16, first + .half 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub32.S b/arch/riscv/= kernel/tests/module_test/test_sub32.S new file mode 100644 index 000000000000..93232c70cae6 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub32.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub32 +test_sub32: + lw a0, sub32 + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub32: + .reloc sub32, R_RISCV_ADD32, second + .reloc sub32, R_RISCV_SUB32, first + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub6.S b/arch/riscv/k= ernel/tests/module_test/test_sub6.S new file mode 100644 index 000000000000..d9c9526ceb62 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub6.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub6 +test_sub6: + lb a0, sub6 + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub6: + .reloc sub6, R_RISCV_SET6, second + .reloc sub6, R_RISCV_SUB6, first + .byte 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub64.S b/arch/riscv/= kernel/tests/module_test/test_sub64.S new file mode 100644 index 000000000000..6d260e2a5d98 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub64.S @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub64 +test_sub64: +#ifdef CONFIG_32BIT + lw a0, sub64 +#else + ld a0, sub64 +#endif + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub64: + .reloc sub64, R_RISCV_ADD64, second + .reloc sub64, R_RISCV_SUB64, first + .word 0 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub8.S b/arch/riscv/k= ernel/tests/module_test/test_sub8.S new file mode 100644 index 000000000000..af7849115d4d --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub8.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub8 +test_sub8: + lb a0, sub8 + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub8: + .reloc sub8, R_RISCV_ADD8, second + .reloc sub8, R_RISCV_SUB8, first + .byte 0 diff --git a/arch/riscv/kernel/tests/module_test/test_uleb128.S b/arch/risc= v/kernel/tests/module_test/test_uleb128.S new file mode 100644 index 000000000000..db9f301092d0 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_uleb128.S @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_uleb +test_uleb: + ld a0, second + addi a0, a0, -127 + ret +.data +first: + .rept 127 + .byte 0 + .endr +second: + .reloc second, R_RISCV_SET_ULEB128, second + .reloc second, R_RISCV_SUB_ULEB128, first + .dword 0 --=20 2.34.1