From nobody Sat Jan 3 04:09:34 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 297AFE9270D for ; Thu, 5 Oct 2023 16:23:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243423AbjJEQWp (ORCPT ); Thu, 5 Oct 2023 12:22:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34362 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242195AbjJEQRL (ORCPT ); Thu, 5 Oct 2023 12:17:11 -0400 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA2F0671F; Thu, 5 Oct 2023 09:02:51 -0700 (PDT) Received: by mail.gandi.net (Postfix) with ESMTPSA id CAEC51BF207; Thu, 5 Oct 2023 16:02:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1696521760; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=3n0vwmgGryrUp3/6Ss9kZWLenWVOSWlr6mGiYIMJzv4=; b=cIQJVOCq8zk3KpEpI9ixHGbgzBrXaahRbLduqJ7d0ifZOyjKg/ADF/WZL9RVMjVaVJ8aKQ JuMWiK7zv2tDDUrWAh+tCLUwrsx02JWzrxB8/60KNp/AekJ+MCf0frDxKixtu3ZMBXT5uA 4aOjk4P+JbNrdODOkk69mQVgUwih1O5AeUNSLeWTeJICFRx4K8a/CJ6g8rIfgQqfrfqN5a PpgBBHhatPThlOBBykjTlKvof3fg6r9oDS9nHILv9vF4CymNbg8siURefQsPatsljAfMzx hlWxXjurtMZBdQHzKGgGfa4JrdiederJ5X5Vx+XJkfSYfPk2c3/HOyweixJk5Q== From: Miquel Raynal To: Lizhi Hou , Brian Xu , Raj Kumar Rampelli , Vinod Koul , Michal Simek Cc: dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thomas Petazzoni , linux-kernel@vger.kernel.org, Miquel Raynal Subject: [PATCH v3 2/3] dmaengine: xilinx: xdma: Prepare the introduction of cyclic transfers Date: Thu, 5 Oct 2023 18:02:36 +0200 Message-Id: <20231005160237.2804238-3-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231005160237.2804238-1-miquel.raynal@bootlin.com> References: <20231005160237.2804238-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: miquel.raynal@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In order to reduce and clarify the diff when introducing cyclic transfers support, let's first prepare the driver a bit. There is no functional change. Signed-off-by: Miquel Raynal --- drivers/dma/xilinx/xdma.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/dma/xilinx/xdma.c b/drivers/dma/xilinx/xdma.c index e0bfd129d563..09ed13d6666d 100644 --- a/drivers/dma/xilinx/xdma.c +++ b/drivers/dma/xilinx/xdma.c @@ -137,10 +137,10 @@ static inline void *xdma_blk_last_desc(struct xdma_de= sc_block *block) } =20 /** - * xdma_link_desc_blocks - Link descriptor blocks for DMA transfer + * xdma_link_sg_desc_blocks - Link SG descriptor blocks for DMA transfer * @sw_desc: Tx descriptor pointer */ -static void xdma_link_desc_blocks(struct xdma_desc *sw_desc) +static void xdma_link_sg_desc_blocks(struct xdma_desc *sw_desc) { struct xdma_desc_block *block; u32 last_blk_desc, desc_control; @@ -239,6 +239,7 @@ xdma_alloc_desc(struct xdma_chan *chan, u32 desc_num) struct xdma_hw_desc *desc; dma_addr_t dma_addr; u32 dblk_num; + u32 control; void *addr; int i, j; =20 @@ -254,6 +255,8 @@ xdma_alloc_desc(struct xdma_chan *chan, u32 desc_num) if (!sw_desc->desc_blocks) goto failed; =20 + control =3D XDMA_DESC_CONTROL(1, 0); + sw_desc->dblk_num =3D dblk_num; for (i =3D 0; i < sw_desc->dblk_num; i++) { addr =3D dma_pool_alloc(chan->desc_pool, GFP_NOWAIT, &dma_addr); @@ -263,10 +266,10 @@ xdma_alloc_desc(struct xdma_chan *chan, u32 desc_num) sw_desc->desc_blocks[i].virt_addr =3D addr; sw_desc->desc_blocks[i].dma_addr =3D dma_addr; for (j =3D 0, desc =3D addr; j < XDMA_DESC_ADJACENT; j++) - desc[j].control =3D cpu_to_le32(XDMA_DESC_CONTROL(1, 0)); + desc[j].control =3D cpu_to_le32(control); } =20 - xdma_link_desc_blocks(sw_desc); + xdma_link_sg_desc_blocks(sw_desc); =20 return sw_desc; =20 @@ -577,6 +580,12 @@ static int xdma_alloc_chan_resources(struct dma_chan *= chan) return 0; } =20 +static enum dma_status xdma_tx_status(struct dma_chan *chan, dma_cookie_t = cookie, + struct dma_tx_state *state) +{ + return dma_cookie_status(chan, cookie, state); +} + /** * xdma_channel_isr - XDMA channel interrupt handler * @irq: IRQ number @@ -925,7 +934,7 @@ static int xdma_probe(struct platform_device *pdev) xdev->dma_dev.dev =3D &pdev->dev; xdev->dma_dev.device_free_chan_resources =3D xdma_free_chan_resources; xdev->dma_dev.device_alloc_chan_resources =3D xdma_alloc_chan_resources; - xdev->dma_dev.device_tx_status =3D dma_cookie_status; + xdev->dma_dev.device_tx_status =3D xdma_tx_status; xdev->dma_dev.device_prep_slave_sg =3D xdma_prep_device_sg; xdev->dma_dev.device_config =3D xdma_device_config; xdev->dma_dev.device_issue_pending =3D xdma_issue_pending; --=20 2.34.1