From nobody Mon Feb 9 06:15:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6C55E9270D for ; Thu, 5 Oct 2023 15:50:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234544AbjJEPuS (ORCPT ); Thu, 5 Oct 2023 11:50:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234816AbjJEPtQ (ORCPT ); Thu, 5 Oct 2023 11:49:16 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2B44C7EC7; Thu, 5 Oct 2023 08:08:58 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 395DRahZ020813; Thu, 5 Oct 2023 08:27:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1696512456; bh=57mCXwxyotaHUWw5CpiJYMffjaQKYYAlBsulxLdV9xk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=J26fgyARoaXZP8uoeO5UcciIyHvE78oCcBDk0A5u3ESoBFq+bPI0S0WM2llwUKlOa 8LcUibaPzoi38se22Z3HguKEjOTahvMbqlUCsLWsfdyws7L0fi0g6nhKWG0m1Kgmgi oAWZwPnPYD+U69MWJsXDCc6uPQVD8I+K08FPBxrQ= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 395DRa8i050431 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 5 Oct 2023 08:27:36 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 5 Oct 2023 08:27:35 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 5 Oct 2023 08:27:35 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 395DRYTb126658; Thu, 5 Oct 2023 08:27:35 -0500 From: Jayesh Choudhary To: , , CC: , , , , , , , , , , , , Subject: [PATCH RESEND v11 1/5] arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane mux Date: Thu, 5 Oct 2023 18:57:28 +0530 Message-ID: <20231005132732.7462-2-j-choudhary@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231005132732.7462-1-j-choudhary@ti.com> References: <20231005132732.7462-1-j-choudhary@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Siddharth Vadapalli The system controller node manages the CTRL_MMR0 region. Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux. Signed-off-by: Siddharth Vadapalli [j-choudhary@ti.com: Fix serdes_ln_ctrl node] Signed-off-by: Jayesh Choudhary Reviewed-by: Roger Quadros --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index efed2d683f63..6d9a5a91fa75 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -5,6 +5,10 @@ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ */ =20 +#include + +#include "k3-serdes.h" + &cbass_main { msmc_ram: sram@70000000 { compatible =3D "mmio-sram"; @@ -26,6 +30,42 @@ l3cache-sram@200000 { }; }; =20 + scm_conf: bus@100000 { + compatible =3D "simple-bus"; + reg =3D <0x00 0x00100000 0x00 0x1c000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x00 0x00 0x00100000 0x1c000>; + + serdes_ln_ctrl: mux-controller@4080 { + compatible =3D "reg-mux"; + reg =3D <0x00004080 0x30>; + #mux-control-cells =3D <1>; + mux-reg-masks =3D <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select= */ + <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */ + <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ + <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */ + <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ + <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */ + idle-states =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + gic500: interrupt-controller@1800000 { compatible =3D "arm,gic-v3"; #address-cells =3D <2>; --=20 2.25.1 From nobody Mon Feb 9 06:15:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65ED4E9270B for ; Thu, 5 Oct 2023 14:46:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238539AbjJEOqV (ORCPT ); Thu, 5 Oct 2023 10:46:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40484 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239090AbjJEOlo (ORCPT ); Thu, 5 Oct 2023 10:41:44 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 904EA8C3B; Thu, 5 Oct 2023 07:16:45 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 395DRcLd128407; Thu, 5 Oct 2023 08:27:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1696512458; bh=aMcgT+/jEqZjTcEjco4EEuJezT33xU/i3vUk/EjdT2o=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=aWRC3oaOBuSo3wXrhTVEdhmRx3hC79CetR7zE6RFRh+xBTPj0Q95wGCJIOgg32GYD RCD1mBCfNQNVxnvdEY4Bb4DM5R9/v+/CuB7HNxxXO8qPzC/y0QscYvp8GXxPRQoWyp tEfaPHA91+QJUtz4DB97VAmb6MbgActocosExTzM= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 395DRcEA025061 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 5 Oct 2023 08:27:38 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 5 Oct 2023 08:27:37 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 5 Oct 2023 08:27:37 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 395DRaZN126675; Thu, 5 Oct 2023 08:27:37 -0500 From: Jayesh Choudhary To: , , CC: , , , , , , , , , , , , Subject: [PATCH RESEND v11 2/5] arm64: dts: ti: k3-j784s4-main: Add WIZ and SERDES PHY nodes Date: Thu, 5 Oct 2023 18:57:29 +0530 Message-ID: <20231005132732.7462-3-j-choudhary@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231005132732.7462-1-j-choudhary@ti.com> References: <20231005132732.7462-1-j-choudhary@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Siddharth Vadapalli J784S4 SoC has 4 Serdes instances along with their respective WIZ instances. Add device-tree nodes for them and disable them by default as the node is incomplete and phy link properties will be added in the platform dt file. Signed-off-by: Siddharth Vadapalli [j-choudhary@ti.com: fix serdes_wiz clock order & disable serdes refclk] Signed-off-by: Jayesh Choudhary Reviewed-by: Roger Quadros --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 165 +++++++++++++++++++++ 1 file changed, 165 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index 6d9a5a91fa75..e20e26b76ffd 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -6,9 +6,20 @@ */ =20 #include +#include +#include =20 #include "k3-serdes.h" =20 +/ { + serdes_refclk: clock-serdes { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + /* To be enabled when serdes_wiz* is functional */ + status =3D "disabled"; + }; +}; + &cbass_main { msmc_ram: sram@70000000 { compatible =3D "mmio-sram"; @@ -709,6 +720,160 @@ main_sdhci1: mmc@4fb0000 { status =3D "disabled"; }; =20 + serdes_wiz0: wiz@5060000 { + compatible =3D "ti,j784s4-wiz-10g"; + #address-cells =3D <1>; + #size-cells =3D <1>; + power-domains =3D <&k3_pds 404 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 404 2>, <&k3_clks 404 6>, <&serdes_refclk>, <&k3_cl= ks 404 5>; + clock-names =3D "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; + assigned-clocks =3D <&k3_clks 404 6>; + assigned-clock-parents =3D <&k3_clks 404 10>; + num-lanes =3D <4>; + #reset-cells =3D <1>; + #clock-cells =3D <1>; + ranges =3D <0x5060000 0x00 0x5060000 0x10000>; + status =3D "disabled"; + + serdes0: serdes@5060000 { + compatible =3D "ti,j721e-serdes-10g"; + reg =3D <0x05060000 0x010000>; + reg-names =3D "torrent_phy"; + resets =3D <&serdes_wiz0 0>; + reset-names =3D "torrent_reset"; + clocks =3D <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; + clock-names =3D "refclk", "phy_en_refclk"; + assigned-clocks =3D <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents =3D <&k3_clks 404 6>, + <&k3_clks 404 6>, + <&k3_clks 404 6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #clock-cells =3D <1>; + status =3D "disabled"; + }; + }; + + serdes_wiz1: wiz@5070000 { + compatible =3D "ti,j784s4-wiz-10g"; + #address-cells =3D <1>; + #size-cells =3D <1>; + power-domains =3D <&k3_pds 405 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 405 2>, <&k3_clks 405 6>, <&serdes_refclk>, <&k3_cl= ks 405 5>; + clock-names =3D "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; + assigned-clocks =3D <&k3_clks 405 6>; + assigned-clock-parents =3D <&k3_clks 405 10>; + num-lanes =3D <4>; + #reset-cells =3D <1>; + #clock-cells =3D <1>; + ranges =3D <0x05070000 0x00 0x05070000 0x10000>; + status =3D "disabled"; + + serdes1: serdes@5070000 { + compatible =3D "ti,j721e-serdes-10g"; + reg =3D <0x05070000 0x010000>; + reg-names =3D "torrent_phy"; + resets =3D <&serdes_wiz1 0>; + reset-names =3D "torrent_reset"; + clocks =3D <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>; + clock-names =3D "refclk", "phy_en_refclk"; + assigned-clocks =3D <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz1 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents =3D <&k3_clks 405 6>, + <&k3_clks 405 6>, + <&k3_clks 405 6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #clock-cells =3D <1>; + status =3D "disabled"; + }; + }; + + serdes_wiz2: wiz@5020000 { + compatible =3D "ti,j784s4-wiz-10g"; + #address-cells =3D <1>; + #size-cells =3D <1>; + power-domains =3D <&k3_pds 406 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 406 2>, <&k3_clks 406 6>, <&serdes_refclk>, <&k3_cl= ks 406 5>; + clock-names =3D "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; + assigned-clocks =3D <&k3_clks 406 6>; + assigned-clock-parents =3D <&k3_clks 406 10>; + num-lanes =3D <4>; + #reset-cells =3D <1>; + #clock-cells =3D <1>; + ranges =3D <0x05020000 0x00 0x05020000 0x10000>; + status =3D "disabled"; + + serdes2: serdes@5020000 { + compatible =3D "ti,j721e-serdes-10g"; + reg =3D <0x05020000 0x010000>; + reg-names =3D "torrent_phy"; + resets =3D <&serdes_wiz2 0>; + reset-names =3D "torrent_reset"; + clocks =3D <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz2 TI_WIZ_PHY_EN_REFCLK>; + clock-names =3D "refclk", "phy_en_refclk"; + assigned-clocks =3D <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz2 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents =3D <&k3_clks 406 6>, + <&k3_clks 406 6>, + <&k3_clks 406 6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #clock-cells =3D <1>; + status =3D "disabled"; + }; + }; + + serdes_wiz4: wiz@5050000 { + compatible =3D "ti,j784s4-wiz-10g"; + #address-cells =3D <1>; + #size-cells =3D <1>; + power-domains =3D <&k3_pds 407 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 407 2>, <&k3_clks 407 6>, <&serdes_refclk>, <&k3_cl= ks 407 5>; + clock-names =3D "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; + assigned-clocks =3D <&k3_clks 407 6>; + assigned-clock-parents =3D <&k3_clks 407 10>; + num-lanes =3D <4>; + #reset-cells =3D <1>; + #clock-cells =3D <1>; + ranges =3D <0x05050000 0x00 0x05050000 0x10000>, + <0xa030a00 0x00 0xa030a00 0x40>; /* DPTX PHY */ + status =3D "disabled"; + + serdes4: serdes@5050000 { + /* + * Note: we also map DPTX PHY registers as the Torrent + * needs to manage those. + */ + compatible =3D "ti,j721e-serdes-10g"; + reg =3D <0x05050000 0x010000>, + <0x0a030a00 0x40>; /* DPTX PHY */ + reg-names =3D "torrent_phy"; + resets =3D <&serdes_wiz4 0>; + reset-names =3D "torrent_reset"; + clocks =3D <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz4 TI_WIZ_PHY_EN_REFCLK>; + clock-names =3D "refclk", "phy_en_refclk"; + assigned-clocks =3D <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz4 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents =3D <&k3_clks 407 6>, + <&k3_clks 407 6>, + <&k3_clks 407 6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #clock-cells =3D <1>; + status =3D "disabled"; + }; + }; + main_navss: bus@30000000 { bootph-all; compatible =3D "simple-bus"; --=20 2.25.1 From nobody Mon Feb 9 06:15:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36C02E92705 for ; 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Thu, 5 Oct 2023 08:27:39 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 5 Oct 2023 08:27:39 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 5 Oct 2023 08:27:39 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 395DRceG126693; Thu, 5 Oct 2023 08:27:39 -0500 From: Jayesh Choudhary To: , , CC: , , , , , , , , , , , , Subject: [PATCH RESEND v11 3/5] arm64: dts: ti: k3-j784s4-main: Add DSS and DP-bridge node Date: Thu, 5 Oct 2023 18:57:30 +0530 Message-ID: <20231005132732.7462-4-j-choudhary@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231005132732.7462-1-j-choudhary@ti.com> References: <20231005132732.7462-1-j-choudhary@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Rahul T R Add DSS and DP-bridge node for J784S4 SoC. DSS IP in J784S4 is same as DSS IP in J721E, so same compatible is being used. The DP is Cadence MHDP8546. Disable them by default as nodes are missing port definition and phy link configurations which are added later in platform dt file. Signed-off-by: Rahul T R [j-choudhary@ti.com: move dss & mhdp node together in main, fix dss node] Signed-off-by: Jayesh Choudhary Reviewed-by: Aradhya Bhatia Reviewed-by: Roger Quadros --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 71 ++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index e20e26b76ffd..59451b8f063c 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -1773,4 +1773,75 @@ c71_3: dsp@67800000 { firmware-name =3D "j784s4-c71_3-fw"; status =3D "disabled"; }; + + mhdp: bridge@a000000 { + compatible =3D "ti,j721e-mhdp8546"; + reg =3D <0x0 0xa000000 0x0 0x30a00>, + <0x0 0x4f40000 0x0 0x20>; + reg-names =3D "mhdptx", "j721e-intg"; + clocks =3D <&k3_clks 217 11>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + power-domains =3D <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + + dp0_ports: ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + /* Remote-endpoints are on the boards so + * ports are defined in the platform dt file. + */ + }; + }; + + dss: dss@4a00000 { + compatible =3D "ti,j721e-dss"; + reg =3D <0x00 0x04a00000 0x00 0x10000>, /* common_m */ + <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ + <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ + <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ + <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ + <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ + <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ + <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ + <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ + <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ + <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ + <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ + <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ + <0x00 0x04aa0000 0x00 0x10000>, /* vp1 */ + <0x00 0x04ac0000 0x00 0x10000>, /* vp1 */ + <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ + <0x00 0x04af0000 0x00 0x10000>; /* wb */ + reg-names =3D "common_m", "common_s0", + "common_s1", "common_s2", + "vidl1", "vidl2","vid1","vid2", + "ovr1", "ovr2", "ovr3", "ovr4", + "vp1", "vp2", "vp3", "vp4", + "wb"; + clocks =3D <&k3_clks 218 0>, + <&k3_clks 218 2>, + <&k3_clks 218 5>, + <&k3_clks 218 14>, + <&k3_clks 218 18>; + clock-names =3D "fck", "vp1", "vp2", "vp3", "vp4"; + power-domains =3D <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>; + interrupts =3D , + , + , + ; + interrupt-names =3D "common_m", + "common_s0", + "common_s1", + "common_s2"; + status =3D "disabled"; + + dss_ports: ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + /* Ports that DSS drives are platform specific + * so they are defined in platform dt file. + */ + }; + }; }; --=20 2.25.1 From nobody Mon Feb 9 06:15:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F2B5E9270A for ; Thu, 5 Oct 2023 14:46:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237723AbjJEOqL (ORCPT ); Thu, 5 Oct 2023 10:46:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33410 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238995AbjJEOlb (ORCPT ); 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charset="utf-8" From: Rahul T R Enable display for J784S4 EVM. Add assigned clocks for DSS, DT node for DisplayPort PHY and pinmux for DP HPD. Add the clock frequency for serdes_refclk. Add the endpoint nodes to describe connection from: DSS =3D> MHDP =3D> DisplayPort connector. Also add the GPIO expander-4 node and pinmux for main_i2c4 which is required for controlling DP power. Set status for all required nodes for DP-0 as "okay". Signed-off-by: Rahul T R [j-choudhary@ti.com: move all the changes together to enable DP-0 in EVM] Signed-off-by: Jayesh Choudhary Reviewed-by: Aradhya Bhatia Reviewed-by: Roger Quadros --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 119 +++++++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts= /ti/k3-j784s4-evm.dts index 5991c2e1d994..6f46a1ab179e 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -249,6 +249,28 @@ vdd_sd_dv: regulator-TLV71033 { states =3D <1800000 0x0>, <3300000 0x1>; }; + + dp0_pwr_3v3: regulator-dp0-prw { + compatible =3D "regulator-fixed"; + regulator-name =3D "dp0-pwr"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&exp4 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + dp0: connector-dp0 { + compatible =3D "dp-connector"; + label =3D "DP0"; + type =3D "full-size"; + dp-pwr-supply =3D <&dp0_pwr_3v3>; + + port { + dp0_connector_in: endpoint { + remote-endpoint =3D <&dp0_out>; + }; + }; + }; }; =20 &main_pmx0 { @@ -289,6 +311,19 @@ vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ >; }; + + dp0_pins_default: dp0-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x0cc, PIN_INPUT, 12) /* (AM37) SPI0_CS0.DP0_HPD */ + >; + }; + + main_i2c4_pins_default: main-i2c4-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AG33) MCAN14_TX.I2C4_SCL */ + J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */ + >; + }; }; =20 &wkup_pmx2 { @@ -862,3 +897,87 @@ adc { ti,adc-channels =3D <0 1 2 3 4 5 6 7>; }; }; + +&serdes_refclk { + status =3D "okay"; + clock-frequency =3D <100000000>; +}; + +&dss { + status =3D "okay"; + assigned-clocks =3D <&k3_clks 218 2>, + <&k3_clks 218 5>, + <&k3_clks 218 14>, + <&k3_clks 218 18>; + assigned-clock-parents =3D <&k3_clks 218 3>, + <&k3_clks 218 7>, + <&k3_clks 218 16>, + <&k3_clks 218 22>; +}; + +&serdes_wiz4 { + status =3D "okay"; +}; + +&serdes4 { + status =3D "okay"; + serdes4_dp_link: phy@0 { + reg =3D <0>; + cdns,num-lanes =3D <4>; + #phy-cells =3D <0>; + cdns,phy-type =3D ; + resets =3D <&serdes_wiz4 1>, <&serdes_wiz4 2>, + <&serdes_wiz4 3>, <&serdes_wiz4 4>; + }; +}; + +&mhdp { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&dp0_pins_default>; + phys =3D <&serdes4_dp_link>; + phy-names =3D "dpphy"; +}; + +&dss_ports { + /* DP */ + port@0 { + reg =3D <0>; + + dpi0_out: endpoint { + remote-endpoint =3D <&dp0_in>; + }; + }; +}; + +&main_i2c4 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c4_pins_default>; + clock-frequency =3D <400000>; + + exp4: gpio@20 { + compatible =3D "ti,tca6408"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + }; +}; + +&dp0_ports { + port@0 { + reg =3D <0>; + + dp0_in: endpoint { + remote-endpoint =3D <&dpi0_out>; + }; + }; + + port@4 { + reg =3D <4>; + + dp0_out: endpoint { + remote-endpoint =3D <&dp0_connector_in>; + }; + }; +}; --=20 2.25.1 From nobody Mon Feb 9 06:15:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4EF74E9270C for ; Thu, 5 Oct 2023 14:46:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238309AbjJEOqT (ORCPT ); Thu, 5 Oct 2023 10:46:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40488 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239099AbjJEOlo (ORCPT ); Thu, 5 Oct 2023 10:41:44 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 14E6724E89; Thu, 5 Oct 2023 07:16:53 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 395DRhb9128496; Thu, 5 Oct 2023 08:27:43 -0500 DKIM-Signature: v=1; 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Thu, 5 Oct 2023 08:27:43 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 395DRgbR057507; Thu, 5 Oct 2023 08:27:42 -0500 From: Jayesh Choudhary To: , , CC: , , , , , , , , , , , , Subject: [PATCH RESEND v11 5/5] arm64: dts: ti: k3-am69-sk: Add DP and HDMI support Date: Thu, 5 Oct 2023 18:57:32 +0530 Message-ID: <20231005132732.7462-6-j-choudhary@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231005132732.7462-1-j-choudhary@ti.com> References: <20231005132732.7462-1-j-choudhary@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Dasnavis Sabiya AM69 starter kit features an HDMI port and an eDP port. Add assigned clocks for DSS, DT node for DisplayPort PHY, pinmux for HDMI hotplug and power down, mcu_i2c1 and dss_vout for HDMI. Also enable Serdes4 settings for DP display. Add the endpoint nodes to describe connection from: DSS =3D> MHDP =3D> DisplayPort connector DSS =3D> TI TFP410 DPI-to-DVI Bridge =3D> HDMI connector Signed-off-by: Dasnavis Sabiya [j-choudhary@ti.com: Fix dvi-bridge, dss, mhdp and serdes-refclk] Signed-off-by: Jayesh Choudhary Reviewed-by: Aradhya Bhatia Reviewed-by: Roger Quadros --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 229 ++++++++++++++++++++++++++ 1 file changed, 229 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti= /k3-am69-sk.dts index bc1d21ff6d03..3dc98926f2e0 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -251,6 +251,76 @@ vdd_sd_dv: regulator-tlv71033 { states =3D <1800000 0x0>, <3300000 0x1>; }; + + dp0_pwr_3v3: regulator-dp0-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "dp0-pwr"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&dp_pwr_en_pins_default>; + gpio =3D <&main_gpio0 4 0>; /* DP0_3V3 _EN */ + enable-active-high; + }; + + dp0: connector-dp0 { + compatible =3D "dp-connector"; + label =3D "DP0"; + type =3D "full-size"; + dp-pwr-supply =3D <&dp0_pwr_3v3>; + + port { + dp0_connector_in: endpoint { + remote-endpoint =3D <&dp0_out>; + }; + }; + }; + + connector-hdmi { + compatible =3D "hdmi-connector"; + label =3D "hdmi"; + type =3D "a"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hdmi_hpd_pins_default>; + ddc-i2c-bus =3D <&mcu_i2c1>; + hpd-gpios =3D <&main_gpio0 0 GPIO_ACTIVE_HIGH>; /* HDMI_HPD */ + + port { + hdmi_connector_in: endpoint { + remote-endpoint =3D <&tfp410_out>; + }; + }; + }; + + bridge-dvi { + compatible =3D "ti,tfp410"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hdmi_pdn_pins_default>; + powerdown-gpios =3D <&wkup_gpio0 14 GPIO_ACTIVE_LOW>; /* HDMI_PDn */ + ti,deskew =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + tfp410_in: endpoint { + remote-endpoint =3D <&dpi1_out0>; + pclk-sample =3D <1>; + }; + }; + + port@1 { + reg =3D <1>; + + tfp410_out: endpoint { + remote-endpoint =3D <&hdmi_connector_in>; + }; + }; + }; + }; }; =20 &main_pmx0 { @@ -308,6 +378,57 @@ J784S4_IOPAD(0x008, PIN_INPUT, 7) /* (AJ33) MCAN12_RX.= GPIO0_2 */ J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */ >; }; + + dp0_pins_default: dp0-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x014, PIN_INPUT, 13) /* (AG33) MCAN14_TX.DP0_HPD */ + >; + }; + + dp_pwr_en_pins_default: dp-pwr-en-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x010, PIN_INPUT, 7) /* (AH33) MCAN13_RX.GPIO0_4 */ + >; + }; + + dss_vout0_pins_default: dss-vout0-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x074, PIN_OUTPUT, 2) /* (AC33) MCAN2_TX.VOUT0_DATA0 */ + J784S4_IOPAD(0x070, PIN_OUTPUT, 2) /* (AH38) MCAN1_RX.VOUT0_DATA1 */ + J784S4_IOPAD(0x07c, PIN_OUTPUT, 2) /* (AJ38) MCASP0_AXR3.VOUT0_DATA2 */ + J784S4_IOPAD(0x068, PIN_OUTPUT, 2) /* (AE38) MCAN0_RX.VOUT0_DATA3 */ + J784S4_IOPAD(0x064, PIN_OUTPUT, 2) /* (AF38) MCAN0_TX.VOUT0_DATA4 */ + J784S4_IOPAD(0x060, PIN_OUTPUT, 2) /* (AE36) MCASP2_AXR1.VOUT0_DATA5 */ + J784S4_IOPAD(0x05c, PIN_OUTPUT, 2) /* (AC36) MCASP2_AXR0.VOUT0_DATA6 */ + J784S4_IOPAD(0x058, PIN_OUTPUT, 2) /* (AE37) MCASP2_AFSX.VOUT0_DATA7 */ + J784S4_IOPAD(0x054, PIN_OUTPUT, 2) /* (AD37) MCASP2_ACLKX.VOUT0_DATA8 */ + J784S4_IOPAD(0x050, PIN_OUTPUT, 2) /* (AC37) MCASP1_AXR2.VOUT0_DATA9 */ + J784S4_IOPAD(0x04c, PIN_OUTPUT, 2) /* (AC32) MCASP1_AXR1.VOUT0_DATA10 */ + J784S4_IOPAD(0x048, PIN_OUTPUT, 2) /* (AK33) MCASP0_AXR2.VOUT0_DATA11 */ + J784S4_IOPAD(0x044, PIN_OUTPUT, 2) /* (AG37) MCASP0_AXR1.VOUT0_DATA12 */ + J784S4_IOPAD(0x040, PIN_OUTPUT, 2) /* (AF37) MCASP0_AXR0.VOUT0_DATA13 */ + J784S4_IOPAD(0x03c, PIN_OUTPUT, 2) /* (AK38) MCASP0_AFSX.VOUT0_DATA14 */ + J784S4_IOPAD(0x038, PIN_OUTPUT, 2) /* (AK35) MCASP0_ACLKX.VOUT0_DATA15 = */ + J784S4_IOPAD(0x0c8, PIN_OUTPUT, 2) /* (AJ32) EXT_REFCLK1.VOUT0_DATA16 */ + J784S4_IOPAD(0x030, PIN_OUTPUT, 2) /* (AK37) GPIO0_12.VOUT0_DATA17 */ + J784S4_IOPAD(0x02c, PIN_OUTPUT, 2) /* (AL32) GPIO0_11.VOUT0_DATA18 */ + J784S4_IOPAD(0x028, PIN_OUTPUT, 2) /* (AE33) MCAN16_RX.VOUT0_DATA19 */ + J784S4_IOPAD(0x024, PIN_OUTPUT, 2) /* (AH34) MCAN16_TX.VOUT0_DATA20 */ + J784S4_IOPAD(0x020, PIN_OUTPUT, 2) /* (AJ35) MCAN15_RX.VOUT0_DATA21 */ + J784S4_IOPAD(0x01c, PIN_OUTPUT, 2) /* (AG34) MCAN15_TX.VOUT0_DATA22 */ + J784S4_IOPAD(0x018, PIN_OUTPUT, 2) /* (AK36) MCAN14_RX.VOUT0_DATA23 */ + J784S4_IOPAD(0x084, PIN_OUTPUT, 2) /* (AG38) MCASP0_AXR5.VOUT0_DE */ + J784S4_IOPAD(0x080, PIN_OUTPUT, 2) /* (AK34) MCASP0_AXR4.VOUT0_HSYNC */ + J784S4_IOPAD(0x078, PIN_OUTPUT, 2) /* (AH37) MCAN2_RX.VOUT0_PCLK */ + J784S4_IOPAD(0x088, PIN_OUTPUT, 2) /* (AF36) MCASP0_AXR6.VOUT0_VSYNC */ + >; + }; + + hdmi_hpd_pins_default: hdmi-hpd-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x000, PIN_INPUT, 7) /* (AN35) EXTINTN.GPIO0_0 */ + >; + }; }; =20 &wkup_pmx2 { @@ -382,6 +503,21 @@ J784S4_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (J36) WKUP_G= PIO0_3 */ J784S4_WKUP_IOPAD(0x11c, PIN_INPUT, 7) /* (M34) WKUP_GPIO0_67 */ >; }; + + mcu_i2c1_pins_default: mcu-i2c1-default-pins { + pinctrl-single,pins =3D < + /* (L35) WKUP_GPIO0_8.MCU_I2C1_SCL */ + J784S4_WKUP_IOPAD(0x078, PIN_INPUT_PULLUP, 0) + /* (L34) WKUP_GPIO0_9.MCU_I2C1_SDA */ + J784S4_WKUP_IOPAD(0x07c, PIN_INPUT_PULLUP, 0) + >; + }; + + hdmi_pdn_pins_default: hdmi-pdn-default-pins { + pinctrl-single,pins =3D < + J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 7) /* (H37) WKUP_GPIO0_14 */ + >; + }; }; =20 &wkup_pmx3 { @@ -666,3 +802,96 @@ &c71_3 { memory-region =3D <&c71_3_dma_memory_region>, <&c71_3_memory_region>; }; + +&wkup_gpio_intr { + status =3D "okay"; +}; + +&mcu_i2c1 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_i2c1_pins_default>; + clock-frequency =3D <100000>; +}; + +&serdes_refclk { + status =3D "okay"; + clock-frequency =3D <100000000>; +}; + +&dss { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&dss_vout0_pins_default>; + assigned-clocks =3D <&k3_clks 218 2>, + <&k3_clks 218 5>, + <&k3_clks 218 14>, + <&k3_clks 218 18>; + assigned-clock-parents =3D <&k3_clks 218 3>, + <&k3_clks 218 7>, + <&k3_clks 218 16>, + <&k3_clks 218 22>; +}; + +&serdes_wiz4 { + status =3D "okay"; +}; + +&serdes4 { + status =3D "okay"; + serdes4_dp_link: phy@0 { + reg =3D <0>; + cdns,num-lanes =3D <4>; + #phy-cells =3D <0>; + cdns,phy-type =3D ; + resets =3D <&serdes_wiz4 1>, <&serdes_wiz4 2>, + <&serdes_wiz4 3>, <&serdes_wiz4 4>; + }; +}; + +&mhdp { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&dp0_pins_default>; + phys =3D <&serdes4_dp_link>; + phy-names =3D "dpphy"; +}; + +&dss_ports { + /* DP */ + port@0 { + reg =3D <0>; + + dpi0_out: endpoint { + remote-endpoint =3D <&dp0_in>; + }; + }; + + /* HDMI */ + port@1 { + reg =3D <1>; + + dpi1_out0: endpoint { + remote-endpoint =3D <&tfp410_in>; + }; + }; +}; + +&dp0_ports { + + port@0 { + reg =3D <0>; + + dp0_in: endpoint { + remote-endpoint =3D <&dpi0_out>; + }; + }; + + port@4 { + reg =3D <4>; + + dp0_out: endpoint { + remote-endpoint =3D <&dp0_connector_in>; + }; + }; +}; --=20 2.25.1