From nobody Wed Dec 17 02:56:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1441E92721 for ; Thu, 5 Oct 2023 15:51:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235389AbjJEPvx (ORCPT ); Thu, 5 Oct 2023 11:51:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43554 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233541AbjJEPuz (ORCPT ); Thu, 5 Oct 2023 11:50:55 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 25ABB63EED; Thu, 5 Oct 2023 07:08:38 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 395AEkpg100679; Thu, 5 Oct 2023 05:14:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1696500886; bh=aMcgT+/jEqZjTcEjco4EEuJezT33xU/i3vUk/EjdT2o=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=nEM09fOM/kV3bI0mUOKgLeTclwUrDEqlBkJ+ztFx59OCwmhdnyl9bIwDmi4/KyrVc gSwfMdrDCd1PiC8zmc+MelELnNbEw4GwDd/JoK5yaloYxAwJPW9tQTkqWExq3Hd862 ALEKW5Zr2xjauBLExX3tl96fjk5q8AXVqUjkvNfw= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 395AEkUX028630 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 5 Oct 2023 05:14:46 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 5 Oct 2023 05:14:45 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 5 Oct 2023 05:14:45 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 395AEikk018838; Thu, 5 Oct 2023 05:14:45 -0500 From: Jayesh Choudhary To: , , CC: , , , , , , , , , , , , Subject: [PATCH v11 2/5] arm64: dts: ti: k3-j784s4-main: Add WIZ and SERDES PHY nodes Date: Thu, 5 Oct 2023 15:44:41 +0530 Message-ID: <20231005101444.229981-1-j-choudhary@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231005100027.228806-1-j-choudhary@ti.com> References: <20231005100027.228806-1-j-choudhary@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Siddharth Vadapalli J784S4 SoC has 4 Serdes instances along with their respective WIZ instances. Add device-tree nodes for them and disable them by default as the node is incomplete and phy link properties will be added in the platform dt file. Signed-off-by: Siddharth Vadapalli [j-choudhary@ti.com: fix serdes_wiz clock order & disable serdes refclk] Signed-off-by: Jayesh Choudhary --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 165 +++++++++++++++++++++ 1 file changed, 165 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index 6d9a5a91fa75..e20e26b76ffd 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -6,9 +6,20 @@ */ =20 #include +#include +#include =20 #include "k3-serdes.h" =20 +/ { + serdes_refclk: clock-serdes { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + /* To be enabled when serdes_wiz* is functional */ + status =3D "disabled"; + }; +}; + &cbass_main { msmc_ram: sram@70000000 { compatible =3D "mmio-sram"; @@ -709,6 +720,160 @@ main_sdhci1: mmc@4fb0000 { status =3D "disabled"; }; =20 + serdes_wiz0: wiz@5060000 { + compatible =3D "ti,j784s4-wiz-10g"; + #address-cells =3D <1>; + #size-cells =3D <1>; + power-domains =3D <&k3_pds 404 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 404 2>, <&k3_clks 404 6>, <&serdes_refclk>, <&k3_cl= ks 404 5>; + clock-names =3D "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; + assigned-clocks =3D <&k3_clks 404 6>; + assigned-clock-parents =3D <&k3_clks 404 10>; + num-lanes =3D <4>; + #reset-cells =3D <1>; + #clock-cells =3D <1>; + ranges =3D <0x5060000 0x00 0x5060000 0x10000>; + status =3D "disabled"; + + serdes0: serdes@5060000 { + compatible =3D "ti,j721e-serdes-10g"; + reg =3D <0x05060000 0x010000>; + reg-names =3D "torrent_phy"; + resets =3D <&serdes_wiz0 0>; + reset-names =3D "torrent_reset"; + clocks =3D <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; + clock-names =3D "refclk", "phy_en_refclk"; + assigned-clocks =3D <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents =3D <&k3_clks 404 6>, + <&k3_clks 404 6>, + <&k3_clks 404 6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #clock-cells =3D <1>; + status =3D "disabled"; + }; + }; + + serdes_wiz1: wiz@5070000 { + compatible =3D "ti,j784s4-wiz-10g"; + #address-cells =3D <1>; + #size-cells =3D <1>; + power-domains =3D <&k3_pds 405 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 405 2>, <&k3_clks 405 6>, <&serdes_refclk>, <&k3_cl= ks 405 5>; + clock-names =3D "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; + assigned-clocks =3D <&k3_clks 405 6>; + assigned-clock-parents =3D <&k3_clks 405 10>; + num-lanes =3D <4>; + #reset-cells =3D <1>; + #clock-cells =3D <1>; + ranges =3D <0x05070000 0x00 0x05070000 0x10000>; + status =3D "disabled"; + + serdes1: serdes@5070000 { + compatible =3D "ti,j721e-serdes-10g"; + reg =3D <0x05070000 0x010000>; + reg-names =3D "torrent_phy"; + resets =3D <&serdes_wiz1 0>; + reset-names =3D "torrent_reset"; + clocks =3D <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>; + clock-names =3D "refclk", "phy_en_refclk"; + assigned-clocks =3D <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz1 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents =3D <&k3_clks 405 6>, + <&k3_clks 405 6>, + <&k3_clks 405 6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #clock-cells =3D <1>; + status =3D "disabled"; + }; + }; + + serdes_wiz2: wiz@5020000 { + compatible =3D "ti,j784s4-wiz-10g"; + #address-cells =3D <1>; + #size-cells =3D <1>; + power-domains =3D <&k3_pds 406 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 406 2>, <&k3_clks 406 6>, <&serdes_refclk>, <&k3_cl= ks 406 5>; + clock-names =3D "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; + assigned-clocks =3D <&k3_clks 406 6>; + assigned-clock-parents =3D <&k3_clks 406 10>; + num-lanes =3D <4>; + #reset-cells =3D <1>; + #clock-cells =3D <1>; + ranges =3D <0x05020000 0x00 0x05020000 0x10000>; + status =3D "disabled"; + + serdes2: serdes@5020000 { + compatible =3D "ti,j721e-serdes-10g"; + reg =3D <0x05020000 0x010000>; + reg-names =3D "torrent_phy"; + resets =3D <&serdes_wiz2 0>; + reset-names =3D "torrent_reset"; + clocks =3D <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz2 TI_WIZ_PHY_EN_REFCLK>; + clock-names =3D "refclk", "phy_en_refclk"; + assigned-clocks =3D <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz2 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents =3D <&k3_clks 406 6>, + <&k3_clks 406 6>, + <&k3_clks 406 6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #clock-cells =3D <1>; + status =3D "disabled"; + }; + }; + + serdes_wiz4: wiz@5050000 { + compatible =3D "ti,j784s4-wiz-10g"; + #address-cells =3D <1>; + #size-cells =3D <1>; + power-domains =3D <&k3_pds 407 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 407 2>, <&k3_clks 407 6>, <&serdes_refclk>, <&k3_cl= ks 407 5>; + clock-names =3D "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; + assigned-clocks =3D <&k3_clks 407 6>; + assigned-clock-parents =3D <&k3_clks 407 10>; + num-lanes =3D <4>; + #reset-cells =3D <1>; + #clock-cells =3D <1>; + ranges =3D <0x05050000 0x00 0x05050000 0x10000>, + <0xa030a00 0x00 0xa030a00 0x40>; /* DPTX PHY */ + status =3D "disabled"; + + serdes4: serdes@5050000 { + /* + * Note: we also map DPTX PHY registers as the Torrent + * needs to manage those. + */ + compatible =3D "ti,j721e-serdes-10g"; + reg =3D <0x05050000 0x010000>, + <0x0a030a00 0x40>; /* DPTX PHY */ + reg-names =3D "torrent_phy"; + resets =3D <&serdes_wiz4 0>; + reset-names =3D "torrent_reset"; + clocks =3D <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz4 TI_WIZ_PHY_EN_REFCLK>; + clock-names =3D "refclk", "phy_en_refclk"; + assigned-clocks =3D <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz4 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents =3D <&k3_clks 407 6>, + <&k3_clks 407 6>, + <&k3_clks 407 6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #clock-cells =3D <1>; + status =3D "disabled"; + }; + }; + main_navss: bus@30000000 { bootph-all; compatible =3D "simple-bus"; --=20 2.25.1