From nobody Thu Dec 18 05:56:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81FD0E9270A for ; Thu, 5 Oct 2023 14:40:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237775AbjJEOjd (ORCPT ); Thu, 5 Oct 2023 10:39:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47528 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236259AbjJEOgv (ORCPT ); Thu, 5 Oct 2023 10:36:51 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 66FDE4F049 for ; Thu, 5 Oct 2023 07:02:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1696514563; x=1728050563; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; 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Thu, 5 Oct 2023 02:30:19 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Thu, 5 Oct 2023 02:30:13 -0700 From: Manikandan Muralidharan To: , , , , , , , , , CC: , , , , , , , Manikandan Muralidharan Subject: [PATCH v7 2/7] drm: atmel-hlcdc: add LCD controller layer definition for sam9x75 Date: Thu, 5 Oct 2023 14:59:49 +0530 Message-ID: <20231005092954.881059-3-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231005092954.881059-1-manikandan.m@microchip.com> References: <20231005092954.881059-1-manikandan.m@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the LCD controller layer definition and descriptor structure for sam9x75 for the following layers: - Base Layer - Overlay1 Layer - Overlay2 Layer - High End Overlay Signed-off-by: Manikandan Muralidharan --- drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 97 ++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c b/drivers/gpu/drm= /atmel-hlcdc/atmel_hlcdc_dc.c index fa0f9a93d50d..d30aec174aa2 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c @@ -462,6 +462,99 @@ static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc= _sam9x60 =3D { .layers =3D atmel_hlcdc_sam9x60_layers, }; =20 +static const struct atmel_hlcdc_layer_desc atmel_xlcdc_sam9x75_layers[] = =3D { + { + .name =3D "base", + .formats =3D &atmel_hlcdc_plane_rgb_formats, + .regs_offset =3D 0x60, + .id =3D 0, + .type =3D ATMEL_HLCDC_BASE_LAYER, + .cfgs_offset =3D 0x1c, + .layout =3D { + .xstride =3D { 2 }, + .default_color =3D 3, + .general_config =3D 4, + .disc_pos =3D 5, + .disc_size =3D 6, + }, + .clut_offset =3D 0x700, + }, + { + .name =3D "overlay1", + .formats =3D &atmel_hlcdc_plane_rgb_formats, + .regs_offset =3D 0x160, + .id =3D 1, + .type =3D ATMEL_HLCDC_OVERLAY_LAYER, + .cfgs_offset =3D 0x1c, + .layout =3D { + .pos =3D 2, + .size =3D 3, + .xstride =3D { 4 }, + .pstride =3D { 5 }, + .default_color =3D 6, + .chroma_key =3D 7, + .chroma_key_mask =3D 8, + .general_config =3D 9, + }, + .clut_offset =3D 0xb00, + }, + { + .name =3D "overlay2", + .formats =3D &atmel_hlcdc_plane_rgb_formats, + .regs_offset =3D 0x260, + .id =3D 2, + .type =3D ATMEL_HLCDC_OVERLAY_LAYER, + .cfgs_offset =3D 0x1c, + .layout =3D { + .pos =3D 2, + .size =3D 3, + .xstride =3D { 4 }, + .pstride =3D { 5 }, + .default_color =3D 6, + .chroma_key =3D 7, + .chroma_key_mask =3D 8, + .general_config =3D 9, + }, + .clut_offset =3D 0xf00, + }, + { + .name =3D "high-end-overlay", + .formats =3D &atmel_hlcdc_plane_rgb_and_yuv_formats, + .regs_offset =3D 0x360, + .id =3D 3, + .type =3D ATMEL_HLCDC_OVERLAY_LAYER, + .cfgs_offset =3D 0x30, + .layout =3D { + .pos =3D 2, + .size =3D 3, + .memsize =3D 4, + .xstride =3D { 5, 7 }, + .pstride =3D { 6, 8 }, + .default_color =3D 9, + .chroma_key =3D 10, + .chroma_key_mask =3D 11, + .general_config =3D 12, + .csc =3D 16, + .scaler_config =3D 23, + }, + .clut_offset =3D 0x1300, + }, +}; + +static const struct atmel_hlcdc_dc_desc atmel_xlcdc_dc_sam9x75 =3D { + .min_width =3D 0, + .min_height =3D 0, + .max_width =3D 2048, + .max_height =3D 2048, + .max_spw =3D 0xff, + .max_vpw =3D 0xff, + .max_hpw =3D 0x3ff, + .fixed_clksrc =3D true, + .is_xlcdc =3D true, + .nlayers =3D ARRAY_SIZE(atmel_xlcdc_sam9x75_layers), + .layers =3D atmel_xlcdc_sam9x75_layers, +}; + static const struct of_device_id atmel_hlcdc_of_match[] =3D { { .compatible =3D "atmel,at91sam9n12-hlcdc", @@ -487,6 +580,10 @@ static const struct of_device_id atmel_hlcdc_of_match[= ] =3D { .compatible =3D "microchip,sam9x60-hlcdc", .data =3D &atmel_hlcdc_dc_sam9x60, }, + { + .compatible =3D "microchip,sam9x75-xlcdc", + .data =3D &atmel_xlcdc_dc_sam9x75, + }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, atmel_hlcdc_of_match); --=20 2.25.1