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([2400:4050:c3e1:100:a16d:fce2:497:afb7]) by smtp.gmail.com with ESMTPSA id b18-20020a637152000000b005782ad723casm269265pgn.27.2023.10.04.19.59.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 19:59:33 -0700 (PDT) From: AKASHI Takahiro To: sudeep.holla@arm.com, cristian.marussi@arm.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org Cc: Oleksii_Moisieiev@epam.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, AKASHI Takahiro Subject: [RFC v2 4/5] gpio: add pinctrl based generic gpio driver Date: Thu, 5 Oct 2023 11:58:42 +0900 Message-Id: <20231005025843.508689-5-takahiro.akashi@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231005025843.508689-1-takahiro.akashi@linaro.org> References: <20231005025843.508689-1-takahiro.akashi@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Some pin controllers provide not only a method to set up lines but also gpio function. With this commit, a new generic gpio driver will be provided. It is implemented purely by using pinctrl interfaces. One of such pin controllers is Arm's SCMI. Signed-off-by: AKASHI Takahiro --- RFC v2 (Oct 5, 2023) * rename the driver to pin-control-gpio (CONFIG_GPIO_BY_PINCTRL) * return meaningful error codes instead of -1 * remove the masking at PIN_CONFIG_PACKED * handle emulated OPEN_DRAIN configuration at get_direction() * define config_set in gpio_chip * drop remove hook RFC (Oct 2, 2023) --- drivers/gpio/Kconfig | 7 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-by-pinctrl.c | 165 +++++++++++++++++++++++++++++++++ 3 files changed, 173 insertions(+) create mode 100644 drivers/gpio/gpio-by-pinctrl.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 673bafb8be58..a60972be114c 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -216,6 +216,13 @@ config GPIO_BRCMSTB help Say yes here to enable GPIO support for Broadcom STB (BCM7XXX) SoCs. =20 +config GPIO_BY_PINCTRL + tristate "GPIO support based on a pure pin control backend" + depends on GPIOLIB + help + Select this option to support GPIO devices based solely on pin + control, specifically pin configuration, such as SCMI. + config GPIO_CADENCE tristate "Cadence GPIO support" depends on OF_GPIO diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index eb73b5d633eb..71458d81e16a 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -43,6 +43,7 @@ obj-$(CONFIG_GPIO_BD71828) +=3D gpio-bd71828.o obj-$(CONFIG_GPIO_BD9571MWV) +=3D gpio-bd9571mwv.o obj-$(CONFIG_GPIO_BRCMSTB) +=3D gpio-brcmstb.o obj-$(CONFIG_GPIO_BT8XX) +=3D gpio-bt8xx.o +obj-$(CONFIG_GPIO_BY_PINCTRL) +=3D gpio-by-pinctrl.o obj-$(CONFIG_GPIO_CADENCE) +=3D gpio-cadence.o obj-$(CONFIG_GPIO_CLPS711X) +=3D gpio-clps711x.o obj-$(CONFIG_GPIO_SNPS_CREG) +=3D gpio-creg-snps.o diff --git a/drivers/gpio/gpio-by-pinctrl.c b/drivers/gpio/gpio-by-pinctrl.c new file mode 100644 index 000000000000..c297a9633e03 --- /dev/null +++ b/drivers/gpio/gpio-by-pinctrl.c @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2023 Linaro Inc. +// Author: AKASHI takahiro + +#include +#include +#include +#include +#include +#include +#include "gpiolib.h" + +struct pin_control_gpio_priv { + struct gpio_chip chip; +}; + +static int pin_control_gpio_get_direction(struct gpio_chip *chip, + unsigned int offset) +{ + unsigned long config; + bool out_en, in_en; + int ret; + + config =3D PIN_CONFIG_OUTPUT_ENABLE; + ret =3D pinctrl_gpio_get_config(chip->gpiodev->base + offset, &config); + if (!ret) + out_en =3D !!config; + else if (ret =3D=3D -EINVAL) + out_en =3D false; + else + return ret; + + config =3D PIN_CONFIG_INPUT_ENABLE; + ret =3D pinctrl_gpio_get_config(chip->gpiodev->base + offset, &config); + if (!ret) + in_en =3D !!config; + else if (ret =3D=3D -EINVAL) + in_en =3D false; + else + return ret; + + if (in_en && !out_en) + return GPIO_LINE_DIRECTION_IN; + + if (!in_en && out_en) + return GPIO_LINE_DIRECTION_OUT; + + if (in_en && out_en) { + /* This may be an emulation for output with open drain */ + config =3D PIN_CONFIG_DRIVE_OPEN_DRAIN; + ret =3D pinctrl_gpio_get_config(chip->gpiodev->base + offset, + &config); + if (!ret && config) + return GPIO_LINE_DIRECTION_OUT; + } + + return -EINVAL; +} + +static int pin_control_gpio_direction_input(struct gpio_chip *chip, + unsigned int offset) +{ + return pinctrl_gpio_direction_input(chip->gpiodev->base + offset); +} + +static int pin_control_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int val) +{ + return pinctrl_gpio_direction_output(chip->gpiodev->base + offset); +} + +static int pin_control_gpio_get(struct gpio_chip *chip, unsigned int offse= t) +{ + unsigned long config; + int ret; + + config =3D PIN_CONFIG_INPUT; + ret =3D pinctrl_gpio_get_config(chip->gpiodev->base + offset, &config); + if (ret) + return ret; + + if (config >> 8) + return 1; + + return 0; +} + +static void pin_control_gpio_set(struct gpio_chip *chip, unsigned int offs= et, + int val) +{ + unsigned long config; + + config =3D PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, val); + + pinctrl_gpio_set_config(chip->gpiodev->base + offset, config); +} + +static u16 sum_up_ngpios(struct gpio_chip *chip) +{ + struct gpio_pin_range *range; + struct gpio_device *gdev =3D chip->gpiodev; + u16 ngpios =3D 0; + + list_for_each_entry(range, &gdev->pin_ranges, node) { + ngpios +=3D range->range.npins; + } + + return ngpios; +} + +static int pin_control_gpio_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct pin_control_gpio_priv *priv; + struct gpio_chip *chip; + int ret; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + chip =3D &priv->chip; + chip->label =3D dev_name(dev); + chip->parent =3D dev; + chip->base =3D -1; + + chip->request =3D gpiochip_generic_request; + chip->free =3D gpiochip_generic_free; + chip->get_direction =3D pin_control_gpio_get_direction; + chip->direction_input =3D pin_control_gpio_direction_input; + chip->direction_output =3D pin_control_gpio_direction_output; + chip->get =3D pin_control_gpio_get; + chip->set =3D pin_control_gpio_set; + chip->set_config =3D gpiochip_generic_config; + + ret =3D devm_gpiochip_add_data(dev, chip, priv); + if (ret) + return ret; + + chip->ngpio =3D sum_up_ngpios(chip); + + platform_set_drvdata(pdev, priv); + + return 0; +} + +static const struct of_device_id pin_control_gpio_match[] =3D { + { .compatible =3D "pin-control-gpio" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, pin_control_gpio_match); + +static struct platform_driver pin_control_gpio_driver =3D { + .probe =3D pin_control_gpio_probe, + .driver =3D { + .name =3D "pin-control-gpio", + .of_match_table =3D pin_control_gpio_match, + }, +}; +module_platform_driver(pin_control_gpio_driver); + +MODULE_AUTHOR("AKASHI Takahiro "); +MODULE_DESCRIPTION("Pinctrl based GPIO driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1