From nobody Thu Dec 18 08:37:43 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C75A4E7AD57 for ; Tue, 3 Oct 2023 14:52:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240250AbjJCOwM (ORCPT ); Tue, 3 Oct 2023 10:52:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240227AbjJCOvj (ORCPT ); Tue, 3 Oct 2023 10:51:39 -0400 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 66B97EA for ; Tue, 3 Oct 2023 07:51:35 -0700 (PDT) Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-405361bb94eso10663025e9.0 for ; Tue, 03 Oct 2023 07:51:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20230601.gappssmtp.com; s=20230601; t=1696344694; x=1696949494; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PpGAZ8JK0NCFcy4HbqYTmEGAjLfb4Lc8h9XsT2EPYsE=; b=dSACUX21hIuF4pWREviicHqpZHEb6E9mveq26pi5uMOzCu06VPLxpFovs6E+ijHlEo GA4NYiHefH79BgN2FyamVMjpKGfOHFCjjsrYujzhuEqQ/WypO6xW0ZUGcPpy5XSBftLc MQlCODnjmYZvr+dfEuqEZaYZxkUxz4RMkVyCCXXx0MVvgAjzIrWGM6LADZHaIFK1r1sX wweA+WDfQpQWQMgJvJ7keS9+W1vZK1Zov9+vRwx9tiTyjGu/bCMMZCCTRNM6Du1GLi28 LBodzf+/cWZyUdTQlWA6wP5ATGobxPlZmHWrvJkVBZqb858tjxgSp9bSWmuvg9eEpes9 diVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696344694; x=1696949494; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PpGAZ8JK0NCFcy4HbqYTmEGAjLfb4Lc8h9XsT2EPYsE=; b=psvjvLMHKaNteQSI88KnsquEv/phcisA4wNdZAujM5iMae5IniVDH+vSq2MKCnh7/I 8mDZpIogTrp9mJGmtFJRB7NX9THAbiAZDC6wE+9L/Lgw0MdLb0pvcxWj3iKUagddOmCs lzQXC+XlhJZQYy6dEWuaUeCGcE5i+eUNK5CewB76iB6HUOH0IS/f6y7AlPGi/UNhiLTS lP79G5714SyVmlikpXXJnrO4TGsORaYsroS649ZQgDY+l+7q5vfkVzSJ1NZSLKrRqApL al4IFyweWmUNz1o+O4/JT93+45RQmU1OlMhbgv97TZp9SFfaCoy1LGPYRXmCHOeZzy4X mMyA== X-Gm-Message-State: AOJu0YxPt+FQwOotw4q8EICB90TaSB+45dPTAurLwNawSkEaNHP/tqAi TOFpUgW/k6TsV1CWXBx9fU2/Yg== X-Google-Smtp-Source: AGHT+IHdW9L9rksYKP5d4TTPkLpphBpvyDRVGz3n8Q2jQ9lwKMXvOj/DhFHduzGRMB1gMl7fCPbUkA== X-Received: by 2002:a7b:c7d2:0:b0:405:48ba:9c with SMTP id z18-20020a7bc7d2000000b0040548ba009cmr13654280wmk.16.1696344693886; Tue, 03 Oct 2023 07:51:33 -0700 (PDT) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:1f2d:3479:a5de:fa35]) by smtp.gmail.com with ESMTPSA id c15-20020a05600c0acf00b003fe29f6b61bsm1462773wmr.46.2023.10.03.07.51.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Oct 2023 07:51:33 -0700 (PDT) From: Bartosz Golaszewski To: Linus Walleij , Andy Shevchenko Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski , Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org Subject: [PATCH 14/36] pinctrl: renesas: use new pinctrl GPIO helpers Date: Tue, 3 Oct 2023 16:50:52 +0200 Message-Id: <20231003145114.21637-15-brgl@bgdev.pl> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231003145114.21637-1-brgl@bgdev.pl> References: <20231003145114.21637-1-brgl@bgdev.pl> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Bartosz Golaszewski Replace the pinctrl helpers taking the global GPIO number as argument with the improved variants that instead take a pointer to the GPIO chip and the controller-relative offset. Signed-off-by: Bartosz Golaszewski Acked-by: Geert Uytterhoeven Reviewed-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/gpio.c | 8 ++++---- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 4 ++-- drivers/pinctrl/renesas/pinctrl-rzv2m.c | 4 ++-- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/renesas/gpio.c b/drivers/pinctrl/renesas/gpio.c index 5758daf94fe2..e7771a57e6d1 100644 --- a/drivers/pinctrl/renesas/gpio.c +++ b/drivers/pinctrl/renesas/gpio.c @@ -135,12 +135,12 @@ static int gpio_pin_request(struct gpio_chip *gc, uns= igned offset) if (idx < 0 || pfc->info->pins[idx].enum_id =3D=3D 0) return -EINVAL; =20 - return pinctrl_gpio_request(gc->base + offset); + return pinctrl_gpio_request_new(gc, offset); } =20 static void gpio_pin_free(struct gpio_chip *gc, unsigned offset) { - return pinctrl_gpio_free(gc->base + offset); + return pinctrl_gpio_free_new(gc, offset); } =20 static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset, @@ -164,7 +164,7 @@ static void gpio_pin_set_value(struct sh_pfc_chip *chip= , unsigned offset, =20 static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset) { - return pinctrl_gpio_direction_input(gc->base + offset); + return pinctrl_gpio_direction_input_new(gc, offset); } =20 static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset, @@ -172,7 +172,7 @@ static int gpio_pin_direction_output(struct gpio_chip *= gc, unsigned offset, { gpio_pin_set_value(gpiochip_get_data(gc), offset, value); =20 - return pinctrl_gpio_direction_output(gc->base + offset); + return pinctrl_gpio_direction_output_new(gc, offset); } =20 static int gpio_pin_get(struct gpio_chip *gc, unsigned offset) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 03b36c6b2b6d..b9195fff0abd 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -801,7 +801,7 @@ static int rzg2l_gpio_request(struct gpio_chip *chip, u= nsigned int offset) u8 reg8; int ret; =20 - ret =3D pinctrl_gpio_request(chip->base + offset); + ret =3D pinctrl_gpio_request_new(chip, offset); if (ret) return ret; =20 @@ -920,7 +920,7 @@ static void rzg2l_gpio_free(struct gpio_chip *chip, uns= igned int offset) { unsigned int virq; =20 - pinctrl_gpio_free(chip->base + offset); + pinctrl_gpio_free_new(chip, offset); =20 virq =3D irq_find_mapping(chip->irq.domain, offset); if (virq) diff --git a/drivers/pinctrl/renesas/pinctrl-rzv2m.c b/drivers/pinctrl/rene= sas/pinctrl-rzv2m.c index 52aeafaba4b6..3d29c77a5aad 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzv2m.c +++ b/drivers/pinctrl/renesas/pinctrl-rzv2m.c @@ -754,7 +754,7 @@ static int rzv2m_gpio_request(struct gpio_chip *chip, u= nsigned int offset) u8 bit =3D RZV2M_PIN_ID_TO_PIN(offset); int ret; =20 - ret =3D pinctrl_gpio_request(chip->base + offset); + ret =3D pinctrl_gpio_request_new(chip, offset); if (ret) return ret; =20 @@ -832,7 +832,7 @@ static int rzv2m_gpio_get(struct gpio_chip *chip, unsig= ned int offset) =20 static void rzv2m_gpio_free(struct gpio_chip *chip, unsigned int offset) { - pinctrl_gpio_free(chip->base + offset); + pinctrl_gpio_free_new(chip, offset); =20 /* * Set the GPIO as an input to ensure that the next GPIO request won't --=20 2.39.2