From nobody Wed Jan 7 03:31:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6395E784B3 for ; Mon, 2 Oct 2023 13:18:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237400AbjJBNSH (ORCPT ); Mon, 2 Oct 2023 09:18:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59278 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237359AbjJBNR6 (ORCPT ); Mon, 2 Oct 2023 09:17:58 -0400 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::228]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 92DF6D9; Mon, 2 Oct 2023 06:17:54 -0700 (PDT) Received: by mail.gandi.net (Postfix) with ESMTPSA id 78A041BF211; Mon, 2 Oct 2023 13:17:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1696252672; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=i7v32YcvbtKkSJ6srCUo4fO3a6wW8xsgEHf4MdRd9fI=; b=Jv8P35xM3G4fXx7JgcG2Da0TXIVsgzHvLMfuRfHn/jbHcHUi4gQrgW+ety+Vpty+xxh1MF BdT9SzwYIQG/IS1beObVyXa3lSu7QvWDXJtzvfOQh6vWXzIQ5h7jYwPp+kKAdU++uXs690 LiCYnrvnYfOA8v5a7ig+jyUjnJP2xNRAuqkiTgqGxtN3aVLyO4tKcTeCyJ7upUc61a6SNx aFzHd6M2Ejd481iPcyCDwbesZLMfk7uZJF6IkgVZXsqM6cilX7dk9iwAQlGXaYyJz6Busk MNixVt1qBTx4Y9GmEwU2fgQmf6E6nLhV18WPg32126x1k0Yu4ig78JN2L4mF/Q== From: =?UTF-8?q?K=C3=B6ry=20Maincent?= To: Cai Huoqing , Manivannan Sadhasivam , Serge Semin , Vinod Koul , Gustavo Pimentel , dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Thomas Petazzoni , Gustavo Pimentel , Herve Codina , Kory Maincent Subject: [PATCH v2 1/5] dmaengine: dw-edma: Fix the ch_count hdma callback Date: Mon, 2 Oct 2023 15:17:45 +0200 Message-Id: <20231002131749.2977952-2-kory.maincent@bootlin.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231002131749.2977952-1-kory.maincent@bootlin.com> References: <20231002131749.2977952-1-kory.maincent@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: kory.maincent@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Kory Maincent The current check of ch_en enabled to know the maximum number of available hardware channels is wrong as it check the number of ch_en register set but all of them are unset at probe. This register is set at the dw_hdma_v0_core_start function which is run lately before a DMA transfer. The HDMA IP have no way to know the number of hardware channels available like the eDMA IP, then let set it to maximum channels and let the platform set the right number of channels. Fixes: e74c39573d35 ("dmaengine: dw-edma: Add support for native HDMA") Signed-off-by: Kory Maincent Acked-by: Manivannan Sadhasivam --- See the following thread mail that talk about this issue: https://lore.kernel.org/lkml/20230607095832.6d6b1a73@kmaincent-XPS-13-7390/ Changes in v2: - Add comment --- drivers/dma/dw-edma/dw-hdma-v0-core.c | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw= -hdma-v0-core.c index 00b735a0202a..3e78d4fd3955 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c @@ -65,18 +65,11 @@ static void dw_hdma_v0_core_off(struct dw_edma *dw) =20 static u16 dw_hdma_v0_core_ch_count(struct dw_edma *dw, enum dw_edma_dir d= ir) { - u32 num_ch =3D 0; - int id; - - for (id =3D 0; id < HDMA_V0_MAX_NR_CH; id++) { - if (GET_CH_32(dw, id, dir, ch_en) & BIT(0)) - num_ch++; - } - - if (num_ch > HDMA_V0_MAX_NR_CH) - num_ch =3D HDMA_V0_MAX_NR_CH; - - return (u16)num_ch; + /* The HDMA IP have no way to know the number of hardware channels + * available, we set it to maximum channels and let the platform + * set the right number of channels. + */ + return HDMA_V0_MAX_NR_CH; } =20 static enum dma_status dw_hdma_v0_core_ch_status(struct dw_edma_chan *chan) --=20 2.25.1